1csx_Parse_CISTPL_CFTABLE_EKNeTrRnYe(l9FF)unctions forcsDxr_iPvaerrsse_CISTPL_CFTABLE_ENTRY(9F)
2
6 csx_Parse_CISTPL_CFTABLE_ENTRY - parse 16-bit Card Configuration Table
7 Entry tuple
8
10 #include <sys/pccard.h>
11 int32_t csx_Parse_CISTPL_CFTABLE_ENTRY(client_handle_t ch, tuple_t *tu,
15 cistpl_cftable_entry_t *cft);
16
19 Solaris DDI Specific (Solaris DDI)
20
22 ch Client handle returned from csx_RegisterClient(9F).
23 tu Pointer to a tuple_t structure (see tuple(9S)) returned by a
26 call to csx_GetFirstTuple(9F) or csx_GetNextTuple(9F).
27 cft Pointer to a cistpl_cftable_entry_t structure which contains the
30 parsed CISTPL_CFTABLE_ENTRY tuple information upon return from
31 this function.
32
35 This function parses the 16 bit Card Configuration Table Entry tuple,
36 CISTPL_CFTABLE_ENTRY, into a form usable by PC Card drivers.
37 The CISTPL_CFTABLE_ENTRY tuple is used to describe each possible con‐
40 figuration of a PC Card and to distinguish among the permitted configu‐
41 rations. The CISTPL_CONFIG tuple must precede all CISTPL_CFTABLE_ENTRY
42 tuples.
43
45 The structure members of cistpl_cftable_entry_t are:
46 uint32_t flags; /* valid descriptions */
48 uint32_t ifc; /* interface description */
49 /* information */
50 uint32_t pin; /* values for PRR */
51 uint32_t index; /* configuration index number */
52 cistpl_cftable_entry_pd_t pd; /* power requirements */
53 /* description */
54 cistpl_cftable_entry_speed_t speed; /* device speed description */
55 cistpl_cftable_entry_io_t io; /* device I/O map */
56 cistpl_cftable_entry_irq_t irq; /* device IRQ utilization */
57 cistpl_cftable_entry_mem_t mem; /* device memory space */
58 cistpl_cftable_entry_misc_t misc; /* miscellaneous
59 /* device features */
60 The flags field is defined and bit-mapped as follows:
64 CISTPL_CFTABLE_TPCE_DEFAULT
66 This is a default configuration
68 CISTPL_CFTABLE_TPCE_IF
71 If configuration byte exists
73 CISTPL_CFTABLE_TPCE_FS_PWR
76 Power information exists
78 CISTPL_CFTABLE_TPCE_FS_TD
81 Timing information exists
83 CISTPL_CFTABLE_TPCE_FS_IO
86 I/O information exists
88 CISTPL_CFTABLE_TPCE_FS_IRQ
91 IRQ information exists
93 CISTPL_CFTABLE_TPCE_FS_MEM
96 MEM space information exists
98 CISTPL_CFTABLE_TPCE_FS_MISC
101 MISC information exists
103 CISTPL_CFTABLE_TPCE_FS_STCE_EV
106 STCE_EV exists
108 CISTPL_CFTABLE_TPCE_FS_STCE_PD
111 STCE_PD exists
113 If the CISTPL_CFTABLE_TPCE_IF flag is set, the ifc field is bit-mapped
117 and defined as follows:
118 CISTPL_CFTABLE_TPCE_IF_MEMORY
120 Memory interface
122 CISTPL_CFTABLE_TPCE_IF_IO_MEM
125 IO and memory
127 CISTPL_CFTABLE_TPCE_IF_CUSTOM_0
130 Custom interface 0
132 CISTPL_CFTABLE_TPCE_IF_CUSTOM_1
135 Custom interface 1
137 CISTPL_CFTABLE_TPCE_IF_CUSTOM_2
140 Custom interface 2
142 CISTPL_CFTABLE_TPCE_IF_CUSTOM_3
145 Custom interface 3
147 CISTPL_CFTABLE_TPCE_IF_MASK
150 Interface type mask
152 CISTPL_CFTABLE_TPCE_IF_BVD
155 BVD active in PRR
157 CISTPL_CFTABLE_TPCE_IF_WP
160 WP active in PRR
162 CISTPL_CFTABLE_TPCE_IF_RDY
165 RDY active in PRR
167 CISTPL_CFTABLE_TPCE_IF_MWAIT
170 WAIT - mem cycles
172 pin is a value for the Pin Replacement Register.
176 index is a configuration index number.
179 The structure members of cistpl_cftable_entry_pd_t are:
182 uint32_t flags; /* which descriptions are valid */
184 cistpl_cftable_entry_pwr_t pd_vcc; /* VCC power description */
185 cistpl_cftable_entry_pwr_t pd_vpp1; /* Vpp1 power description */
186 cistpl_cftable_entry_pwr_t pd_vpp2; /* Vpp2 power description */
187 This flags field is bit-mapped and defined as follows:
191 CISTPL_CFTABLE_TPCE_FS_PWR_VCC
193 Vcc description valid
195 CISTPL_CFTABLE_TPCE_FS_PWR_VPP1
198 Vpp1 description valid
200 CISTPL_CFTABLE_TPCE_FS_PWR_VPP2
203 Vpp2 description valid
205 The structure members of cistpl_cftable_entry_pwr_t are:
209 uint32_t nomV; /* nominal supply voltage */
211 uint32_t nomV_flags;
212 uint32_t minV; /* minimum supply voltage */
213 uint32_t minV_flags;
214 uint32_t maxV; /* maximum supply voltage */
215 uint32_t maxV_flags;
216 uint32_t staticI; /* continuous supply current */
217 uint32_t staticI_flags;
218 uint32_t avgI; /* max current required averaged over 1 sec. */
219 uint32_t avgI_flags;
220 uint32_t peakI; /* max current required averaged over 10mS */
221 uint32_t peakI_flags;
222 uint32_t pdownI; /* power down supply current required */
223 uint32_t pdownI_flags;
224 nomV, minV, maxV, staticI, avgI, peakI_flag, and pdownI are defined
228 and bit-mapped as follows:
229 CISTPL_CFTABLE_PD_NOMV Nominal supply voltage
231 CISTPL_CFTABLE_PD_MINV Minimum supply voltage
234 CISTPL_CFTABLE_PD_MAXV Maximum supply voltage
237 CISTPL_CFTABLE_PD_STATICI Continuous supply current
240 CISTPL_CFTABLE_PD_AVGI Maximum current required averaged
243 over 1 second
244 CISTPL_CFTABLE_PD_PEAKI Maximum current required averaged
247 over 10mS
248 CISTPL_CFTABLE_PD_PDOWNI Power down supply current required
251 nomV_flags, minV_flags, maxV_flags, staticI_flags, avgI_flags,
255 peakI_flags, and pdownI_flags are defined and bit-mapped as follows:
256 CISTPL_CFTABLE_PD_EXISTS This parameter exists
258 CISTPL_CFTABLE_PD_MUL10 Multiply return value by 10
261 CISTPL_CFTABLE_PD_NC_SLEEP No connection on sleep/power down
264 CISTPL_CFTABLE_PD_ZERO Zero value required
267 CISTPL_CFTABLE_PD_NC No connection ever
270 The structure members of cistpl_cftable_entry_speed_t are:
274 uint32_t flags; /* which timing information is present */
276 uint32_t wait; /* max WAIT time in device speed format */
277 uint32_t nS_wait; /* max WAIT time in nS */
278 uint32_t rdybsy; /* max RDY/BSY time in device speed format */
279 uint32_t nS_rdybsy; /* max RDY/BSY time in nS */
280 uint32_t rsvd; /* max RSVD time in device speed format */
281 uint32_t nS_rsvd; /* max RSVD time in nS */
282 The flags field is bit-mapped and defined as follows:
286 CISTPL_CFTABLE_TPCE_FS_TD_WAIT
288 WAIT timing exists
290 CISTPL_CFTABLE_TPCE_FS_TD_RDY
293 RDY/BSY timing exists
295 CISTPL_CFTABLE_TPCE_FS_TD_RSVD
298 RSVD timing exists
300 The structure members of cistpl_cftable_entry_io_t are:
304 uint32_t flags; /* direct copy of TPCE_IO byte in tuple */
306 uint32_t addr_lines; /* number of decoded I/O address lines */
307 uint32_t ranges; /* number of I/O ranges */
308 cistpl_cftable_entry_io_range_t
309 range[CISTPL_CFTABLE_ENTRY_MAX_IO_RANGES];
310 The flags field is defined and bit-mapped as follows:
314 CISTPL_CFTABLE_TPCE_FS_IO_BUS
316 Bus width mask
318 CISTPL_CFTABLE_TPCE_FS_IO_BUS8
321 8-bit flag
323 CISTPL_CFTABLE_TPCE_FS_IO_BUS16
326 16-bit flag
328 CISTPL_CFTABLE_TPCE_FS_IO_RANGE
331 IO address ranges exist
333 The structure members of cistpl_cftable_entry_io_range_t are:
337 uint32_t addr; /* I/O start address */
339 uint32_t length; /* I/O register length */
340 The structure members of cistpl_cftable_entry_irq_t are:
344 uint32_t flags; /* direct copy of TPCE_IR byte in tuple */
346 uint32_t irqs; /* bit mask for each allowed IRQ */
347 The structure members of cistpl_cftable_entry_mem_t are:
351 uint32_t flags; /* memory descriptor type and host addr info */
353 uint32_t windows; /* number of memory space descriptors */
354 cistpl_cftable_entry_mem_window_t
355 window[CISTPL_CFTABLE_ENTRY_MAX_MEM_WINDOWS];
356 The flags field is defined and bit-mapped as follows:
360 CISTPL_CFTABLE_TPCE_FS_MEM3
362 Space descriptors
364 CISTPL_CFTABLE_TPCE_FS_MEM2
367 host_addr=card_addr
369 CISTPL_CFTABLE_TPCE_FS_MEM1
372 Card address=0 any host address
374 CISTPL_CFTABLE_TPCE_FS_MEM_HOST
377 If host address is present in MEM3
379 The structure members of cistpl_cftable_entry_mem_window_t are:
383 uint32_t length; /* length of this window */
385 uint32_t card_addr; /* card address */
386 uint32_t host_addr; /* host address */
387 The structure members of cistpl_cftable_entry_misc_t are:
391 uint32_t flags; /* miscellaneous features flags */
393 The flags field is defined and bit-mapped as follows:
397 CISTPL_CFTABLE_TPCE_MI_MTC_MASK
399 Max twin cards mask
401 CISTPL_CFTABLE_TPCE_MI_AUDIO
404 Audio on BVD2
406 CISTPL_CFTABLE_TPCE_MI_READONLY
409 R/O storage
411 CISTPL_CFTABLE_TPCE_MI_PWRDOWN
414 Powerdown capable
416 CISTPL_CFTABLE_TPCE_MI_DRQ_MASK
419 DMAREQ mask
421 CISTPL_CFTABLE_TPCE_MI_DRQ_SPK
424 DMAREQ on SPKR
426 CISTPL_CFTABLE_TPCE_MI_DRQ_IOIS
429 DMAREQ on IOIS16
431 CISTPL_CFTABLE_TPCE_MI_DRQ_INP
434 DMAREQ on INPACK
436 CISTPL_CFTABLE_TPCE_MI_DMA_8
439 DMA width 8 bits
441 CISTPL_CFTABLE_TPCE_MI_DMA_16
444 DMA width 16 bits
446
449 CS_SUCCESS Successful operation.
450 CS_BAD_HANDLE Client handle is invalid.
453 CS_UNKNOWN_TUPLE Parser does not know how to parse tuple.
456 CS_NO_CARD No PC Card in socket.
459 CS_NO_CIS No Card Information Structure (CIS) on PC
462 Card.
463 CS_UNSUPPORTED_FUNCTION No PCMCIA hardware installed.
466
469 This function may be called from user or kernel context.
470
472 csx_GetFirstTuple(9F), csx_GetTupleData(9F), csx_Parse_CISTPL_CON‐
473 FIG(9F), csx_RegisterClient(9F), csx_ValidateCIS(9F), tuple(9S)
474 PC Card 95 Standard, PCMCIA/JEIDA
477SunOS 5.11 20 Dec 1996csx_Parse_CISTPL_CFTABLE_ENTRY(9F)