1ddi_dma_lim_sparc(9S) Data Structures for Drivers ddi_dma_lim_sparc(9S)
2
6 ddi_dma_lim_sparc, ddi_dma_lim - SPARC DMA limits structure
7
9 #include <sys/ddidmareq.h>
10
13 Solaris SPARC DDI specific (Solaris SPARC DDI). These interfaces are
14 obsolete.
15
17 This page describes the SPARC version of the ddi_dma_lim structure. See
18 ddi_dma_lim_x86(9S) for a description of the x86 version of this struc‐
19 ture.
20 A ddi_dma_lim structure describes in a generic fashion the possible
23 limitations of a device's DMA engine. This information is used by the
24 system when it attempts to set up DMA resources for a device.
25
27 uint_t dlim_addr_lo; /* low range of 32 bit
28 addressing capability */
29 uint_t dlim_addr_hi; /* inclusive upper bound of address.
30 capability */
31 uint_t dlim_cntr_max; /* inclusive upper bound of
32 dma engine address limit * /
33 uint_t dlim_burstsizes; /* binary encoded dma burst sizes */
34 uint_t dlim_minxfer; /* minimum effective dma xfer size */
35 uint_t dlim_dmaspeed; /* average dma data rate (kb/s) */
36 The dlim_addr_lo and dlim_addr_hi fields specify the address range the
40 device's DMA engine can access. The dlim_addr_lo field describes the
41 lower 32-bit boundary of the device's DMA engine, the dlim_addr_hi
42 describes the inclusive upper 32-bit boundary. The system allocates DMA
43 resources in a way that the address for programming the device's DMA
44 engine (see ddi_dma_cookie(9S) or ddi_dma_htoc(9F)) is within this
45 range. For example, if your device can access the whole 32-bit address
46 range, you may use [0,0xFFFFFFFF]. If your device has just a 16-bit
47 address register but will access the top of the 32-bit address range,
48 then [0xFFFF0000,0xFFFFFFFF] is the right limit.
49 The dlim_cntr_max field describes an inclusive upper bound for the
52 device's DMA engine address register. This handles a fairly common case
53 where a portion of the address register is only a latch rather than a
54 full register. For example, the upper 8 bits of a 32-bit address regis‐
55 ter can be a latch. This splits the address register into a portion
56 that acts as a true address register (24 bits) for a 16 Mbyte segment
57 and a latch (8 bits) to hold a segment number. To describe these lim‐
58 its, specify 0xFFFFFF in the dlim_cntr_max structure.
59 The dlim_burstsizes field describes the possible burst sizes the
62 device's DMA engine can accept. At the time of a DMA resource request,
63 this element defines the possible DMA burst cycle sizes that the
64 requester's DMA engine can handle. The format of the data is binary
65 encoding of burst sizes assumed to be powers of two. That is, if a DMA
66 engine is capable of doing 1-, 2-, 4-, and 16-byte transfers, the
67 encoding ix 0x17. If the device is an SBus device and can take advan‐
68 tage of a 64-bit SBus, the lower 16 bits are used to specify the burst
69 size for 32-bit transfers and the upper 16 bits are used to specify the
70 burst size for 64-bit transfers. As the resource request is handled by
71 the system, the burstsizes value can be modified. Prior to enabling DMA
72 for the specific device, the driver that owns the DMA engine should
73 check (using ddi_dma_burstsizes(9F)) what the allowed burstsizes have
74 become and program the DMA engine appropriately.
75 The dlim_minxfer field describes the minimum effective DMA transfer
78 size (in units of bytes). It must be a power of two. This value speci‐
79 fies the minimum effective granularity of the DMA engine. It is dis‐
80 tinct from dlim_burstsizes in that it describes the minimum amount of
81 access a DMA transfer will effect. dlim_burstsizes describes in what
82 electrical fashion the DMA engine might perform its accesses, while
83 dlim_minxfer describes the minimum amount of memory that can be touched
84 by the DMA transfer. As a resource request is handled by the system,
85 the dlim_minxfer value can be modified contingent upon the presence
86 (and use) of I/O caches and DMA write buffers in between the DMA engine
87 and the object that DMA is being performed on. After DMA resources have
88 been allocated, the resultant minimum transfer value can be gotten
89 using ddi_dma_devalign(9F).
90 The field dlim_dmaspeed is the expected average data rate for the DMA
93 engine (in units of kilobytes per second). Note that this should not be
94 the maximum, or peak, burst data rate, but a reasonable guess as to the
95 average throughput. This field is entirely optional and can be left as
96 zero. Its intended use is to provide some hints about how much of the
97 DMA resource this device might need.
98
100 See attributes(5) for descriptions of the following attributes:
101 ┌─────────────────────────────┬─────────────────────────────┐
106 │ ATTRIBUTE TYPE │ ATTRIBUTE VALUE │
107 ├─────────────────────────────┼─────────────────────────────┤
108 │Interface Stability │Obsolete │
109 └─────────────────────────────┴─────────────────────────────┘
110
112 ddi_dma_addr_setup(9F), ddi_dma_buf_setup(9F), ddi_dma_burstsizes(9F),
113 ddi_dma_devalign(9F), ddi_dma_htoc(9F), ddi_dma_setup(9F),
114 ddi_dma_cookie(9S), ddi_dma_lim_x86(9S), ddi_dma_req(9S)
115SunOS 5.11 12 Oct 2005 ddi_dma_lim_sparc(9S)