1Netlist::Module(3) User Contributed Perl Documentation Netlist::Module(3)
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6 Verilog::Netlist::Module - Module within a Verilog Netlist
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9 use Verilog::Netlist;
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11 ...
12 my $module = $netlist->find_module('modname');
13 my $cell = $self->find_cell('name')
14 my $port = $self->find_port('name')
15 my $net = $self->find_net('name')
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18 A Verilog::Netlist::Module object is created by Verilog::Netlist for
19 every module, macromodule, primitive or program in the design.
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22 See also Verilog::Netlist::Subclass for additional accessors and
23 methods.
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25 $self->cells
26 Returns list of references to Verilog::Netlist::Cell in the module.
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28 $self->cells_sorted
29 Returns list of name sorted references to Verilog::Netlist::Cell in
30 the module.
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32 $self->comment
33 Returns any comments following the definition. keep_comments=>1
34 must be passed to Verilog::Netlist::new for comments to be
35 retained.
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37 $self->find_port_by_index
38 Returns the port name associated with the given index. Indexes
39 start at 1 (pin numbers are traditionally counted from pin 1..pin
40 N, not starting at zero. This was probably an unfortunate choice,
41 sorry.)
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43 $self->is_top
44 Returns true if the module has no cells referencing it (is at the
45 top of the hierarchy.)
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47 $self->keyword
48 Returns the keyword used to declare the module ("module",
49 "macromodule", "primitive" or "program".) It might at first not
50 seem obvious that programs are considered modules, but in most
51 cases they contain the same type of objects so can be handled
52 identically.
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54 $self->name
55 The name of the module.
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57 $self->netlist
58 Reference to the Verilog::Netlist the module is under.
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60 $self->nets
61 Returns list of references to Verilog::Netlist::Net in the module.
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63 $self->nets_sorted
64 Returns list of name sorted references to Verilog::Netlist::Net in
65 the module.
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67 $self->nets_and_ports_sorted
68 Returns list of name sorted references to Verilog::Netlist::Net and
69 Verilog::Netlist::Port in the module.
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71 $self->ports
72 Returns list of references to Verilog::Netlist::Port in the module.
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74 $self->ports_ordered
75 Returns list of references to Verilog::Netlist::Port in the module
76 sorted by pin number.
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78 $self->ports_sorted
79 Returns list of references to Verilog::Netlist::Port in the module
80 sorted by name.
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83 See also Verilog::Netlist::Subclass for additional accessors and
84 methods.
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86 $self->autos
87 Updates the AUTOs for the module.
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89 $self->find_cell(name)
90 Returns Verilog::Netlist::Cell matching given name.
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92 $self->find_port(name)
93 Returns Verilog::Netlist::Port matching given name.
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95 $self->find_net(name)
96 Returns Verilog::Netlist::Net matching given name.
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98 $self->level
99 Returns the reverse depth of this module with respect to other
100 modules. Leaf modules (modules with no cells) will be level 1.
101 Modules which instantiate cells of level 1 will be level 2 modules
102 and so forth. See also Netlist's modules_sorted_level.
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104 $self->lint
105 Checks the module for errors.
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107 $self->link
108 Creates interconnections between this module and other modules.
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110 $self->modulename_from_filename
111 Uses a rough algorithm (drop the extension) to convert a filename
112 to the module that is expected to be inside it.
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114 $self->new_cell
115 Creates a new Verilog::Netlist::Cell.
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117 $self->new_port
118 Creates a new Verilog::Netlist::Port.
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120 $self->new_net
121 Creates a new Verilog::Netlist::Net.
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123 $self->dump
124 Prints debugging information for this module.
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126 $self->verilog_text
127 Returns verilog code which represents this module. Returned as an
128 array that must be joined together to form the final text string.
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131 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
132 software tool suite. The latest version is available from CPAN and
133 from http://www.veripool.org/verilog-perl
134 <http://www.veripool.org/verilog-perl>.
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136 Copyright 2000-2009 by Wilson Snyder. This package is free software;
137 you can redistribute it and/or modify it under the terms of either the
138 GNU Lesser General Public License Version 3 or the Perl Artistic
139 License Version 2.0.
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142 Wilson Snyder <wsnyder@wsnyder.org>
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145 Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
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149perl v5.12.0 2009-07-20 Netlist::Module(3)