Verilog::Netlist::Module(3pm)

1Netlist::Module(3)    User Contributed Perl Documentation   Netlist::Module(3)
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NAME

6       Verilog::Netlist::Module - Module within a Verilog Netlist
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SYNOPSIS

9         use Verilog::Netlist;
10
11         ...
12         my $module = $netlist->find_module('modname');
13         my $cell = $self->find_cell('name')
14         my $port =  $self->find_port('name')
15         my $net =  $self->find_net('name')
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DESCRIPTION

18       A Verilog::Netlist::Module object is created by Verilog::Netlist for
19       every module, macromodule, primitive or program in the design.
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ACCESSORS

22       See also Verilog::Netlist::Subclass for additional accessors and
23       methods.
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25       $self->cells
26           Returns list of references to Verilog::Netlist::Cell in the module.
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28       $self->cells_sorted
29           Returns list of name sorted references to Verilog::Netlist::Cell in
30           the module.
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32       $self->comment
33           Returns any comments following the definition.  keep_comments=>1
34           must be passed to Verilog::Netlist::new for comments to be
35           retained.
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37       $self->find_port_by_index
38           Returns the port name associated with the given index.  Indexes
39           start at 1 (pin numbers are traditionally counted from pin 1..pin
40           N, not starting at zero.  This was probably an unfortunate choice,
41           sorry.)
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43       $self->is_top
44           Returns true if the module has no cells referencing it (is at the
45           top of the hierarchy.)
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47       $self->keyword
48           Returns the keyword used to declare the module ("module",
49           "macromodule", "primitive" or "program".)  It might at first not
50           seem obvious that programs are considered modules, but in most
51           cases they contain the same type of objects so can be handled
52           identically.
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54       $self->name
55           The name of the module.
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57       $self->netlist
58           Reference to the Verilog::Netlist the module is under.
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60       $self->nets
61           Returns list of references to Verilog::Netlist::Net in the module.
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63       $self->nets_sorted
64           Returns list of name sorted references to Verilog::Netlist::Net in
65           the module.
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67       $self->nets_and_ports_sorted
68           Returns list of name sorted references to Verilog::Netlist::Net and
69           Verilog::Netlist::Port in the module.
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71       $self->ports
72           Returns list of references to Verilog::Netlist::Port in the module.
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74       $self->ports_ordered
75           Returns list of references to Verilog::Netlist::Port in the module
76           sorted by pin number.
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78       $self->ports_sorted
79           Returns list of references to Verilog::Netlist::Port in the module
80           sorted by name.
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82       $self->statements
83           Returns list of references to Verilog::Netlist::ContAssign in the
84           module.  Other statement types (Always, etc) may also be added to
85           this list in the future.
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87       $self->statements_sorted
88           Returns list of name sorted references to
89           Verilog::Netlist::ContAssign in the module.  Other statement types
90           (Always, etc) may also be added to this list in the future.
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MEMBER FUNCTIONS

93       See also Verilog::Netlist::Subclass for additional accessors and
94       methods.
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96       $self->find_cell(name)
97           Returns Verilog::Netlist::Cell matching given name.
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99       $self->find_port(name)
100           Returns Verilog::Netlist::Port matching given name.
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102       $self->find_net(name)
103           Returns Verilog::Netlist::Net matching given name.
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105       $self->is_libcell
106           Returns if module declared inside a `celldefine.
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108       $self->level
109           Returns the reverse depth of this module with respect to other
110           modules.  Leaf modules (modules with no cells) will be level 1.
111           Modules which instantiate cells of level 1 will be level 2 modules
112           and so forth.  See also Netlist's modules_sorted_level.
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114       $self->lint
115           Checks the module for errors.
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117       $self->link
118           Creates interconnections between this module and other modules.
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120       $self->modulename_from_filename
121           Uses a rough algorithm (drop the extension) to convert a filename
122           to the module that is expected to be inside it.
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124       $self->new_cell
125           Creates a new Verilog::Netlist::Cell.
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127       $self->new_port
128           Creates a new Verilog::Netlist::Port.
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130       $self->new_net
131           Creates a new Verilog::Netlist::Net.
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133       $self->dump
134           Prints debugging information for this module.
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136       $self->verilog_text
137           Returns verilog code which represents this module.  Returned as an
138           array that must be joined together to form the final text string.
139           The netlist must be already ->link'ed for this to work correctly.
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DISTRIBUTION

142       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
143       EDA software tool suite.  The latest version is available from CPAN and
144       from <https://www.veripool.org/verilog-perl>.
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146       Copyright 2000-2020 by Wilson Snyder.  This package is free software;
147       you can redistribute it and/or modify it under the terms of either the
148       GNU Lesser General Public License Version 3 or the Perl Artistic
149       License Version 2.0.
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AUTHORS

152       Wilson Snyder <wsnyder@wsnyder.org>
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