Verilog::Verilog-Perl(3pm)

1Verilog-Perl(3)       User Contributed Perl Documentation      Verilog-Perl(3)
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NAME

6       Verilog-Perl - Overview of Verilog language packages for Perl
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DESCRIPTION

9       The Verilog-Perl distribution provides Perl parsing and utilities for
10       the Verilog Language.  This file provides an overview of the
11       distribution, for specific details on each component, see that
12       component's manpage.
13
14       You may also want to try the AUTO features present in
15       http://www.veripool.org/verilog-mode <http://www.veripool.org/verilog-
16       mode> Verilog-Mode.
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INSTALLATION

19       Skip this section if Verilog-Perl has already been installed.
20
21   Supported Systems
22       Verilog-Perl should run on any system with Perl, G++, Flex, and Bison.
23       It is known to work on at least:
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25       ·   sparc-sun-solaris2.5.1
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27       ·   i386-linux
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29       ·   i686-w2k-cygwin
30
31   CPAN Installation
32           Easiest installation is using the "CPAN" command line that comes
33           with Perl.  After configuring CPAN the first time, simply
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35              $ cpan
36              cpan> install Verilog-Perl
37
38           Read the rest of this file for details on the programs provided.
39
40   Manual Installation
41           Download the latest version from <http://www.perl.org/CPAN/>, or
42           from http://www.veripool.org/verilog-perl
43           <http://www.veripool.org/verilog-perl>.
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45           "cd" to the directory containing this README notice.
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47           Type "perl Makefile.PL" to configure Verilog for your system.
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49           Type "make" to compile Verilog.  Some Solaris users have had
50           trouble with "open" being redefined.  If this happens, try editing
51           the Makefile to change _FILE_OFFSET_BITS to 32 instead of 64.
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53           Type "make test" to check the package.  If you don't have Synopsys'
54           VCS, the test will print a warning, which you can ignore.
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56           Type "make install" to install the programs and any data files and
57           documentation.
58
59           Read the rest of this file for details on the programs provided.
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SCRIPTS

62       The following scripts are installed by Verilog-Perl:
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64       vhier
65           Vhier reads the Verilog files passed on the command line and
66           outputs a tree of all of the filenames, modules, and cells
67           referenced by that file.
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69       vpassert
70           Vpassert will read the specified Verilog files and preprocess
71           special PLI assertions.
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73       vppreproc
74           Vppreproc (Verilog-Perl Pre Processor) reads the Verilog files
75           passed on the command line and outputs preprocessed output.
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77       vrename
78           Vrename will allow a signal to be changed across all levels of the
79           design hierarchy, or to create a cross reference of signal names.
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PACKAGES

82       Verilog::Getopt
83           Verilog::Getopt provides standardized handling of options similar
84           to Verilog/VCS and cc/GCC.
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86       Verilog::Language
87           Verilog::Language provides general utilities for using the Verilog
88           Language, such as parsing numbers or determining what keywords
89           exist.
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91       Verilog::Netlist
92           Verilog::Netlist reads and holds interconnect information about a
93           whole design database.
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95       Verilog::Netlist::Cell
96           A Verilog::Netlist::Cell object is created by Verilog::Netlist for
97           every instantiation in the current module.
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99       Verilog::Netlist::File
100           Verilog::Netlist::File allows Verilog::Netlist objects to be read
101           and written in Verilog format.
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103       Verilog::Netlist::Module
104           A Verilog::Netlist::Module object is created by Verilog::Netlist
105           for every module in the design.
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107       Verilog::Netlist::Net
108           A Verilog::Netlist::Net object is created by
109           Verilog::Netlist::Module for every signal and input/output
110           declaration in the current module.
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112       Verilog::Netlist::Pin
113           A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell
114           for for each pin connection on a cell.
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116       Verilog::Netlist::Port
117           A Verilog::Netlist::Port object is created by
118           Verilog::Netlist::Module for every port connection in the module.
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120       Verilog::Netlist::Subclas
121           The Verilog::Netlist::Subclass is used as a base class for all
122           Verilog::Netlist::* structures.
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124       Verilog::Parser
125           Verilog::Parser will tokenize a Verilog file and invoke various
126           callback methods.
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128       Verilog::Preproc
129           Verilog::Preproc reads Verilog files, and preprocesses them
130           according to the Verilog specification.  Programs can be easily
131           converted from reading a IO::File into reading preprocessed output
132           from Verilog::Preproc.
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134       Verilog::SigParse
135           Verilog::SigParser builds upon the Verilog::Parser package to
136           provide callbacks for when a signal is declared, a module
137           instantiated, or a module defined.
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WHICH PARSER PACKAGE?

140       If you are starting a new application which needs to parse the Verilog
141       language you have several tools available to you.  Which you pick
142       depends on how low level and complete the information you need is.
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144       Verilog::Preproc
145           Verilog::Preproc is useful when you need only text out, or a list
146           of defines, etc.  It can preprocess a file, or be used to provide
147           the Verilog macro language on top of synthesis scripts.  It
148           understands the full SystemVerilog 2005 preprocessor syntax, and
149           parts of the SystemVerilog 2009 draft standard (the rest will be
150           supported when the standard is approved.)
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152       Verilog::Parser
153           Verilog::Parser is useful when you need to tokenize or write source
154           filters (where you need everything including whitespace).  It can
155           take raw files, or preprocessed input.  It understands all
156           SystemVerilog 2005 keywords.
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158       Abstract Syntax Tree
159           Verilog::Parser knows enough to make a complete Abstract Syntax
160           Tree (AST) of Verilog syntax, however this hasn't been implemented
161           yet.  This would allow any arbitrary transformation of Verilog
162           syntax (everthing is known excluding whitespace).  If you'd find
163           this useful please contact the author.
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165       Verilog::SigParser
166           Verilog::SigParser is useful when you need a list of modules,
167           signals, ports, functions, etc.  It requires a preprocessed file,
168           and can parse all SystemVerilog 2005 files, but only provides
169           callbacks on certain interesting things.
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171       Verilog::Netlist
172           Verilog::Netlist is useful for when you need the hierarchy, and a
173           list of signals per module, pins per cell, etc.  It builds upon the
174           output of Verilog::SigParser, so requires preprocessed files.  It
175           parses all SystemVerilog 2005 files, but not all SystemVerilog
176           constructs are loaded into objects.
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178           This is probably the most popular choice.
179
180       VPI Using the VPI is the best way to access the behavior of the design.
181           It is not part of this package as it requires a compliant simulator
182           and C++ code to call the VPI, and understands as much of the
183           language as the simulator supports.  This allows writing lint
184           checks and full knowledge of all parts of the code, but generally
185           requires the most work (short of writing a parser from scratch.)
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187       Verilator
188           The Verilator program also contains a very similar front end as
189           Verilog-Perl.  It also understands how to elaborate and connect
190           complex pins and types.  If you're looking to add some lint like
191           checks against netlists, this may be a better starting point.
192
193       Verilog-Mode for Emacs
194           Although not a parser, a common requested use of Verilog-Perl is to
195           automatically make shell modules and interconnect modules.
196           Verilog-Mode is a better solution to this problem, as it results in
197           completely portable code; the program (Verilog-Mode) isn't needed
198           for others to update the design.  It's also in very common usage,
199           including by many IP providers.
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DISTRIBUTION

202       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
203       software tool suite.  The latest version is available from CPAN and
204       from http://www.veripool.org/verilog-perl
205       <http://www.veripool.org/verilog-perl>.
206
207       Copyright 2000-2009 by Wilson Snyder.  This package is free software;
208       you can redistribute it and/or modify it under the terms of either the
209       GNU Lesser General Public License Version 3 or the Perl Artistic
210       License Version 2.0.
211
212       This code is provided with no warranty of any kind, and is used
213       entirely at your own risk.
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AUTHORS

216       Wilson Snyder <wsnyder@wsnyder.org>
217