1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14 [--help] [-I dir] [-J]
15 [-K] [-L] [--listing-lhs-width=NUM]
16 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
17 [--listing-cont-lines=NUM] [--keep-locals]
18 [-o objfile] [-R]
19 [--hash-size=NUM] [--reduce-memory-overheads]
20 [--statistics]
21 [-v] [-version] [--version]
22 [-W] [--warn] [--fatal-warnings] [-w] [-x]
23 [-Z] [@FILE]
24 [--sectname-subst] [--size-check=[error|warning]]
25 [--target-help] [target-options]
26 [--|files ...]
27 Target AArch64 options:
29 [-EB|-EL]
30 [-mabi=ABI]
31 Target Alpha options:
33 [-mcpu]
34 [-mdebug | -no-mdebug]
35 [-replace | -noreplace]
36 [-relax] [-g] [-Gsize]
37 [-F] [-32addr]
38 Target ARC options:
40 [-mcpu=cpu]
41 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
42 [-mcode-density]
43 [-EB|-EL]
44 Target ARM options:
46 [-mcpu=processor[+extension...]]
47 [-march=architecture[+extension...]]
48 [-mfpu=floating-point-format]
49 [-mfloat-abi=abi]
50 [-meabi=ver]
51 [-mthumb]
52 [-EB|-EL]
53 [-mapcs-32|-mapcs-26|-mapcs-float|
54 -mapcs-reentrant]
55 [-mthumb-interwork] [-k]
56 Target Blackfin options:
58 [-mcpu=processor[-sirevision]]
59 [-mfdpic]
60 [-mno-fdpic]
61 [-mnopic]
62 Target CRIS options:
64 [--underscore | --no-underscore]
65 [--pic] [-N]
66 [--emulation=criself | --emulation=crisaout]
67 [--march=v0_v10 | --march=v10 | --march=v32 |
68 --march=common_v10_v32]
69 Target D10V options:
71 [-O]
72 Target D30V options:
74 [-O|-n|-N]
75 Target EPIPHANY options:
77 [-mepiphany|-mepiphany16]
78 Target H8/300 options:
80 [-h-tick-hex]
81 Target i386 options:
83 [--32|--x32|--64] [-n]
84 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
85 Target i960 options:
87 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
88 -AKC|-AMC]
89 [-b] [-no-relax]
90 Target IA-64 options:
92 [-mconstant-gp|-mauto-pic]
93 [-milp32|-milp64|-mlp64|-mp64]
94 [-mle|mbe]
95 [-mtune=itanium1|-mtune=itanium2]
96 [-munwind-check=warning|-munwind-check=error]
97 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
98 [-x|-xexplicit] [-xauto] [-xdebug]
99 Target IP2K options:
101 [-mip2022|-mip2022ext]
102 Target M32C options:
104 [-m32c|-m16c] [-relax] [-h-tick-hex]
105 Target M32R options:
107 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
108 --W[n]p]
109 Target M680X0 options:
111 [-l] [-m68000|-m68010|-m68020|...]
112 Target M68HC11 options:
114 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
115 [-mshort|-mlong]
116 [-mshort-double|-mlong-double]
117 [--force-long-branches] [--short-branches]
118 [--strict-direct-mode] [--print-insn-syntax]
119 [--print-opcodes] [--generate-example]
120 Target MCORE options:
122 [-jsri2bsr] [-sifilter] [-relax]
123 [-mcpu=[210|340]]
124 Target Meta options:
126 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
127 Target MIPS options:
129 [-nocpp] [-EL] [-EB] [-O[optimization level]]
130 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
131 [-non_shared] [-xgot [-mvxworks-pic]
132 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
133 [-mfp64] [-mgp64] [-mfpxx]
134 [-modd-spreg] [-mno-odd-spreg]
135 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
136 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
137 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
138 [-mips64r3] [-mips64r5] [-mips64r6]
139 [-construct-floats] [-no-construct-floats]
140 [-mnan=encoding]
141 [-trap] [-no-break] [-break] [-no-trap]
142 [-mips16] [-no-mips16]
143 [-mmicromips] [-mno-micromips]
144 [-msmartmips] [-mno-smartmips]
145 [-mips3d] [-no-mips3d]
146 [-mdmx] [-no-mdmx]
147 [-mdsp] [-mno-dsp]
148 [-mdspr2] [-mno-dspr2]
149 [-mmsa] [-mno-msa]
150 [-mxpa] [-mno-xpa]
151 [-mmt] [-mno-mt]
152 [-mmcu] [-mno-mcu]
153 [-minsn32] [-mno-insn32]
154 [-mfix7000] [-mno-fix7000]
155 [-mfix-rm7000] [-mno-fix-rm7000]
156 [-mfix-vr4120] [-mno-fix-vr4120]
157 [-mfix-vr4130] [-mno-fix-vr4130]
158 [-mdebug] [-no-mdebug]
159 [-mpdr] [-mno-pdr]
160 Target MMIX options:
162 [--fixed-special-register-names] [--globalize-symbols]
163 [--gnu-syntax] [--relax] [--no-predefined-symbols]
164 [--no-expand] [--no-merge-gregs] [-x]
165 [--linker-allocated-gregs]
166 Target Nios II options:
168 [-relax-all] [-relax-section] [-no-relax]
169 [-EB] [-EL]
170 Target NDS32 options:
172 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
173 [-misa=isa] [-mabi=abi] [-mall-ext]
174 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
175 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
176 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
177 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
178 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
179 [-mb2bb]
180 Target PDP11 options:
182 [-mpic|-mno-pic] [-mall] [-mno-extensions]
183 [-mextension|-mno-extension]
184 [-mcpu] [-mmachine]
185 Target picoJava options:
187 [-mb|-me]
188 Target PowerPC options:
190 [-a32|-a64]
191 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
192 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
193 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
194 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
195 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
196 -mcell|-mspe|-mtitan|-me300|-mcom]
197 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
198 [-mregnames|-mno-regnames]
199 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
200 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
201 [-msolaris|-mno-solaris]
202 [-nops=count]
203 Target RL78 options:
205 [-mg10]
206 [-m32bit-doubles|-m64bit-doubles]
207 Target RX options:
209 [-mlittle-endian|-mbig-endian]
210 [-m32bit-doubles|-m64bit-doubles]
211 [-muse-conventional-section-names]
212 [-msmall-data-limit]
213 [-mpid]
214 [-mrelax]
215 [-mint-register=number]
216 [-mgcc-abi|-mrx-abi]
217 Target s390 options:
219 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
220 [-mregnames|-mno-regnames]
221 [-mwarn-areg-zero]
222 Target SCORE options:
224 [-EB][-EL][-FIXDD][-NWARN]
225 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
226 [-march=score7][-march=score3]
227 [-USE_R1][-KPIC][-O0][-G num][-V]
228 Target SPARC options:
230 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
231 -Av8plus|-Av8plusa|-Av9|-Av9a]
232 [-xarch=v8plus|-xarch=v8plusa] [-bump]
233 [-32|-64]
234 Target TIC54X options:
236 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
237 [-merrors-to-file <filename>|-me <filename>]
238 Target TIC6X options:
240 [-march=arch] [-mbig-endian|-mlittle-endian]
241 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
242 [-mpic|-mno-pic]
243 Target TILE-Gx options:
245 [-m32|-m64][-EB][-EL]
246 Target Visium options:
248 [-mtune=arch]
249 Target Xtensa options:
251 [--[no-]text-section-literals] [--[no-]auto-litpools]
252 [--[no-]absolute-literals]
253 [--[no-]target-align] [--[no-]longcalls]
254 [--[no-]transform]
255 [--rename-section oldname=newname]
256 [--[no-]trampolines]
257 Target Z80 options:
259 [-z80] [-r800]
260 [ -ignore-undocumented-instructions] [-Wnud]
261 [ -ignore-unportable-instructions] [-Wnup]
262 [ -warn-undocumented-instructions] [-Wud]
263 [ -warn-unportable-instructions] [-Wup]
264 [ -forbid-undocumented-instructions] [-Fud]
265 [ -forbid-unportable-instructions] [-Fup]
266
268 GNU as is really a family of assemblers. If you use (or have used) the
269 GNU assembler on one architecture, you should find a fairly similar
270 environment when you use it on another architecture. Each version has
271 much in common with the others, including object file formats, most
272 assembler directives (often called pseudo-ops) and assembler syntax.
273 as is primarily intended to assemble the output of the GNU C compiler
275 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
276 assemble correctly everything that other assemblers for the same
277 machine would assemble. Any exceptions are documented explicitly.
278 This doesn't mean as always uses the same syntax as another assembler
279 for the same architecture; for example, we know of several incompatible
280 versions of 680x0 assembly language syntax.
281 Each time you run as it assembles exactly one source program. The
283 source program is made up of one or more files. (The standard input is
284 also a file.)
285 You give as a command line that has zero or more input file names. The
287 input files are read (from left file name to right). A command line
288 argument (in any position) that has no special meaning is taken to be
289 an input file name.
290 If you give as no file names it attempts to read one input file from
292 the as standard input, which is normally your terminal. You may have
293 to type ctl-D to tell as there is no more program to assemble.
294 Use -- if you need to explicitly name the standard input file in your
296 command line.
297 If the source is empty, as produces a small, empty object file.
299 as may write warnings and error messages to the standard error file
301 (usually your terminal). This should not happen when a compiler runs
302 as automatically. Warnings report an assumption made so that as could
303 keep assembling a flawed program; errors report a grave problem that
304 stops the assembly.
305 If you are invoking as via the GNU C compiler, you can use the -Wa
307 option to pass arguments through to the assembler. The assembler
308 arguments must be separated from each other (and the -Wa) by commas.
309 For example:
310 gcc -c -g -O -Wa,-alh,-L file.c
312 This passes two options to the assembler: -alh (emit a listing to
314 standard output with high-level and assembly source) and -L (retain
315 local symbols in the symbol table).
316 Usually you do not need to use this -Wa mechanism, since many compiler
318 command-line options are automatically passed to the assembler by the
319 compiler. (You can call the GNU compiler driver with the -v option to
320 see precisely what options it passes to each compilation pass,
321 including the assembler.)
322
324 @file
325 Read command-line options from file. The options read are inserted
326 in place of the original @file option. If file does not exist, or
327 cannot be read, then the option will be treated literally, and not
328 removed.
329 Options in file are separated by whitespace. A whitespace
331 character may be included in an option by surrounding the entire
332 option in either single or double quotes. Any character (including
333 a backslash) may be included by prefixing the character to be
334 included with a backslash. The file may itself contain additional
335 @file options; any such options will be processed recursively.
336 -a[cdghlmns]
338 Turn on listings, in any of a variety of ways:
339 -ac omit false conditionals
341 -ad omit debugging directives
343 -ag include general information, like as version and options passed
345 -ah include high-level source
347 -al include assembly
349 -am include macro expansions
351 -an omit forms processing
353 -as include symbols
355 =file
357 set the name of the listing file
358 You may combine these options; for example, use -aln for assembly
360 listing without forms processing. The =file option, if used, must
361 be the last one. By itself, -a defaults to -ahls.
362 --alternate
364 Begin in alternate macro mode.
365 --compress-debug-sections
367 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
368 the ELF ABI. The resulting object file may not be compatible with
369 older linkers and object file utilities. Note if compression would
370 make a given section larger then it is not compressed.
371 --compress-debug-sections=none
373 --compress-debug-sections=zlib
374 --compress-debug-sections=zlib-gnu
375 --compress-debug-sections=zlib-gabi
376 These options control how DWARF debug sections are compressed.
377 --compress-debug-sections=none is equivalent to
378 --nocompress-debug-sections. --compress-debug-sections=zlib and
379 --compress-debug-sections=zlib-gabi are equivalent to
380 --compress-debug-sections. --compress-debug-sections=zlib-gnu
381 compresses DWARF debug sections using zlib. The debug sections are
382 renamed to begin with .zdebug. Note if compression would make a
383 given section larger then it is not compressed nor renamed.
384 --nocompress-debug-sections
386 Do not compress DWARF debug sections. This is usually the default
387 for all targets except the x86/x86_64, but a configure time option
388 can be used to override this.
389 -D Ignored. This option is accepted for script compatibility with
391 calls to other assemblers.
392 --debug-prefix-map old=new
394 When assembling files in directory old, record debugging
395 information describing them as in new instead.
396 --defsym sym=value
398 Define the symbol sym to be value before assembling the input file.
399 value must be an integer constant. As in C, a leading 0x indicates
400 a hexadecimal value, and a leading 0 indicates an octal value. The
401 value of the symbol can be overridden inside a source file via the
402 use of a ".set" pseudo-op.
403 -f "fast"---skip whitespace and comment preprocessing (assume source
405 is compiler output).
406 -g
408 --gen-debug
409 Generate debugging information for each assembler source line using
410 whichever debug format is preferred by the target. This currently
411 means either STABS, ECOFF or DWARF2.
412 --gstabs
414 Generate stabs debugging information for each assembler line. This
415 may help debugging assembler code, if the debugger can handle it.
416 --gstabs+
418 Generate stabs debugging information for each assembler line, with
419 GNU extensions that probably only gdb can handle, and that could
420 make other debuggers crash or refuse to read your program. This
421 may help debugging assembler code. Currently the only GNU
422 extension is the location of the current working directory at
423 assembling time.
424 --gdwarf-2
426 Generate DWARF2 debugging information for each assembler line.
427 This may help debugging assembler code, if the debugger can handle
428 it. Note---this option is only supported by some targets, not all
429 of them.
430 --gdwarf-sections
432 Instead of creating a .debug_line section, create a series of
433 .debug_line.foo sections where foo is the name of the corresponding
434 code section. For example a code section called .text.func will
435 have its dwarf line number information placed into a section called
436 .debug_line.text.func. If the code section is just called .text
437 then debug line section will still be called just .debug_line
438 without any suffix.
439 --size-check=error
441 --size-check=warning
442 Issue an error or warning for invalid ELF .size directive.
443 --help
445 Print a summary of the command line options and exit.
446 --target-help
448 Print a summary of all target specific options and exit.
449 -I dir
451 Add directory dir to the search list for ".include" directives.
452 -J Don't warn about signed overflow.
454 -K Issue warnings when difference tables altered for long
456 displacements.
457 -L
459 --keep-locals
460 Keep (in the symbol table) local symbols. These symbols start with
461 system-specific local label prefixes, typically .L for ELF systems
462 or L for traditional a.out systems.
463 --listing-lhs-width=number
465 Set the maximum width, in words, of the output data column for an
466 assembler listing to number.
467 --listing-lhs-width2=number
469 Set the maximum width, in words, of the output data column for
470 continuation lines in an assembler listing to number.
471 --listing-rhs-width=number
473 Set the maximum width of an input source line, as displayed in a
474 listing, to number bytes.
475 --listing-cont-lines=number
477 Set the maximum number of lines printed in a listing for a single
478 line of input to number + 1.
479 -o objfile
481 Name the object-file output from as objfile.
482 -R Fold the data section into the text section.
484 --hash-size=number
486 Set the default size of GAS's hash tables to a prime number close
487 to number. Increasing this value can reduce the length of time it
488 takes the assembler to perform its tasks, at the expense of
489 increasing the assembler's memory requirements. Similarly reducing
490 this value can reduce the memory requirements at the expense of
491 speed.
492 --reduce-memory-overheads
494 This option reduces GAS's memory requirements, at the expense of
495 making the assembly processes slower. Currently this switch is a
496 synonym for --hash-size=4051, but in the future it may have other
497 effects as well.
498 --sectname-subst
500 Honor substitution sequences in section names.
501 --statistics
503 Print the maximum space (in bytes) and total time (in seconds) used
504 by assembly.
505 --strip-local-absolute
507 Remove local absolute symbols from the outgoing symbol table.
508 -v
510 -version
511 Print the as version.
512 --version
514 Print the as version and exit.
515 -W
517 --no-warn
518 Suppress warning messages.
519 --fatal-warnings
521 Treat warnings as errors.
522 --warn
524 Don't suppress warning messages or treat them as errors.
525 -w Ignored.
527 -x Ignored.
529 -Z Generate an object file even after errors.
531 -- | files ...
533 Standard input, or source files to assemble.
534 The following options are available when as is configured for the
536 64-bit mode of the ARM Architecture (AArch64).
537 -EB This option specifies that the output generated by the assembler
539 should be marked as being encoded for a big-endian processor.
540 -EL This option specifies that the output generated by the assembler
542 should be marked as being encoded for a little-endian processor.
543 -mabi=abi
545 Specify which ABI the source code uses. The recognized arguments
546 are: "ilp32" and "lp64", which decides the generated object file in
547 ELF32 and ELF64 format respectively. The default is "lp64".
548 -mcpu=processor[+extension...]
550 This option specifies the target processor. The assembler will
551 issue an error message if an attempt is made to assemble an
552 instruction which will not execute on the target processor. The
553 following processor names are recognized: "cortex-a35",
554 "cortex-a53", "cortex-a57", "cortex-a72", "exynos-m1", "qdf24xx",
555 "thunderx", "xgene1" and "xgene2". The special name "all" may be
556 used to allow the assembler to accept instructions valid for any
557 supported processor, including all optional extensions.
558 In addition to the basic instruction set, the assembler can be told
560 to accept, or restrict, various extension mnemonics that extend the
561 processor.
562 If some implementations of a particular processor can have an
564 extension, then then those extensions are automatically enabled.
565 Consequently, you will not normally have to specify any additional
566 extensions.
567 -march=architecture[+extension...]
569 This option specifies the target architecture. The assembler will
570 issue an error message if an attempt is made to assemble an
571 instruction which will not execute on the target architecture. The
572 following architecture names are recognized: "armv8-a", "armv8.1-a"
573 and "armv8.2-a".
574 If both -mcpu and -march are specified, the assembler will use the
576 setting for -mcpu. If neither are specified, the assembler will
577 default to -mcpu=all.
578 The architecture option can be extended with the same instruction
580 set extension options as the -mcpu option. Unlike -mcpu,
581 extensions are not always enabled by default,
582 -mverbose-error
584 This option enables verbose error messages for AArch64 gas. This
585 option is enabled by default.
586 -mno-verbose-error
588 This option disables verbose error messages in AArch64 gas.
589 The following options are available when as is configured for an Alpha
591 processor.
592 -mcpu
594 This option specifies the target processor. If an attempt is made
595 to assemble an instruction which will not execute on the target
596 processor, the assembler may either expand the instruction as a
597 macro or issue an error message. This option is equivalent to the
598 ".arch" directive.
599 The following processor names are recognized: 21064, "21064a",
601 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
602 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
603 "ev67", "ev68". The special name "all" may be used to allow the
604 assembler to accept instructions valid for any Alpha processor.
605 In order to support existing practice in OSF/1 with respect to
607 ".arch", and existing practice within MILO (the Linux ARC
608 bootloader), the numbered processor names (e.g. 21064) enable the
609 processor-specific PALcode instructions, while the "electro-vlasic"
610 names (e.g. "ev4") do not.
611 -mdebug
613 -no-mdebug
614 Enables or disables the generation of ".mdebug" encapsulation for
615 stabs directives and procedure descriptors. The default is to
616 automatically enable ".mdebug" when the first stabs directive is
617 seen.
618 -relax
620 This option forces all relocations to be put into the object file,
621 instead of saving space and resolving some relocations at assembly
622 time. Note that this option does not propagate all symbol
623 arithmetic into the object file, because not all symbol arithmetic
624 can be represented. However, the option can still be useful in
625 specific applications.
626 -replace
628 -noreplace
629 Enables or disables the optimization of procedure calls, both at
630 assemblage and at link time. These options are only available for
631 VMS targets and "-replace" is the default. See section 1.4.1 of
632 the OpenVMS Linker Utility Manual.
633 -g This option is used when the compiler generates debug information.
635 When gcc is using mips-tfile to generate debug information for
636 ECOFF, local labels must be passed through to the object file.
637 Otherwise this option has no effect.
638 -Gsize
640 A local common symbol larger than size is placed in ".bss", while
641 smaller symbols are placed in ".sbss".
642 -F
644 -32addr
645 These options are ignored for backward compatibility.
646 The following options are available when as is configured for an ARC
648 processor.
649 -mcpu=cpu
651 This option selects the core processor variant.
652 -EB | -EL
654 Select either big-endian (-EB) or little-endian (-EL) output.
655 -mcode-density
657 Enable Code Density extenssion instructions.
658 The following options are available when as is configured for the ARM
660 processor family.
661 -mcpu=processor[+extension...]
663 Specify which ARM processor variant is the target.
664 -march=architecture[+extension...]
666 Specify which ARM architecture variant is used by the target.
667 -mfpu=floating-point-format
669 Select which Floating Point architecture is the target.
670 -mfloat-abi=abi
672 Select which floating point ABI is in use.
673 -mthumb
675 Enable Thumb only instruction decoding.
676 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
678 Select which procedure calling convention is in use.
679 -EB | -EL
681 Select either big-endian (-EB) or little-endian (-EL) output.
682 -mthumb-interwork
684 Specify that the code has been generated with interworking between
685 Thumb and ARM code in mind.
686 -mccs
688 Turns on CodeComposer Studio assembly syntax compatibility mode.
689 -k Specify that PIC code has been generated.
691 The following options are available when as is configured for the
693 Blackfin processor family.
694 -mcpu=processor[-sirevision]
696 This option specifies the target processor. The optional
697 sirevision is not used in assembler. It's here such that GCC can
698 easily pass down its "-mcpu=" option. The assembler will issue an
699 error message if an attempt is made to assemble an instruction
700 which will not execute on the target processor. The following
701 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
702 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
703 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
704 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
705 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
706 "bf549", "bf549m", "bf561", and "bf592".
707 -mfdpic
709 Assemble for the FDPIC ABI.
710 -mno-fdpic
712 -mnopic
713 Disable -mfdpic.
714 See the info pages for documentation of the CRIS-specific options.
716 The following options are available when as is configured for a D10V
718 processor.
719 -O Optimize output by parallelizing instructions.
721 The following options are available when as is configured for a D30V
723 processor.
724 -O Optimize output by parallelizing instructions.
726 -n Warn when nops are generated.
728 -N Warn when a nop after a 32-bit multiply instruction is generated.
730 The following options are available when as is configured for an
732 Epiphany processor.
733 -mepiphany
735 Specifies that the both 32 and 16 bit instructions are allowed.
736 This is the default behavior.
737 -mepiphany16
739 Restricts the permitted instructions to just the 16 bit set.
740 The following options are available when as is configured for an H8/300
742 processor. @chapter H8/300 Dependent Features
743 Options
745 The Renesas H8/300 version of "as" has one machine-dependent option:
746 -h-tick-hex
748 Support H'00 style hex constants in addition to 0x00 style.
749 -mach=name
751 Sets the H8300 machine variant. The following machine names are
752 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
753 "h8300sxn".
754 The following options are available when as is configured for an i386
756 processor.
757 --32 | --x32 | --64
759 Select the word size, either 32 bits or 64 bits. --32 implies
760 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
761 architecture with 32-bit or 64-bit word-size respectively.
762 These options are only available with the ELF object file format,
764 and require that the necessary BFD support has been included (on a
765 32-bit platform you have to add --enable-64-bit-bfd to configure
766 enable 64-bit usage and use x86-64 as target platform).
767 -n By default, x86 GAS replaces multiple nop instructions used for
769 alignment within code sections with multi-byte nop instructions
770 such as leal 0(%esi,1),%esi. This switch disables the
771 optimization.
772 --divide
774 On SVR4-derived platforms, the character / is treated as a comment
775 character, which means that it cannot be used in expressions. The
776 --divide option turns / into a normal character. This does not
777 disable / at the beginning of a line starting a comment, or affect
778 using # for starting a comment.
779 -march=CPU[+EXTENSION...]
781 This option specifies the target processor. The assembler will
782 issue an error message if an attempt is made to assemble an
783 instruction which will not execute on the target processor. The
784 following processor names are recognized: "i8086", "i186", "i286",
785 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
786 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
787 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
788 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
789 "bdver3", "bdver4", "znver1", "btver1", "btver2", "generic32" and
790 "generic64".
791 In addition to the basic instruction set, the assembler can be told
793 to accept various extension mnemonics. For example,
794 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
795 following extensions are currently supported: 8087, 287, 387,
796 "no87", "mmx", "nommx", "sse", "sse2", "sse3", "ssse3", "sse4.1",
797 "sse4.2", "sse4", "nosse", "avx", "avx2", "adx", "rdseed",
798 "prfchw", "smap", "mpx", "sha", "prefetchwt1", "clflushopt", "se1",
799 "clwb", "pcommit", "avx512f", "avx512cd", "avx512er", "avx512pf",
800 "avx512vl", "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
801 "noavx", "vmx", "vmfunc", "smx", "xsave", "xsaveopt", "xsavec",
802 "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2",
803 "fma", "movbe", "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush",
804 "mwaitx", "clzero", "lwp", "fma4", "xop", "cx16", "syscall",
805 "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme", "abm" and
806 "padlock". Note that rather than extending a basic instruction
807 set, the extension mnemonics starting with "no" revoke the
808 respective functionality.
809 When the ".arch" directive is used with -march, the ".arch"
811 directive will take precedent.
812 -mtune=CPU
814 This option specifies a processor to optimize for. When used in
815 conjunction with the -march option, only instructions of the
816 processor specified by the -march option will be generated.
817 Valid CPU values are identical to the processor list of -march=CPU.
819 -msse2avx
821 This option specifies that the assembler should encode SSE
822 instructions with VEX prefix.
823 -msse-check=none
825 -msse-check=warning
826 -msse-check=error
827 These options control if the assembler should check SSE
828 instructions. -msse-check=none will make the assembler not to
829 check SSE instructions, which is the default. -msse-check=warning
830 will make the assembler issue a warning for any SSE instruction.
831 -msse-check=error will make the assembler issue an error for any
832 SSE instruction.
833 -mavxscalar=128
835 -mavxscalar=256
836 These options control how the assembler should encode scalar AVX
837 instructions. -mavxscalar=128 will encode scalar AVX instructions
838 with 128bit vector length, which is the default. -mavxscalar=256
839 will encode scalar AVX instructions with 256bit vector length.
840 -mevexlig=128
842 -mevexlig=256
843 -mevexlig=512
844 These options control how the assembler should encode length-
845 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
846 EVEX instructions with 128bit vector length, which is the default.
847 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
848 with 256bit and 512bit vector length, respectively.
849 -mevexwig=0
851 -mevexwig=1
852 These options control how the assembler should encode w-ignored
853 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
854 instructions with evex.w = 0, which is the default. -mevexwig=1
855 will encode WIG EVEX instructions with evex.w = 1.
856 -mmnemonic=att
858 -mmnemonic=intel
859 This option specifies instruction mnemonic for matching
860 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
861 will take precedent.
862 -msyntax=att
864 -msyntax=intel
865 This option specifies instruction syntax when processing
866 instructions. The ".att_syntax" and ".intel_syntax" directives
867 will take precedent.
868 -mnaked-reg
870 This opetion specifies that registers don't require a % prefix.
871 The ".att_syntax" and ".intel_syntax" directives will take
872 precedent.
873 -madd-bnd-prefix
875 This option forces the assembler to add BND prefix to all branches,
876 even if such prefix was not explicitly specified in the source
877 code.
878 -mno-shared
880 On ELF target, the assembler normally optimizes out non-PLT
881 relocations against defined non-weak global branch targets with
882 default visibility. The -mshared option tells the assembler to
883 generate code which may go into a shared library where all non-weak
884 global branch targets with default visibility can be preempted.
885 The resulting code is slightly bigger. This option only affects
886 the handling of branch instructions.
887 -mbig-obj
889 On x86-64 PE/COFF target this option forces the use of big object
890 file format, which allows more than 32768 sections.
891 -momit-lock-prefix=no
893 -momit-lock-prefix=yes
894 These options control how the assembler should encode lock prefix.
895 This option is intended as a workaround for processors, that fail
896 on lock prefix. This option can only be safely used with single-
897 core, single-thread computers -momit-lock-prefix=yes will omit all
898 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
899 usual, which is the default.
900 -mevexrcig=rne
902 -mevexrcig=rd
903 -mevexrcig=ru
904 -mevexrcig=rz
905 These options control how the assembler should encode SAE-only EVEX
906 instructions. -mevexrcig=rne will encode RC bits of EVEX
907 instruction with 00, which is the default. -mevexrcig=rd,
908 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
909 instructions with 01, 10 and 11 RC bits, respectively.
910 -mamd64
912 -mintel64
913 This option specifies that the assembler should accept only AMD64
914 or Intel64 ISA in 64-bit mode. The default is to accept both.
915 The following options are available when as is configured for the Intel
917 80960 processor.
918 -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
920 Specify which variant of the 960 architecture is the target.
921 -b Add code to collect statistics about branches taken.
923 -no-relax
925 Do not alter compare-and-branch instructions for long
926 displacements; error if necessary.
927 The following options are available when as is configured for the
929 Ubicom IP2K series.
930 -mip2022ext
932 Specifies that the extended IP2022 instructions are allowed.
933 -mip2022
935 Restores the default behaviour, which restricts the permitted
936 instructions to just the basic IP2022 ones.
937 The following options are available when as is configured for the
939 Renesas M32C and M16C processors.
940 -m32c
942 Assemble M32C instructions.
943 -m16c
945 Assemble M16C instructions (the default).
946 -relax
948 Enable support for link-time relaxations.
949 -h-tick-hex
951 Support H'00 style hex constants in addition to 0x00 style.
952 The following options are available when as is configured for the
954 Renesas M32R (formerly Mitsubishi M32R) series.
955 --m32rx
957 Specify which processor in the M32R family is the target. The
958 default is normally the M32R, but this option changes it to the
959 M32RX.
960 --warn-explicit-parallel-conflicts or --Wp
962 Produce warning messages when questionable parallel constructs are
963 encountered.
964 --no-warn-explicit-parallel-conflicts or --Wnp
966 Do not produce warning messages when questionable parallel
967 constructs are encountered.
968 The following options are available when as is configured for the
970 Motorola 68000 series.
971 -l Shorten references to undefined symbols, to one word instead of
973 two.
974 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
976 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
977 | -m68333 | -m68340 | -mcpu32 | -m5200
978 Specify what processor in the 68000 family is the target. The
979 default is normally the 68020, but this can be changed at
980 configuration time.
981 -m68881 | -m68882 | -mno-68881 | -mno-68882
983 The target machine does (or does not) have a floating-point
984 coprocessor. The default is to assume a coprocessor for 68020,
985 68030, and cpu32. Although the basic 68000 is not compatible with
986 the 68881, a combination of the two can be specified, since it's
987 possible to do emulation of the coprocessor instructions with the
988 main processor.
989 -m68851 | -mno-68851
991 The target machine does (or does not) have a memory-management unit
992 coprocessor. The default is to assume an MMU for 68020 and up.
993 The following options are available when as is configured for an Altera
995 Nios II processor.
996 -relax-section
998 Replace identified out-of-range branches with PC-relative "jmp"
999 sequences when possible. The generated code sequences are suitable
1000 for use in position-independent code, but there is a practical
1001 limit on the extended branch range because of the length of the
1002 sequences. This option is the default.
1003 -relax-all
1005 Replace branch instructions not determinable to be in range and all
1006 call instructions with "jmp" and "callr" sequences (respectively).
1007 This option generates absolute relocations against the target
1008 symbols and is not appropriate for position-independent code.
1009 -no-relax
1011 Do not replace any branches or calls.
1012 -EB Generate big-endian output.
1014 -EL Generate little-endian output. This is the default.
1016 -march=architecture
1018 This option specifies the target architecture. The assembler
1019 issues an error message if an attempt is made to assemble an
1020 instruction which will not execute on the target architecture. The
1021 following architecture names are recognized: "r1", "r2". The
1022 default is "r1".
1023 The following options are available when as is configured for a Meta
1025 processor.
1026 "-mcpu=metac11"
1028 Generate code for Meta 1.1.
1029 "-mcpu=metac12"
1031 Generate code for Meta 1.2.
1032 "-mcpu=metac21"
1034 Generate code for Meta 2.1.
1035 "-mfpu=metac21"
1037 Allow code to use FPU hardware of Meta 2.1.
1038 See the info pages for documentation of the MMIX-specific options.
1040 The following options are available when as is configured for a NDS32
1042 processor.
1043 "-O1"
1045 Optimize for performance.
1046 "-Os"
1048 Optimize for space.
1049 "-EL"
1051 Produce little endian data output.
1052 "-EB"
1054 Produce little endian data output.
1055 "-mpic"
1057 Generate PIC.
1058 "-mno-fp-as-gp-relax"
1060 Suppress fp-as-gp relaxation for this file.
1061 "-mb2bb-relax"
1063 Back-to-back branch optimization.
1064 "-mno-all-relax"
1066 Suppress all relaxation for this file.
1067 "-march=<arch name>"
1069 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1070 v3f, v3s, v2, v2j, v2f, v2s.
1071 "-mbaseline=<baseline>"
1073 Assemble for baseline <baseline> which could be v2, v3, v3m.
1074 "-mfpu-freg=FREG"
1076 Specify a FPU configuration.
1077 "0 8 SP / 4 DP registers"
1079 "1 16 SP / 8 DP registers"
1080 "2 32 SP / 16 DP registers"
1081 "3 32 SP / 32 DP registers"
1082 "-mabi=abi"
1083 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1084 "-m[no-]mac"
1086 Enable/Disable Multiply instructions support.
1087 "-m[no-]div"
1089 Enable/Disable Divide instructions support.
1090 "-m[no-]16bit-ext"
1092 Enable/Disable 16-bit extension
1093 "-m[no-]dx-regs"
1095 Enable/Disable d0/d1 registers
1096 "-m[no-]perf-ext"
1098 Enable/Disable Performance extension
1099 "-m[no-]perf2-ext"
1101 Enable/Disable Performance extension 2
1102 "-m[no-]string-ext"
1104 Enable/Disable String extension
1105 "-m[no-]reduced-regs"
1107 Enable/Disable Reduced Register configuration (GPR16) option
1108 "-m[no-]audio-isa-ext"
1110 Enable/Disable AUDIO ISA extension
1111 "-m[no-]fpu-sp-ext"
1113 Enable/Disable FPU SP extension
1114 "-m[no-]fpu-dp-ext"
1116 Enable/Disable FPU DP extension
1117 "-m[no-]fpu-fma"
1119 Enable/Disable FPU fused-multiply-add instructions
1120 "-mall-ext"
1122 Turn on all extensions and instructions support
1123 The following options are available when as is configured for a PowerPC
1125 processor.
1126 -a32
1128 Generate ELF32 or XCOFF32.
1129 -a64
1131 Generate ELF64 or XCOFF64.
1132 -K PIC
1134 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1135 -mpwrx | -mpwr2
1137 Generate code for POWER/2 (RIOS2).
1138 -mpwr
1140 Generate code for POWER (RIOS1)
1141 -m601
1143 Generate code for PowerPC 601.
1144 -mppc, -mppc32, -m603, -m604
1146 Generate code for PowerPC 603/604.
1147 -m403, -m405
1149 Generate code for PowerPC 403/405.
1150 -m440
1152 Generate code for PowerPC 440. BookE and some 405 instructions.
1153 -m464
1155 Generate code for PowerPC 464.
1156 -m476
1158 Generate code for PowerPC 476.
1159 -m7400, -m7410, -m7450, -m7455
1161 Generate code for PowerPC 7400/7410/7450/7455.
1162 -m750cl
1164 Generate code for PowerPC 750CL.
1165 -m821, -m850, -m860
1167 Generate code for PowerPC 821/850/860.
1168 -mppc64, -m620
1170 Generate code for PowerPC 620/625/630.
1171 -me500, -me500x2
1173 Generate code for Motorola e500 core complex.
1174 -me500mc
1176 Generate code for Freescale e500mc core complex.
1177 -me500mc64
1179 Generate code for Freescale e500mc64 core complex.
1180 -me5500
1182 Generate code for Freescale e5500 core complex.
1183 -me6500
1185 Generate code for Freescale e6500 core complex.
1186 -mspe
1188 Generate code for Motorola SPE instructions.
1189 -mtitan
1191 Generate code for AppliedMicro Titan core complex.
1192 -mppc64bridge
1194 Generate code for PowerPC 64, including bridge insns.
1195 -mbooke
1197 Generate code for 32-bit BookE.
1198 -ma2
1200 Generate code for A2 architecture.
1201 -me300
1203 Generate code for PowerPC e300 family.
1204 -maltivec
1206 Generate code for processors with AltiVec instructions.
1207 -mvle
1209 Generate code for Freescale PowerPC VLE instructions.
1210 -mvsx
1212 Generate code for processors with Vector-Scalar (VSX) instructions.
1213 -mhtm
1215 Generate code for processors with Hardware Transactional Memory
1216 instructions.
1217 -mpower4, -mpwr4
1219 Generate code for Power4 architecture.
1220 -mpower5, -mpwr5, -mpwr5x
1222 Generate code for Power5 architecture.
1223 -mpower6, -mpwr6
1225 Generate code for Power6 architecture.
1226 -mpower7, -mpwr7
1228 Generate code for Power7 architecture.
1229 -mpower8, -mpwr8
1231 Generate code for Power8 architecture.
1232 -mpower9, -mpwr9
1234 Generate code for Power9 architecture.
1235 -mcell
1237 -mcell
1238 Generate code for Cell Broadband Engine architecture.
1239 -mcom
1241 Generate code Power/PowerPC common instructions.
1242 -many
1244 Generate code for any architecture (PWR/PWRX/PPC).
1245 -mregnames
1247 Allow symbolic names for registers.
1248 -mno-regnames
1250 Do not allow symbolic names for registers.
1251 -mrelocatable
1253 Support for GCC's -mrelocatable option.
1254 -mrelocatable-lib
1256 Support for GCC's -mrelocatable-lib option.
1257 -memb
1259 Set PPC_EMB bit in ELF flags.
1260 -mlittle, -mlittle-endian, -le
1262 Generate code for a little endian machine.
1263 -mbig, -mbig-endian, -be
1265 Generate code for a big endian machine.
1266 -msolaris
1268 Generate code for Solaris.
1269 -mno-solaris
1271 Do not generate code for Solaris.
1272 -nops=count
1274 If an alignment directive inserts more than count nops, put a
1275 branch at the beginning to skip execution of the nops.
1276 See the info pages for documentation of the RX-specific options.
1278 The following options are available when as is configured for the s390
1280 processor family.
1281 -m31
1283 -m64
1284 Select the word size, either 31/32 bits or 64 bits.
1285 -mesa
1287 -mzarch
1288 Select the architecture mode, either the Enterprise System
1289 Architecture (esa) or the z/Architecture mode (zarch).
1290 -march=processor
1292 Specify which s390 processor variant is the target, g6, g6, z900,
1293 z990, z9-109, z9-ec, z10, z196, zEC12, or z13.
1294 -mregnames
1296 -mno-regnames
1297 Allow or disallow symbolic names for registers.
1298 -mwarn-areg-zero
1300 Warn whenever the operand for a base or index register has been
1301 specified but evaluates to zero.
1302 The following options are available when as is configured for a
1304 TMS320C6000 processor.
1305 -march=arch
1307 Enable (only) instructions from architecture arch. By default, all
1308 instructions are permitted.
1309 The following values of arch are accepted: "c62x", "c64x", "c64x+",
1311 "c67x", "c67x+", "c674x".
1312 -mdsbt
1314 -mno-dsbt
1315 The -mdsbt option causes the assembler to generate the
1316 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1317 code is using DSBT addressing. The -mno-dsbt option, the default,
1318 causes the tag to have a value of 0, indicating that the code does
1319 not use DSBT addressing. The linker will emit a warning if objects
1320 of different type (DSBT and non-DSBT) are linked together.
1321 -mpid=no
1323 -mpid=near
1324 -mpid=far
1325 The -mpid= option causes the assembler to generate the
1326 "Tag_ABI_PID" attribute with a value indicating the form of data
1327 addressing used by the code. -mpid=no, the default, indicates
1328 position-dependent data addressing, -mpid=near indicates position-
1329 independent addressing with GOT accesses using near DP addressing,
1330 and -mpid=far indicates position-independent addressing with GOT
1331 accesses using far DP addressing. The linker will emit a warning
1332 if objects built with different settings of this option are linked
1333 together.
1334 -mpic
1336 -mno-pic
1337 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1338 attribute with a value of 1, indicating that the code is using
1339 position-independent code addressing, The "-mno-pic" option, the
1340 default, causes the tag to have a value of 0, indicating position-
1341 dependent code addressing. The linker will emit a warning if
1342 objects of different type (position-dependent and position-
1343 independent) are linked together.
1344 -mbig-endian
1346 -mlittle-endian
1347 Generate code for the specified endianness. The default is little-
1348 endian.
1349 The following options are available when as is configured for a TILE-Gx
1351 processor.
1352 -m32 | -m64
1354 Select the word size, either 32 bits or 64 bits.
1355 -EB | -EL
1357 Select the endianness, either big-endian (-EB) or little-endian
1358 (-EL).
1359 The following option is available when as is configured for a Visium
1361 processor.
1362 -mtune=arch
1364 This option specifies the target architecture. If an attempt is
1365 made to assemble an instruction that will not execute on the target
1366 architecture, the assembler will issue an error message.
1367 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
1369 The following options are available when as is configured for an Xtensa
1371 processor.
1372 --text-section-literals | --no-text-section-literals
1374 Control the treatment of literal pools. The default is
1375 --no-text-section-literals, which places literals in separate
1376 sections in the output file. This allows the literal pool to be
1377 placed in a data RAM/ROM. With --text-section-literals, the
1378 literals are interspersed in the text section in order to keep them
1379 as close as possible to their references. This may be necessary
1380 for large assembly files, where the literals would otherwise be out
1381 of range of the "L32R" instructions in the text section. Literals
1382 are grouped into pools following ".literal_position" directives or
1383 preceding "ENTRY" instructions. These options only affect literals
1384 referenced via PC-relative "L32R" instructions; literals for
1385 absolute mode "L32R" instructions are handled separately.
1386 --auto-litpools | --no-auto-litpools
1388 Control the treatment of literal pools. The default is
1389 --no-auto-litpools, which in the absence of --text-section-literals
1390 places literals in separate sections in the output file. This
1391 allows the literal pool to be placed in a data RAM/ROM. With
1392 --auto-litpools, the literals are interspersed in the text section
1393 in order to keep them as close as possible to their references,
1394 explicit ".literal_position" directives are not required. This may
1395 be necessary for very large functions, where single literal pool at
1396 the beginning of the function may not be reachable by "L32R"
1397 instructions at the end. These options only affect literals
1398 referenced via PC-relative "L32R" instructions; literals for
1399 absolute mode "L32R" instructions are handled separately. When
1400 used together with --text-section-literals, --auto-litpools takes
1401 precedence.
1402 --absolute-literals | --no-absolute-literals
1404 Indicate to the assembler whether "L32R" instructions use absolute
1405 or PC-relative addressing. If the processor includes the absolute
1406 addressing option, the default is to use absolute "L32R"
1407 relocations. Otherwise, only the PC-relative "L32R" relocations
1408 can be used.
1409 --target-align | --no-target-align
1411 Enable or disable automatic alignment to reduce branch penalties at
1412 some expense in code size. This optimization is enabled by
1413 default. Note that the assembler will always align instructions
1414 like "LOOP" that have fixed alignment requirements.
1415 --longcalls | --no-longcalls
1417 Enable or disable transformation of call instructions to allow
1418 calls across a greater range of addresses. This option should be
1419 used when call targets can potentially be out of range. It may
1420 degrade both code size and performance, but the linker can
1421 generally optimize away the unnecessary overhead when a call ends
1422 up within range. The default is --no-longcalls.
1423 --transform | --no-transform
1425 Enable or disable all assembler transformations of Xtensa
1426 instructions, including both relaxation and optimization. The
1427 default is --transform; --no-transform should only be used in the
1428 rare cases when the instructions must be exactly as specified in
1429 the assembly source. Using --no-transform causes out of range
1430 instruction operands to be errors.
1431 --rename-section oldname=newname
1433 Rename the oldname section to newname. This option can be used
1434 multiple times to rename multiple sections.
1435 --trampolines | --no-trampolines
1437 Enable or disable transformation of jump instructions to allow
1438 jumps across a greater range of addresses. This option should be
1439 used when jump targets can potentially be out of range. In the
1440 absence of such jumps this option does not affect code size or
1441 performance. The default is --trampolines.
1442 The following options are available when as is configured for a Z80
1444 family processor.
1445 -z80
1447 Assemble for Z80 processor.
1448 -r800
1450 Assemble for R800 processor.
1451 -ignore-undocumented-instructions
1453 -Wnud
1454 Assemble undocumented Z80 instructions that also work on R800
1455 without warning.
1456 -ignore-unportable-instructions
1458 -Wnup
1459 Assemble all undocumented Z80 instructions without warning.
1460 -warn-undocumented-instructions
1462 -Wud
1463 Issue a warning for undocumented Z80 instructions that also work on
1464 R800.
1465 -warn-unportable-instructions
1467 -Wup
1468 Issue a warning for undocumented Z80 instructions that do not work
1469 on R800.
1470 -forbid-undocumented-instructions
1472 -Fud
1473 Treat all undocumented instructions as errors.
1474 -forbid-unportable-instructions
1476 -Fup
1477 Treat undocumented Z80 instructions that do not work on R800 as
1478 errors.
1479
1481 gcc(1), ld(1), and the Info entries for binutils and ld.
1482
1484 Copyright (c) 1991-2015 Free Software Foundation, Inc.
1485 Permission is granted to copy, distribute and/or modify this document
1487 under the terms of the GNU Free Documentation License, Version 1.3 or
1488 any later version published by the Free Software Foundation; with no
1489 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
1490 Texts. A copy of the license is included in the section entitled "GNU
1491 Free Documentation License".
1492binutils-2.26 2016-01-25 AS(1)