1AS(1) GNU Development Tools AS(1)
2
6 AS - the portable GNU assembler.
7
9 as [-a[cdghlns][=file]] [--alternate] [-D]
10 [--compress-debug-sections] [--nocompress-debug-sections]
11 [--debug-prefix-map old=new]
12 [--defsym sym=val] [-f] [-g] [--gstabs]
13 [--gstabs+] [--gdwarf-<N>] [--gdwarf-sections]
14 [--gdwarf-cie-version=VERSION]
15 [--help] [-I dir] [-J]
16 [-K] [-L] [--listing-lhs-width=NUM]
17 [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18 [--listing-cont-lines=NUM] [--keep-locals]
19 [--no-pad-sections]
20 [-o objfile] [-R]
21 [--hash-size=NUM] [--reduce-memory-overheads]
22 [--statistics]
23 [-v] [-version] [--version]
24 [-W] [--warn] [--fatal-warnings] [-w] [-x]
25 [-Z] [@FILE]
26 [--sectname-subst] [--size-check=[error|warning]]
27 [--elf-stt-common=[no|yes]]
28 [--generate-missing-build-notes=[no|yes]]
29 [--target-help] [target-options]
30 [--|files ...]
31
33 Target AArch64 options:
34 [-EB|-EL]
35 [-mabi=ABI]
36 Target Alpha options:
38 [-mcpu]
39 [-mdebug | -no-mdebug]
40 [-replace | -noreplace]
41 [-relax] [-g] [-Gsize]
42 [-F] [-32addr]
43 Target ARC options:
45 [-mcpu=cpu]
46 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
47 [-mcode-density]
48 [-mrelax]
49 [-EB|-EL]
50 Target ARM options:
52 [-mcpu=processor[+extension...]]
53 [-march=architecture[+extension...]]
54 [-mfpu=floating-point-format]
55 [-mfloat-abi=abi]
56 [-meabi=ver]
57 [-mthumb]
58 [-EB|-EL]
59 [-mapcs-32|-mapcs-26|-mapcs-float|
60 -mapcs-reentrant]
61 [-mthumb-interwork] [-k]
62 Target Blackfin options:
64 [-mcpu=processor[-sirevision]]
65 [-mfdpic]
66 [-mno-fdpic]
67 [-mnopic]
68 Target BPF options:
70 [-EL] [-EB]
71 Target CRIS options:
73 [--underscore | --no-underscore]
74 [--pic] [-N]
75 [--emulation=criself | --emulation=crisaout]
76 [--march=v0_v10 | --march=v10 | --march=v32 |
77 --march=common_v10_v32]
78 Target C-SKY options:
80 [-march=arch] [-mcpu=cpu]
81 [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
82 [-fpic] [-pic]
83 [-mljump] [-mno-ljump]
84 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
85 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
86 [-mnolrw ] [-mno-lrw]
87 [-melrw] [-mno-elrw]
88 [-mlaf ] [-mliterals-after-func]
89 [-mno-laf] [-mno-literals-after-func]
90 [-mlabr] [-mliterals-after-br]
91 [-mno-labr] [-mnoliterals-after-br]
92 [-mistack] [-mno-istack]
93 [-mhard-float] [-mmp] [-mcp] [-mcache]
94 [-msecurity] [-mtrust]
95 [-mdsp] [-medsp] [-mvdsp]
96 Target D10V options:
98 [-O]
99 Target D30V options:
101 [-O|-n|-N]
102 Target EPIPHANY options:
104 [-mepiphany|-mepiphany16]
105 Target H8/300 options:
107 [-h-tick-hex]
108 Target i386 options:
110 [--32|--x32|--64] [-n]
111 [-march=CPU[+EXTENSION...]] [-mtune=CPU]
112 Target IA-64 options:
114 [-mconstant-gp|-mauto-pic]
115 [-milp32|-milp64|-mlp64|-mp64]
116 [-mle|mbe]
117 [-mtune=itanium1|-mtune=itanium2]
118 [-munwind-check=warning|-munwind-check=error]
119 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
120 [-x|-xexplicit] [-xauto] [-xdebug]
121 Target IP2K options:
123 [-mip2022|-mip2022ext]
124 Target M32C options:
126 [-m32c|-m16c] [-relax] [-h-tick-hex]
127 Target M32R options:
129 [--m32rx|--[no-]warn-explicit-parallel-conflicts|
130 --W[n]p]
131 Target M680X0 options:
133 [-l] [-m68000|-m68010|-m68020|...]
134 Target M68HC11 options:
136 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
137 [-mshort|-mlong]
138 [-mshort-double|-mlong-double]
139 [--force-long-branches] [--short-branches]
140 [--strict-direct-mode] [--print-insn-syntax]
141 [--print-opcodes] [--generate-example]
142 Target MCORE options:
144 [-jsri2bsr] [-sifilter] [-relax]
145 [-mcpu=[210|340]]
146 Target Meta options:
148 [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
149 Target MIPS options:
151 [-nocpp] [-EL] [-EB] [-O[optimization level]]
152 [-g[debug level]] [-G num] [-KPIC] [-call_shared]
153 [-non_shared] [-xgot [-mvxworks-pic]
154 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
155 [-mfp64] [-mgp64] [-mfpxx]
156 [-modd-spreg] [-mno-odd-spreg]
157 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
158 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
159 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
160 [-mips64r3] [-mips64r5] [-mips64r6]
161 [-construct-floats] [-no-construct-floats]
162 [-mignore-branch-isa] [-mno-ignore-branch-isa]
163 [-mnan=encoding]
164 [-trap] [-no-break] [-break] [-no-trap]
165 [-mips16] [-no-mips16]
166 [-mmips16e2] [-mno-mips16e2]
167 [-mmicromips] [-mno-micromips]
168 [-msmartmips] [-mno-smartmips]
169 [-mips3d] [-no-mips3d]
170 [-mdmx] [-no-mdmx]
171 [-mdsp] [-mno-dsp]
172 [-mdspr2] [-mno-dspr2]
173 [-mdspr3] [-mno-dspr3]
174 [-mmsa] [-mno-msa]
175 [-mxpa] [-mno-xpa]
176 [-mmt] [-mno-mt]
177 [-mmcu] [-mno-mcu]
178 [-mcrc] [-mno-crc]
179 [-mginv] [-mno-ginv]
180 [-mloongson-mmi] [-mno-loongson-mmi]
181 [-mloongson-cam] [-mno-loongson-cam]
182 [-mloongson-ext] [-mno-loongson-ext]
183 [-mloongson-ext2] [-mno-loongson-ext2]
184 [-minsn32] [-mno-insn32]
185 [-mfix7000] [-mno-fix7000]
186 [-mfix-rm7000] [-mno-fix-rm7000]
187 [-mfix-vr4120] [-mno-fix-vr4120]
188 [-mfix-vr4130] [-mno-fix-vr4130]
189 [-mfix-r5900] [-mno-fix-r5900]
190 [-mdebug] [-no-mdebug]
191 [-mpdr] [-mno-pdr]
192 Target MMIX options:
194 [--fixed-special-register-names] [--globalize-symbols]
195 [--gnu-syntax] [--relax] [--no-predefined-symbols]
196 [--no-expand] [--no-merge-gregs] [-x]
197 [--linker-allocated-gregs]
198 Target Nios II options:
200 [-relax-all] [-relax-section] [-no-relax]
201 [-EB] [-EL]
202 Target NDS32 options:
204 [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
205 [-misa=isa] [-mabi=abi] [-mall-ext]
206 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
207 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
208 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
209 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
210 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
211 [-mb2bb]
212 Target PDP11 options:
214 [-mpic|-mno-pic] [-mall] [-mno-extensions]
215 [-mextension|-mno-extension]
216 [-mcpu] [-mmachine]
217 Target picoJava options:
219 [-mb|-me]
220 Target PowerPC options:
222 [-a32|-a64]
223 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
224 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
225 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
226 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
227 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
228 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
229 [-many] [-maltivec|-mvsx|-mhtm|-mvle]
230 [-mregnames|-mno-regnames]
231 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
232 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
233 [-msolaris|-mno-solaris]
234 [-nops=count]
235 Target PRU options:
237 [-link-relax]
238 [-mnolink-relax]
239 [-mno-warn-regname-label]
240 Target RISC-V options:
242 [-fpic|-fPIC|-fno-pic]
243 [-march=ISA]
244 [-mabi=ABI]
245 Target RL78 options:
247 [-mg10]
248 [-m32bit-doubles|-m64bit-doubles]
249 Target RX options:
251 [-mlittle-endian|-mbig-endian]
252 [-m32bit-doubles|-m64bit-doubles]
253 [-muse-conventional-section-names]
254 [-msmall-data-limit]
255 [-mpid]
256 [-mrelax]
257 [-mint-register=number]
258 [-mgcc-abi|-mrx-abi]
259 Target s390 options:
261 [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
262 [-mregnames|-mno-regnames]
263 [-mwarn-areg-zero]
264 Target SCORE options:
266 [-EB][-EL][-FIXDD][-NWARN]
267 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
268 [-march=score7][-march=score3]
269 [-USE_R1][-KPIC][-O0][-G num][-V]
270 Target SPARC options:
272 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
273 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
274 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
275 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
276 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
277 -Asparcvisr|-Asparc5]
278 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
279 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
280 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
281 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
282 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
283 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
284 -bump]
285 [-32|-64]
286 [--enforce-aligned-data][--dcti-couples-detect]
287 Target TIC54X options:
289 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
290 [-merrors-to-file <filename>|-me <filename>]
291 Target TIC6X options:
293 [-march=arch] [-mbig-endian|-mlittle-endian]
294 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
295 [-mpic|-mno-pic]
296 Target TILE-Gx options:
298 [-m32|-m64][-EB][-EL]
299 Target Visium options:
301 [-mtune=arch]
302 Target Xtensa options:
304 [--[no-]text-section-literals] [--[no-]auto-litpools]
305 [--[no-]absolute-literals]
306 [--[no-]target-align] [--[no-]longcalls]
307 [--[no-]transform]
308 [--rename-section oldname=newname]
309 [--[no-]trampolines]
310 [--abi-windowed|--abi-call0]
311 Target Z80 options:
313 [-march=CPU[-EXT][+EXT]]
314 [-local-prefix=PREFIX]
315 [-colonless]
316 [-sdcc]
317 [-fp-s=FORMAT]
318 [-fp-d=FORMAT]
319
321 GNU as is really a family of assemblers. If you use (or have used) the
322 GNU assembler on one architecture, you should find a fairly similar
323 environment when you use it on another architecture. Each version has
324 much in common with the others, including object file formats, most
325 assembler directives (often called pseudo-ops) and assembler syntax.
326 as is primarily intended to assemble the output of the GNU C compiler
328 "gcc" for use by the linker "ld". Nevertheless, we've tried to make as
329 assemble correctly everything that other assemblers for the same
330 machine would assemble. Any exceptions are documented explicitly.
331 This doesn't mean as always uses the same syntax as another assembler
332 for the same architecture; for example, we know of several incompatible
333 versions of 680x0 assembly language syntax.
334 Each time you run as it assembles exactly one source program. The
336 source program is made up of one or more files. (The standard input is
337 also a file.)
338 You give as a command line that has zero or more input file names. The
340 input files are read (from left file name to right). A command-line
341 argument (in any position) that has no special meaning is taken to be
342 an input file name.
343 If you give as no file names it attempts to read one input file from
345 the as standard input, which is normally your terminal. You may have
346 to type ctl-D to tell as there is no more program to assemble.
347 Use -- if you need to explicitly name the standard input file in your
349 command line.
350 If the source is empty, as produces a small, empty object file.
352 as may write warnings and error messages to the standard error file
354 (usually your terminal). This should not happen when a compiler runs
355 as automatically. Warnings report an assumption made so that as could
356 keep assembling a flawed program; errors report a grave problem that
357 stops the assembly.
358 If you are invoking as via the GNU C compiler, you can use the -Wa
360 option to pass arguments through to the assembler. The assembler
361 arguments must be separated from each other (and the -Wa) by commas.
362 For example:
363 gcc -c -g -O -Wa,-alh,-L file.c
365 This passes two options to the assembler: -alh (emit a listing to
367 standard output with high-level and assembly source) and -L (retain
368 local symbols in the symbol table).
369 Usually you do not need to use this -Wa mechanism, since many compiler
371 command-line options are automatically passed to the assembler by the
372 compiler. (You can call the GNU compiler driver with the -v option to
373 see precisely what options it passes to each compilation pass,
374 including the assembler.)
375
377 @file
378 Read command-line options from file. The options read are inserted
379 in place of the original @file option. If file does not exist, or
380 cannot be read, then the option will be treated literally, and not
381 removed.
382 Options in file are separated by whitespace. A whitespace
384 character may be included in an option by surrounding the entire
385 option in either single or double quotes. Any character (including
386 a backslash) may be included by prefixing the character to be
387 included with a backslash. The file may itself contain additional
388 @file options; any such options will be processed recursively.
389 -a[cdghlmns]
391 Turn on listings, in any of a variety of ways:
392 -ac omit false conditionals
394 -ad omit debugging directives
396 -ag include general information, like as version and options passed
398 -ah include high-level source
400 -al include assembly
402 -am include macro expansions
404 -an omit forms processing
406 -as include symbols
408 =file
410 set the name of the listing file
411 You may combine these options; for example, use -aln for assembly
413 listing without forms processing. The =file option, if used, must
414 be the last one. By itself, -a defaults to -ahls.
415 --alternate
417 Begin in alternate macro mode.
418 --compress-debug-sections
420 Compress DWARF debug sections using zlib with SHF_COMPRESSED from
421 the ELF ABI. The resulting object file may not be compatible with
422 older linkers and object file utilities. Note if compression would
423 make a given section larger then it is not compressed.
424 --compress-debug-sections=none
426 --compress-debug-sections=zlib
427 --compress-debug-sections=zlib-gnu
428 --compress-debug-sections=zlib-gabi
429 These options control how DWARF debug sections are compressed.
430 --compress-debug-sections=none is equivalent to
431 --nocompress-debug-sections. --compress-debug-sections=zlib and
432 --compress-debug-sections=zlib-gabi are equivalent to
433 --compress-debug-sections. --compress-debug-sections=zlib-gnu
434 compresses DWARF debug sections using zlib. The debug sections are
435 renamed to begin with .zdebug. Note if compression would make a
436 given section larger then it is not compressed nor renamed.
437 --nocompress-debug-sections
439 Do not compress DWARF debug sections. This is usually the default
440 for all targets except the x86/x86_64, but a configure time option
441 can be used to override this.
442 -D Ignored. This option is accepted for script compatibility with
444 calls to other assemblers.
445 --debug-prefix-map old=new
447 When assembling files in directory old, record debugging
448 information describing them as in new instead.
449 --defsym sym=value
451 Define the symbol sym to be value before assembling the input file.
452 value must be an integer constant. As in C, a leading 0x indicates
453 a hexadecimal value, and a leading 0 indicates an octal value. The
454 value of the symbol can be overridden inside a source file via the
455 use of a ".set" pseudo-op.
456 -f "fast"---skip whitespace and comment preprocessing (assume source
458 is compiler output).
459 -g
461 --gen-debug
462 Generate debugging information for each assembler source line using
463 whichever debug format is preferred by the target. This currently
464 means either STABS, ECOFF or DWARF2.
465 --gstabs
467 Generate stabs debugging information for each assembler line. This
468 may help debugging assembler code, if the debugger can handle it.
469 --gstabs+
471 Generate stabs debugging information for each assembler line, with
472 GNU extensions that probably only gdb can handle, and that could
473 make other debuggers crash or refuse to read your program. This
474 may help debugging assembler code. Currently the only GNU
475 extension is the location of the current working directory at
476 assembling time.
477 --gdwarf-2
479 Generate DWARF2 debugging information for each assembler line.
480 This may help debugging assembler code, if the debugger can handle
481 it. Note---this option is only supported by some targets, not all
482 of them.
483 --gdwarf-3
485 This option is the same as the --gdwarf-2 option, except that it
486 allows for the possibility of the generation of extra debug
487 information as per version 3 of the DWARF specification. Note -
488 enabling this option does not guarantee the generation of any extra
489 infortmation, the choice to do so is on a per target basis.
490 --gdwarf-4
492 This option is the same as the --gdwarf-2 option, except that it
493 allows for the possibility of the generation of extra debug
494 information as per version 4 of the DWARF specification. Note -
495 enabling this option does not guarantee the generation of any extra
496 infortmation, the choice to do so is on a per target basis.
497 --gdwarf-5
499 This option is the same as the --gdwarf-2 option, except that it
500 allows for the possibility of the generation of extra debug
501 information as per version 5 of the DWARF specification. Note -
502 enabling this option does not guarantee the generation of any extra
503 infortmation, the choice to do so is on a per target basis.
504 --gdwarf-sections
506 Instead of creating a .debug_line section, create a series of
507 .debug_line.foo sections where foo is the name of the corresponding
508 code section. For example a code section called .text.func will
509 have its dwarf line number information placed into a section called
510 .debug_line.text.func. If the code section is just called .text
511 then debug line section will still be called just .debug_line
512 without any suffix.
513 --gdwarf-cie-version=version
515 Control which version of DWARF Common Information Entries (CIEs)
516 are produced. When this flag is not specificed the default is
517 version 1, though some targets can modify this default. Other
518 possible values for version are 3 or 4.
519 --size-check=error
521 --size-check=warning
522 Issue an error or warning for invalid ELF .size directive.
523 --elf-stt-common=no
525 --elf-stt-common=yes
526 These options control whether the ELF assembler should generate
527 common symbols with the "STT_COMMON" type. The default can be
528 controlled by a configure option --enable-elf-stt-common.
529 --generate-missing-build-notes=yes
531 --generate-missing-build-notes=no
532 These options control whether the ELF assembler should generate GNU
533 Build attribute notes if none are present in the input sources.
534 The default can be controlled by the --enable-generate-build-notes
535 configure option.
536 --help
538 Print a summary of the command-line options and exit.
539 --target-help
541 Print a summary of all target specific options and exit.
542 -I dir
544 Add directory dir to the search list for ".include" directives.
545 -J Don't warn about signed overflow.
547 -K Issue warnings when difference tables altered for long
549 displacements.
550 -L
552 --keep-locals
553 Keep (in the symbol table) local symbols. These symbols start with
554 system-specific local label prefixes, typically .L for ELF systems
555 or L for traditional a.out systems.
556 --listing-lhs-width=number
558 Set the maximum width, in words, of the output data column for an
559 assembler listing to number.
560 --listing-lhs-width2=number
562 Set the maximum width, in words, of the output data column for
563 continuation lines in an assembler listing to number.
564 --listing-rhs-width=number
566 Set the maximum width of an input source line, as displayed in a
567 listing, to number bytes.
568 --listing-cont-lines=number
570 Set the maximum number of lines printed in a listing for a single
571 line of input to number + 1.
572 --no-pad-sections
574 Stop the assembler for padding the ends of output sections to the
575 alignment of that section. The default is to pad the sections, but
576 this can waste space which might be needed on targets which have
577 tight memory constraints.
578 -o objfile
580 Name the object-file output from as objfile.
581 -R Fold the data section into the text section.
583 --hash-size=number
585 Set the default size of GAS's hash tables to a prime number close
586 to number. Increasing this value can reduce the length of time it
587 takes the assembler to perform its tasks, at the expense of
588 increasing the assembler's memory requirements. Similarly reducing
589 this value can reduce the memory requirements at the expense of
590 speed.
591 --reduce-memory-overheads
593 This option reduces GAS's memory requirements, at the expense of
594 making the assembly processes slower. Currently this switch is a
595 synonym for --hash-size=4051, but in the future it may have other
596 effects as well.
597 --sectname-subst
599 Honor substitution sequences in section names.
600 --statistics
602 Print the maximum space (in bytes) and total time (in seconds) used
603 by assembly.
604 --strip-local-absolute
606 Remove local absolute symbols from the outgoing symbol table.
607 -v
609 -version
610 Print the as version.
611 --version
613 Print the as version and exit.
614 -W
616 --no-warn
617 Suppress warning messages.
618 --fatal-warnings
620 Treat warnings as errors.
621 --warn
623 Don't suppress warning messages or treat them as errors.
624 -w Ignored.
626 -x Ignored.
628 -Z Generate an object file even after errors.
630 -- | files ...
632 Standard input, or source files to assemble.
633 The following options are available when as is configured for the
635 64-bit mode of the ARM Architecture (AArch64).
636 -EB This option specifies that the output generated by the assembler
638 should be marked as being encoded for a big-endian processor.
639 -EL This option specifies that the output generated by the assembler
641 should be marked as being encoded for a little-endian processor.
642 -mabi=abi
644 Specify which ABI the source code uses. The recognized arguments
645 are: "ilp32" and "lp64", which decides the generated object file in
646 ELF32 and ELF64 format respectively. The default is "lp64".
647 -mcpu=processor[+extension...]
649 This option specifies the target processor. The assembler will
650 issue an error message if an attempt is made to assemble an
651 instruction which will not execute on the target processor. The
652 following processor names are recognized: "cortex-a34",
653 "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
654 "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
655 "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "ares",
656 "exynos-m1", "falkor", "neoverse-n1", "neoverse-e1", "qdf24xx",
657 "saphira", "thunderx", "vulcan", "xgene1" and "xgene2". The
658 special name "all" may be used to allow the assembler to accept
659 instructions valid for any supported processor, including all
660 optional extensions.
661 In addition to the basic instruction set, the assembler can be told
663 to accept, or restrict, various extension mnemonics that extend the
664 processor.
665 If some implementations of a particular processor can have an
667 extension, then then those extensions are automatically enabled.
668 Consequently, you will not normally have to specify any additional
669 extensions.
670 -march=architecture[+extension...]
672 This option specifies the target architecture. The assembler will
673 issue an error message if an attempt is made to assemble an
674 instruction which will not execute on the target architecture. The
675 following architecture names are recognized: "armv8-a",
676 "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", and
677 "armv8.6-a".
678 If both -mcpu and -march are specified, the assembler will use the
680 setting for -mcpu. If neither are specified, the assembler will
681 default to -mcpu=all.
682 The architecture option can be extended with the same instruction
684 set extension options as the -mcpu option. Unlike -mcpu,
685 extensions are not always enabled by default,
686 -mverbose-error
688 This option enables verbose error messages for AArch64 gas. This
689 option is enabled by default.
690 -mno-verbose-error
692 This option disables verbose error messages in AArch64 gas.
693 The following options are available when as is configured for an Alpha
695 processor.
696 -mcpu
698 This option specifies the target processor. If an attempt is made
699 to assemble an instruction which will not execute on the target
700 processor, the assembler may either expand the instruction as a
701 macro or issue an error message. This option is equivalent to the
702 ".arch" directive.
703 The following processor names are recognized: 21064, "21064a",
705 21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
706 "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
707 "ev67", "ev68". The special name "all" may be used to allow the
708 assembler to accept instructions valid for any Alpha processor.
709 In order to support existing practice in OSF/1 with respect to
711 ".arch", and existing practice within MILO (the Linux ARC
712 bootloader), the numbered processor names (e.g. 21064) enable the
713 processor-specific PALcode instructions, while the "electro-vlasic"
714 names (e.g. "ev4") do not.
715 -mdebug
717 -no-mdebug
718 Enables or disables the generation of ".mdebug" encapsulation for
719 stabs directives and procedure descriptors. The default is to
720 automatically enable ".mdebug" when the first stabs directive is
721 seen.
722 -relax
724 This option forces all relocations to be put into the object file,
725 instead of saving space and resolving some relocations at assembly
726 time. Note that this option does not propagate all symbol
727 arithmetic into the object file, because not all symbol arithmetic
728 can be represented. However, the option can still be useful in
729 specific applications.
730 -replace
732 -noreplace
733 Enables or disables the optimization of procedure calls, both at
734 assemblage and at link time. These options are only available for
735 VMS targets and "-replace" is the default. See section 1.4.1 of
736 the OpenVMS Linker Utility Manual.
737 -g This option is used when the compiler generates debug information.
739 When gcc is using mips-tfile to generate debug information for
740 ECOFF, local labels must be passed through to the object file.
741 Otherwise this option has no effect.
742 -Gsize
744 A local common symbol larger than size is placed in ".bss", while
745 smaller symbols are placed in ".sbss".
746 -F
748 -32addr
749 These options are ignored for backward compatibility.
750 The following options are available when as is configured for an ARC
752 processor.
753 -mcpu=cpu
755 This option selects the core processor variant.
756 -EB | -EL
758 Select either big-endian (-EB) or little-endian (-EL) output.
759 -mcode-density
761 Enable Code Density extenssion instructions.
762 The following options are available when as is configured for the ARM
764 processor family.
765 -mcpu=processor[+extension...]
767 Specify which ARM processor variant is the target.
768 -march=architecture[+extension...]
770 Specify which ARM architecture variant is used by the target.
771 -mfpu=floating-point-format
773 Select which Floating Point architecture is the target.
774 -mfloat-abi=abi
776 Select which floating point ABI is in use.
777 -mthumb
779 Enable Thumb only instruction decoding.
780 -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
782 Select which procedure calling convention is in use.
783 -EB | -EL
785 Select either big-endian (-EB) or little-endian (-EL) output.
786 -mthumb-interwork
788 Specify that the code has been generated with interworking between
789 Thumb and ARM code in mind.
790 -mccs
792 Turns on CodeComposer Studio assembly syntax compatibility mode.
793 -k Specify that PIC code has been generated.
795 The following options are available when as is configured for the
797 Blackfin processor family.
798 -mcpu=processor[-sirevision]
800 This option specifies the target processor. The optional
801 sirevision is not used in assembler. It's here such that GCC can
802 easily pass down its "-mcpu=" option. The assembler will issue an
803 error message if an attempt is made to assemble an instruction
804 which will not execute on the target processor. The following
805 processor names are recognized: "bf504", "bf506", "bf512", "bf514",
806 "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
807 "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
808 implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
809 "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
810 "bf549", "bf549m", "bf561", and "bf592".
811 -mfdpic
813 Assemble for the FDPIC ABI.
814 -mno-fdpic
816 -mnopic
817 Disable -mfdpic.
818 The following options are available when as is configured for the Linux
820 kernel BPF processor family.
821 @chapter BPF Dependent Features
823 Options
825 -EB This option specifies that the assembler should emit big-endian
826 eBPF.
827 -EL This option specifies that the assembler should emit little-endian
829 eBPF.
830 Note that if no endianness option is specified in the command line, the
832 host endianness is used. See the info pages for documentation of the
833 CRIS-specific options.
834 The following options are available when as is configured for the C-SKY
836 processor family.
837 -march=archname
839 Assemble for architecture archname. The --help option lists valid
840 values for archname.
841 -mcpu=cpuname
843 Assemble for architecture cpuname. The --help option lists valid
844 values for cpuname.
845 -EL
847 -mlittle-endian
848 Generate little-endian output.
849 -EB
851 -mbig-endian
852 Generate big-endian output.
853 -fpic
855 -pic
856 Generate position-independent code.
857 -mljump
859 -mno-ljump
860 Enable/disable transformation of the short branch instructions
861 "jbf", "jbt", and "jbr" to "jmpi". This option is for V2
862 processors only. It is ignored on CK801 and CK802 targets, which
863 do not support the "jmpi" instruction, and is enabled by default
864 for other processors.
865 -mbranch-stub
867 -mno-branch-stub
868 Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
869 instructions to the linker.
870 This option is only available for bare-metal C-SKY V2 ELF targets,
872 where it is enabled by default. It cannot be used in code that
873 will be dynamically linked against shared libraries.
874 -force2bsr
876 -mforce2bsr
877 -no-force2bsr
878 -mno-force2bsr
879 Enable/disable transformation of "jbsr" instructions to "bsr".
880 This option is always enabled (and -mno-force2bsr is ignored) for
881 CK801/CK802 targets. It is also always enabled when -mbranch-stub
882 is in effect.
883 -jsri2bsr
885 -mjsri2bsr
886 -no-jsri2bsr
887 -mno-jsri2bsr
888 Enable/disable transformation of "jsri" instructions to "bsr".
889 This option is enabled by default.
890 -mnolrw
892 -mno-lrw
893 Enable/disable transformation of "lrw" instructions into a
894 "movih"/"ori" pair.
895 -melrw
897 -mno-elrw
898 Enable/disable extended "lrw" instructions. This option is enabled
899 by default for CK800-series processors.
900 -mlaf
902 -mliterals-after-func
903 -mno-laf
904 -mno-literals-after-func
905 Enable/disable placement of literal pools after each function.
906 -mlabr
908 -mliterals-after-br
909 -mno-labr
910 -mnoliterals-after-br
911 Enable/disable placement of literal pools after unconditional
912 branches. This option is enabled by default.
913 -mistack
915 -mno-istack
916 Enable/disable interrupt stack instructions. This option is
917 enabled by default on CK801, CK802, and CK802 processors.
918 The following options explicitly enable certain optional instructions.
920 These features are also enabled implicitly by using "-mcpu=" to specify
921 a processor that supports it.
922 -mhard-float
924 Enable hard float instructions.
925 -mmp
927 Enable multiprocessor instructions.
928 -mcp
930 Enable coprocessor instructions.
931 -mcache
933 Enable cache prefetch instruction.
934 -msecurity
936 Enable C-SKY security instructions.
937 -mtrust
939 Enable C-SKY trust instructions.
940 -mdsp
942 Enable DSP instructions.
943 -medsp
945 Enable enhanced DSP instructions.
946 -mvdsp
948 Enable vector DSP instructions.
949 The following options are available when as is configured for an
951 Epiphany processor.
952 -mepiphany
954 Specifies that the both 32 and 16 bit instructions are allowed.
955 This is the default behavior.
956 -mepiphany16
958 Restricts the permitted instructions to just the 16 bit set.
959 The following options are available when as is configured for an H8/300
961 processor. @chapter H8/300 Dependent Features
962 Options
964 The Renesas H8/300 version of "as" has one machine-dependent option:
965 -h-tick-hex
967 Support H'00 style hex constants in addition to 0x00 style.
968 -mach=name
970 Sets the H8300 machine variant. The following machine names are
971 recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
972 "h8300sxn".
973 The following options are available when as is configured for an i386
975 processor.
976 --32 | --x32 | --64
978 Select the word size, either 32 bits or 64 bits. --32 implies
979 Intel i386 architecture, while --x32 and --64 imply AMD x86-64
980 architecture with 32-bit or 64-bit word-size respectively.
981 These options are only available with the ELF object file format,
983 and require that the necessary BFD support has been included (on a
984 32-bit platform you have to add --enable-64-bit-bfd to configure
985 enable 64-bit usage and use x86-64 as target platform).
986 -n By default, x86 GAS replaces multiple nop instructions used for
988 alignment within code sections with multi-byte nop instructions
989 such as leal 0(%esi,1),%esi. This switch disables the optimization
990 if a single byte nop (0x90) is explicitly specified as the fill
991 byte for alignment.
992 --divide
994 On SVR4-derived platforms, the character / is treated as a comment
995 character, which means that it cannot be used in expressions. The
996 --divide option turns / into a normal character. This does not
997 disable / at the beginning of a line starting a comment, or affect
998 using # for starting a comment.
999 -march=CPU[+EXTENSION...]
1001 This option specifies the target processor. The assembler will
1002 issue an error message if an attempt is made to assemble an
1003 instruction which will not execute on the target processor. The
1004 following processor names are recognized: "i8086", "i186", "i286",
1005 "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
1006 "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
1007 "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
1008 "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
1009 "bdver3", "bdver4", "znver1", "znver2", "btver1", "btver2",
1010 "generic32" and "generic64".
1011 In addition to the basic instruction set, the assembler can be told
1013 to accept various extension mnemonics. For example,
1014 "-march=i686+sse4+vmx" extends i686 with sse4 and vmx. The
1015 following extensions are currently supported: 8087, 287, 387, 687,
1016 "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1017 "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1018 "sse4.1", "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nosse4a",
1019 "nossse3", "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2",
1020 "noavx", "noavx2", "adx", "rdseed", "prfchw", "smap", "mpx", "sha",
1021 "rdpid", "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq",
1022 "prefetchwt1", "clflushopt", "se1", "clwb", "movdiri", "movdir64b",
1023 "enqcmd", "serialize", "tsxldtrk", "avx512f", "avx512cd",
1024 "avx512er", "avx512pf", "avx512vl", "avx512bw", "avx512dq",
1025 "avx512ifma", "avx512vbmi", "avx512_4fmaps", "avx512_4vnniw",
1026 "avx512_vpopcntdq", "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1027 "avx512_vp2intersect", "avx512_bf16", "noavx512f", "noavx512cd",
1028 "noavx512er", "noavx512pf", "noavx512vl", "noavx512bw",
1029 "noavx512dq", "noavx512ifma", "noavx512vbmi", "noavx512_4fmaps",
1030 "noavx512_4vnniw", "noavx512_vpopcntdq", "noavx512_vbmi2",
1031 "noavx512_vnni", "noavx512_bitalg", "noavx512_vp2intersect",
1032 "noavx512_bf16", "noenqcmd", "noserialize", "notsxldtrk", "vmx",
1033 "vmfunc", "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes",
1034 "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe",
1035 "ept", "lzcnt", "popcnt", "hle", "rtm", "invpcid", "clflush",
1036 "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg", "cldemote",
1037 "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop", "cx16",
1038 "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme" and
1039 "padlock". Note that rather than extending a basic instruction
1040 set, the extension mnemonics starting with "no" revoke the
1041 respective functionality.
1042 When the ".arch" directive is used with -march, the ".arch"
1044 directive will take precedent.
1045 -mtune=CPU
1047 This option specifies a processor to optimize for. When used in
1048 conjunction with the -march option, only instructions of the
1049 processor specified by the -march option will be generated.
1050 Valid CPU values are identical to the processor list of -march=CPU.
1052 -msse2avx
1054 This option specifies that the assembler should encode SSE
1055 instructions with VEX prefix.
1056 -msse-check=none
1058 -msse-check=warning
1059 -msse-check=error
1060 These options control if the assembler should check SSE
1061 instructions. -msse-check=none will make the assembler not to
1062 check SSE instructions, which is the default. -msse-check=warning
1063 will make the assembler issue a warning for any SSE instruction.
1064 -msse-check=error will make the assembler issue an error for any
1065 SSE instruction.
1066 -mavxscalar=128
1068 -mavxscalar=256
1069 These options control how the assembler should encode scalar AVX
1070 instructions. -mavxscalar=128 will encode scalar AVX instructions
1071 with 128bit vector length, which is the default. -mavxscalar=256
1072 will encode scalar AVX instructions with 256bit vector length.
1073 WARNING: Don't use this for production code - due to CPU errata the
1075 resulting code may not work on certain models.
1076 -mvexwig=0
1078 -mvexwig=1
1079 These options control how the assembler should encode VEX.W-ignored
1080 (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX
1081 instructions with vex.w = 0, which is the default. -mvexwig=1 will
1082 encode WIG EVEX instructions with vex.w = 1.
1083 WARNING: Don't use this for production code - due to CPU errata the
1085 resulting code may not work on certain models.
1086 -mevexlig=128
1088 -mevexlig=256
1089 -mevexlig=512
1090 These options control how the assembler should encode length-
1091 ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG
1092 EVEX instructions with 128bit vector length, which is the default.
1093 -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1094 with 256bit and 512bit vector length, respectively.
1095 -mevexwig=0
1097 -mevexwig=1
1098 These options control how the assembler should encode w-ignored
1099 (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX
1100 instructions with evex.w = 0, which is the default. -mevexwig=1
1101 will encode WIG EVEX instructions with evex.w = 1.
1102 -mmnemonic=att
1104 -mmnemonic=intel
1105 This option specifies instruction mnemonic for matching
1106 instructions. The ".att_mnemonic" and ".intel_mnemonic" directives
1107 will take precedent.
1108 -msyntax=att
1110 -msyntax=intel
1111 This option specifies instruction syntax when processing
1112 instructions. The ".att_syntax" and ".intel_syntax" directives
1113 will take precedent.
1114 -mnaked-reg
1116 This option specifies that registers don't require a % prefix. The
1117 ".att_syntax" and ".intel_syntax" directives will take precedent.
1118 -madd-bnd-prefix
1120 This option forces the assembler to add BND prefix to all branches,
1121 even if such prefix was not explicitly specified in the source
1122 code.
1123 -mno-shared
1125 On ELF target, the assembler normally optimizes out non-PLT
1126 relocations against defined non-weak global branch targets with
1127 default visibility. The -mshared option tells the assembler to
1128 generate code which may go into a shared library where all non-weak
1129 global branch targets with default visibility can be preempted.
1130 The resulting code is slightly bigger. This option only affects
1131 the handling of branch instructions.
1132 -mbig-obj
1134 On PE/COFF target this option forces the use of big object file
1135 format, which allows more than 32768 sections.
1136 -momit-lock-prefix=no
1138 -momit-lock-prefix=yes
1139 These options control how the assembler should encode lock prefix.
1140 This option is intended as a workaround for processors, that fail
1141 on lock prefix. This option can only be safely used with single-
1142 core, single-thread computers -momit-lock-prefix=yes will omit all
1143 lock prefixes. -momit-lock-prefix=no will encode lock prefix as
1144 usual, which is the default.
1145 -mfence-as-lock-add=no
1147 -mfence-as-lock-add=yes
1148 These options control how the assembler should encode lfence,
1149 mfence and sfence. -mfence-as-lock-add=yes will encode lfence,
1150 mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1151 addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will
1152 encode lfence, mfence and sfence as usual, which is the default.
1153 -mrelax-relocations=no
1155 -mrelax-relocations=yes
1156 These options control whether the assembler should generate relax
1157 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1158 and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1159 -mrelax-relocations=yes will generate relax relocations.
1160 -mrelax-relocations=no will not generate relax relocations. The
1161 default can be controlled by a configure option
1162 --enable-x86-relax-relocations.
1163 -malign-branch-boundary=NUM
1165 This option controls how the assembler should align branches with
1166 segment prefixes or NOP. NUM must be a power of 2. It should be 0
1167 or no less than 16. Branches will be aligned within NUM byte
1168 boundary. -malign-branch-boundary=0, which is the default, doesn't
1169 align branches.
1170 -malign-branch=TYPE[+TYPE...]
1172 This option specifies types of branches to align. TYPE is
1173 combination of jcc, which aligns conditional jumps, fused, which
1174 aligns fused conditional jumps, jmp, which aligns unconditional
1175 jumps, call which aligns calls, ret, which aligns rets, indirect,
1176 which aligns indirect jumps and calls. The default is
1177 -malign-branch=jcc+fused+jmp.
1178 -malign-branch-prefix-size=NUM
1180 This option specifies the maximum number of prefixes on an
1181 instruction to align branches. NUM should be between 0 and 5. The
1182 default NUM is 5.
1183 -mbranches-within-32B-boundaries
1185 This option aligns conditional jumps, fused conditional jumps and
1186 unconditional jumps within 32 byte boundary with up to 5 segment
1187 prefixes on an instruction. It is equivalent to
1188 -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1189 -malign-branch-prefix-size=5. The default doesn't align branches.
1190 -mlfence-after-load=no
1192 -mlfence-after-load=yes
1193 These options control whether the assembler should generate lfence
1194 after load instructions. -mlfence-after-load=yes will generate
1195 lfence. -mlfence-after-load=no will not generate lfence, which is
1196 the default.
1197 -mlfence-before-indirect-branch=none
1199 -mlfence-before-indirect-branch=all
1200 -mlfence-before-indirect-branch=register
1201 -mlfence-before-indirect-branch=memory
1202 These options control whether the assembler should generate lfence
1203 before indirect near branch instructions.
1204 -mlfence-before-indirect-branch=all will generate lfence before
1205 indirect near branch via register and issue a warning before
1206 indirect near branch via memory. It also implicitly sets
1207 -mlfence-before-ret=shl when there's no explict
1208 -mlfence-before-ret=. -mlfence-before-indirect-branch=register
1209 will generate lfence before indirect near branch via register.
1210 -mlfence-before-indirect-branch=memory will issue a warning before
1211 indirect near branch via memory.
1212 -mlfence-before-indirect-branch=none will not generate lfence nor
1213 issue warning, which is the default. Note that lfence won't be
1214 generated before indirect near branch via register with
1215 -mlfence-after-load=yes since lfence will be generated after
1216 loading branch target register.
1217 -mlfence-before-ret=none
1219 -mlfence-before-ret=shl
1220 -mlfence-before-ret=or
1221 -mlfence-before-ret=yes
1222 -mlfence-before-ret=not
1223 These options control whether the assembler should generate lfence
1224 before ret. -mlfence-before-ret=or will generate generate or
1225 instruction with lfence. -mlfence-before-ret=shl/yes will generate
1226 shl instruction with lfence. -mlfence-before-ret=not will generate
1227 not instruction with lfence. -mlfence-before-ret=none will not
1228 generate lfence, which is the default.
1229 -mx86-used-note=no
1231 -mx86-used-note=yes
1232 These options control whether the assembler should generate
1233 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1234 property notes. The default can be controlled by the
1235 --enable-x86-used-note configure option.
1236 -mevexrcig=rne
1238 -mevexrcig=rd
1239 -mevexrcig=ru
1240 -mevexrcig=rz
1241 These options control how the assembler should encode SAE-only EVEX
1242 instructions. -mevexrcig=rne will encode RC bits of EVEX
1243 instruction with 00, which is the default. -mevexrcig=rd,
1244 -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1245 instructions with 01, 10 and 11 RC bits, respectively.
1246 -mamd64
1248 -mintel64
1249 This option specifies that the assembler should accept only AMD64
1250 or Intel64 ISA in 64-bit mode. The default is to accept common,
1251 Intel64 only and AMD64 ISAs.
1252 -O0 | -O | -O1 | -O2 | -Os
1254 Optimize instruction encoding with smaller instruction size. -O
1255 and -O1 encode 64-bit register load instructions with 64-bit
1256 immediate as 32-bit register load instructions with 31-bit or
1257 32-bits immediates, encode 64-bit register clearing instructions
1258 with 32-bit register clearing instructions, encode 256-bit/512-bit
1259 VEX/EVEX vector register clearing instructions with 128-bit VEX
1260 vector register clearing instructions, encode 128-bit/256-bit EVEX
1261 vector register load/store instructions with VEX vector register
1262 load/store instructions, and encode 128-bit/256-bit EVEX packed
1263 integer logical instructions with 128-bit/256-bit VEX packed
1264 integer logical.
1265 -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1267 vector register clearing instructions with 128-bit EVEX vector
1268 register clearing instructions. In 64-bit mode VEX encoded
1269 instructions with commutative source operands will also have their
1270 source operands swapped if this allows using the 2-byte VEX prefix
1271 form instead of the 3-byte one. Certain forms of AND as well as OR
1272 with the same (register) operand specified twice will also be
1273 changed to TEST.
1274 -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1276 64-bit register tests with immediate as 8-bit register test with
1277 immediate. -O0 turns off this optimization.
1278 The following options are available when as is configured for the
1280 Ubicom IP2K series.
1281 -mip2022ext
1283 Specifies that the extended IP2022 instructions are allowed.
1284 -mip2022
1286 Restores the default behaviour, which restricts the permitted
1287 instructions to just the basic IP2022 ones.
1288 The following options are available when as is configured for the
1290 Renesas M32C and M16C processors.
1291 -m32c
1293 Assemble M32C instructions.
1294 -m16c
1296 Assemble M16C instructions (the default).
1297 -relax
1299 Enable support for link-time relaxations.
1300 -h-tick-hex
1302 Support H'00 style hex constants in addition to 0x00 style.
1303 The following options are available when as is configured for the
1305 Renesas M32R (formerly Mitsubishi M32R) series.
1306 --m32rx
1308 Specify which processor in the M32R family is the target. The
1309 default is normally the M32R, but this option changes it to the
1310 M32RX.
1311 --warn-explicit-parallel-conflicts or --Wp
1313 Produce warning messages when questionable parallel constructs are
1314 encountered.
1315 --no-warn-explicit-parallel-conflicts or --Wnp
1317 Do not produce warning messages when questionable parallel
1318 constructs are encountered.
1319 The following options are available when as is configured for the
1321 Motorola 68000 series.
1322 -l Shorten references to undefined symbols, to one word instead of
1324 two.
1325 -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1327 | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1328 | -m68333 | -m68340 | -mcpu32 | -m5200
1329 Specify what processor in the 68000 family is the target. The
1330 default is normally the 68020, but this can be changed at
1331 configuration time.
1332 -m68881 | -m68882 | -mno-68881 | -mno-68882
1334 The target machine does (or does not) have a floating-point
1335 coprocessor. The default is to assume a coprocessor for 68020,
1336 68030, and cpu32. Although the basic 68000 is not compatible with
1337 the 68881, a combination of the two can be specified, since it's
1338 possible to do emulation of the coprocessor instructions with the
1339 main processor.
1340 -m68851 | -mno-68851
1342 The target machine does (or does not) have a memory-management unit
1343 coprocessor. The default is to assume an MMU for 68020 and up.
1344 The following options are available when as is configured for an Altera
1346 Nios II processor.
1347 -relax-section
1349 Replace identified out-of-range branches with PC-relative "jmp"
1350 sequences when possible. The generated code sequences are suitable
1351 for use in position-independent code, but there is a practical
1352 limit on the extended branch range because of the length of the
1353 sequences. This option is the default.
1354 -relax-all
1356 Replace branch instructions not determinable to be in range and all
1357 call instructions with "jmp" and "callr" sequences (respectively).
1358 This option generates absolute relocations against the target
1359 symbols and is not appropriate for position-independent code.
1360 -no-relax
1362 Do not replace any branches or calls.
1363 -EB Generate big-endian output.
1365 -EL Generate little-endian output. This is the default.
1367 -march=architecture
1369 This option specifies the target architecture. The assembler
1370 issues an error message if an attempt is made to assemble an
1371 instruction which will not execute on the target architecture. The
1372 following architecture names are recognized: "r1", "r2". The
1373 default is "r1".
1374 The following options are available when as is configured for a PRU
1376 processor.
1377 -mlink-relax
1379 Assume that LD would optimize LDI32 instructions by checking the
1380 upper 16 bits of the expression. If they are all zeros, then LD
1381 would shorten the LDI32 instruction to a single LDI. In such case
1382 "as" will output DIFF relocations for diff expressions.
1383 -mno-link-relax
1385 Assume that LD would not optimize LDI32 instructions. As a
1386 consequence, DIFF relocations will not be emitted.
1387 -mno-warn-regname-label
1389 Do not warn if a label name matches a register name. Usually
1390 assembler programmers will want this warning to be emitted. C
1391 compilers may want to turn this off.
1392 The following options are available when as is configured for a MIPS
1394 processor.
1395 -G num
1397 This option sets the largest size of an object that can be
1398 referenced implicitly with the "gp" register. It is only accepted
1399 for targets that use ECOFF format, such as a DECstation running
1400 Ultrix. The default value is 8.
1401 -EB Generate "big endian" format output.
1403 -EL Generate "little endian" format output.
1405 -mips1
1407 -mips2
1408 -mips3
1409 -mips4
1410 -mips5
1411 -mips32
1412 -mips32r2
1413 -mips32r3
1414 -mips32r5
1415 -mips32r6
1416 -mips64
1417 -mips64r2
1418 -mips64r3
1419 -mips64r5
1420 -mips64r6
1421 Generate code for a particular MIPS Instruction Set Architecture
1422 level. -mips1 is an alias for -march=r3000, -mips2 is an alias for
1423 -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1424 alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3,
1425 -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1426 -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1427 MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1428 MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1429 Release 6 ISA processors, respectively.
1430 -march=cpu
1432 Generate code for a particular MIPS CPU.
1433 -mtune=cpu
1435 Schedule and tune for a particular MIPS CPU.
1436 -mfix7000
1438 -mno-fix7000
1439 Cause nops to be inserted if the read of the destination register
1440 of an mfhi or mflo instruction occurs in the following two
1441 instructions.
1442 -mfix-rm7000
1444 -mno-fix-rm7000
1445 Cause nops to be inserted if a dmult or dmultu instruction is
1446 followed by a load instruction.
1447 -mfix-r5900
1449 -mno-fix-r5900
1450 Do not attempt to schedule the preceding instruction into the delay
1451 slot of a branch instruction placed at the end of a short loop of
1452 six instructions or fewer and always schedule a "nop" instruction
1453 there instead. The short loop bug under certain conditions causes
1454 loops to execute only once or twice, due to a hardware bug in the
1455 R5900 chip.
1456 -mdebug
1458 -no-mdebug
1459 Cause stabs-style debugging output to go into an ECOFF-style
1460 .mdebug section instead of the standard ELF .stabs sections.
1461 -mpdr
1463 -mno-pdr
1464 Control generation of ".pdr" sections.
1465 -mgp32
1467 -mfp32
1468 The register sizes are normally inferred from the ISA and ABI, but
1469 these flags force a certain group of registers to be treated as 32
1470 bits wide at all times. -mgp32 controls the size of general-
1471 purpose registers and -mfp32 controls the size of floating-point
1472 registers.
1473 -mgp64
1475 -mfp64
1476 The register sizes are normally inferred from the ISA and ABI, but
1477 these flags force a certain group of registers to be treated as 64
1478 bits wide at all times. -mgp64 controls the size of general-
1479 purpose registers and -mfp64 controls the size of floating-point
1480 registers.
1481 -mfpxx
1483 The register sizes are normally inferred from the ISA and ABI, but
1484 using this flag in combination with -mabi=32 enables an ABI variant
1485 which will operate correctly with floating-point registers which
1486 are 32 or 64 bits wide.
1487 -modd-spreg
1489 -mno-odd-spreg
1490 Enable use of floating-point operations on odd-numbered single-
1491 precision registers when supported by the ISA. -mfpxx implies
1492 -mno-odd-spreg, otherwise the default is -modd-spreg.
1493 -mips16
1495 -no-mips16
1496 Generate code for the MIPS 16 processor. This is equivalent to
1497 putting ".module mips16" at the start of the assembly file.
1498 -no-mips16 turns off this option.
1499 -mmips16e2
1501 -mno-mips16e2
1502 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
1503 equivalent to putting ".module mips16e2" at the start of the
1504 assembly file. -mno-mips16e2 turns off this option.
1505 -mmicromips
1507 -mno-micromips
1508 Generate code for the microMIPS processor. This is equivalent to
1509 putting ".module micromips" at the start of the assembly file.
1510 -mno-micromips turns off this option. This is equivalent to
1511 putting ".module nomicromips" at the start of the assembly file.
1512 -msmartmips
1514 -mno-smartmips
1515 Enables the SmartMIPS extension to the MIPS32 instruction set.
1516 This is equivalent to putting ".module smartmips" at the start of
1517 the assembly file. -mno-smartmips turns off this option.
1518 -mips3d
1520 -no-mips3d
1521 Generate code for the MIPS-3D Application Specific Extension. This
1522 tells the assembler to accept MIPS-3D instructions. -no-mips3d
1523 turns off this option.
1524 -mdmx
1526 -no-mdmx
1527 Generate code for the MDMX Application Specific Extension. This
1528 tells the assembler to accept MDMX instructions. -no-mdmx turns
1529 off this option.
1530 -mdsp
1532 -mno-dsp
1533 Generate code for the DSP Release 1 Application Specific Extension.
1534 This tells the assembler to accept DSP Release 1 instructions.
1535 -mno-dsp turns off this option.
1536 -mdspr2
1538 -mno-dspr2
1539 Generate code for the DSP Release 2 Application Specific Extension.
1540 This option implies -mdsp. This tells the assembler to accept DSP
1541 Release 2 instructions. -mno-dspr2 turns off this option.
1542 -mdspr3
1544 -mno-dspr3
1545 Generate code for the DSP Release 3 Application Specific Extension.
1546 This option implies -mdsp and -mdspr2. This tells the assembler to
1547 accept DSP Release 3 instructions. -mno-dspr3 turns off this
1548 option.
1549 -mmsa
1551 -mno-msa
1552 Generate code for the MIPS SIMD Architecture Extension. This tells
1553 the assembler to accept MSA instructions. -mno-msa turns off this
1554 option.
1555 -mxpa
1557 -mno-xpa
1558 Generate code for the MIPS eXtended Physical Address (XPA)
1559 Extension. This tells the assembler to accept XPA instructions.
1560 -mno-xpa turns off this option.
1561 -mmt
1563 -mno-mt
1564 Generate code for the MT Application Specific Extension. This
1565 tells the assembler to accept MT instructions. -mno-mt turns off
1566 this option.
1567 -mmcu
1569 -mno-mcu
1570 Generate code for the MCU Application Specific Extension. This
1571 tells the assembler to accept MCU instructions. -mno-mcu turns off
1572 this option.
1573 -mcrc
1575 -mno-crc
1576 Generate code for the MIPS cyclic redundancy check (CRC)
1577 Application Specific Extension. This tells the assembler to accept
1578 CRC instructions. -mno-crc turns off this option.
1579 -mginv
1581 -mno-ginv
1582 Generate code for the Global INValidate (GINV) Application Specific
1583 Extension. This tells the assembler to accept GINV instructions.
1584 -mno-ginv turns off this option.
1585 -mloongson-mmi
1587 -mno-loongson-mmi
1588 Generate code for the Loongson MultiMedia extensions Instructions
1589 (MMI) Application Specific Extension. This tells the assembler to
1590 accept MMI instructions. -mno-loongson-mmi turns off this option.
1591 -mloongson-cam
1593 -mno-loongson-cam
1594 Generate code for the Loongson Content Address Memory (CAM)
1595 instructions. This tells the assembler to accept Loongson CAM
1596 instructions. -mno-loongson-cam turns off this option.
1597 -mloongson-ext
1599 -mno-loongson-ext
1600 Generate code for the Loongson EXTensions (EXT) instructions. This
1601 tells the assembler to accept Loongson EXT instructions.
1602 -mno-loongson-ext turns off this option.
1603 -mloongson-ext2
1605 -mno-loongson-ext2
1606 Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1607 This option implies -mloongson-ext. This tells the assembler to
1608 accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off
1609 this option.
1610 -minsn32
1612 -mno-insn32
1613 Only use 32-bit instruction encodings when generating code for the
1614 microMIPS processor. This option inhibits the use of any 16-bit
1615 instructions. This is equivalent to putting ".set insn32" at the
1616 start of the assembly file. -mno-insn32 turns off this option.
1617 This is equivalent to putting ".set noinsn32" at the start of the
1618 assembly file. By default -mno-insn32 is selected, allowing all
1619 instructions to be used.
1620 --construct-floats
1622 --no-construct-floats
1623 The --no-construct-floats option disables the construction of
1624 double width floating point constants by loading the two halves of
1625 the value into the two single width floating point registers that
1626 make up the double width register. By default --construct-floats
1627 is selected, allowing construction of these floating point
1628 constants.
1629 --relax-branch
1631 --no-relax-branch
1632 The --relax-branch option enables the relaxation of out-of-range
1633 branches. By default --no-relax-branch is selected, causing any
1634 out-of-range branches to produce an error.
1635 -mignore-branch-isa
1637 -mno-ignore-branch-isa
1638 Ignore branch checks for invalid transitions between ISA modes.
1639 The semantics of branches does not provide for an ISA mode switch,
1640 so in most cases the ISA mode a branch has been encoded for has to
1641 be the same as the ISA mode of the branch's target label.
1642 Therefore GAS has checks implemented that verify in branch assembly
1643 that the two ISA modes match. -mignore-branch-isa disables these
1644 checks. By default -mno-ignore-branch-isa is selected, causing any
1645 invalid branch requiring a transition between ISA modes to produce
1646 an error.
1647 -mnan=encoding
1649 Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1650 (-mnan=legacy) NaN encoding format. The latter is the default.
1651 --emulation=name
1653 This option was formerly used to switch between ELF and ECOFF
1654 output on targets like IRIX 5 that supported both. MIPS ECOFF
1655 support was removed in GAS 2.24, so the option now serves little
1656 purpose. It is retained for backwards compatibility.
1657 The available configuration names are: mipself, mipslelf and
1659 mipsbelf. Choosing mipself now has no effect, since the output is
1660 always ELF. mipslelf and mipsbelf select little- and big-endian
1661 output respectively, but -EL and -EB are now the preferred options
1662 instead.
1663 -nocpp
1665 as ignores this option. It is accepted for compatibility with the
1666 native tools.
1667 --trap
1669 --no-trap
1670 --break
1671 --no-break
1672 Control how to deal with multiplication overflow and division by
1673 zero. --trap or --no-break (which are synonyms) take a trap
1674 exception (and only work for Instruction Set Architecture level 2
1675 and higher); --break or --no-trap (also synonyms, and the default)
1676 take a break exception.
1677 -n When this option is used, as will issue a warning every time it
1679 generates a nop instruction from a macro.
1680 The following options are available when as is configured for a Meta
1682 processor.
1683 "-mcpu=metac11"
1685 Generate code for Meta 1.1.
1686 "-mcpu=metac12"
1688 Generate code for Meta 1.2.
1689 "-mcpu=metac21"
1691 Generate code for Meta 2.1.
1692 "-mfpu=metac21"
1694 Allow code to use FPU hardware of Meta 2.1.
1695 See the info pages for documentation of the MMIX-specific options.
1697 The following options are available when as is configured for a NDS32
1699 processor.
1700 "-O1"
1702 Optimize for performance.
1703 "-Os"
1705 Optimize for space.
1706 "-EL"
1708 Produce little endian data output.
1709 "-EB"
1711 Produce little endian data output.
1712 "-mpic"
1714 Generate PIC.
1715 "-mno-fp-as-gp-relax"
1717 Suppress fp-as-gp relaxation for this file.
1718 "-mb2bb-relax"
1720 Back-to-back branch optimization.
1721 "-mno-all-relax"
1723 Suppress all relaxation for this file.
1724 "-march=<arch name>"
1726 Assemble for architecture <arch name> which could be v3, v3j, v3m,
1727 v3f, v3s, v2, v2j, v2f, v2s.
1728 "-mbaseline=<baseline>"
1730 Assemble for baseline <baseline> which could be v2, v3, v3m.
1731 "-mfpu-freg=FREG"
1733 Specify a FPU configuration.
1734 "0 8 SP / 4 DP registers"
1736 "1 16 SP / 8 DP registers"
1737 "2 32 SP / 16 DP registers"
1738 "3 32 SP / 32 DP registers"
1739 "-mabi=abi"
1740 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1741 "-m[no-]mac"
1743 Enable/Disable Multiply instructions support.
1744 "-m[no-]div"
1746 Enable/Disable Divide instructions support.
1747 "-m[no-]16bit-ext"
1749 Enable/Disable 16-bit extension
1750 "-m[no-]dx-regs"
1752 Enable/Disable d0/d1 registers
1753 "-m[no-]perf-ext"
1755 Enable/Disable Performance extension
1756 "-m[no-]perf2-ext"
1758 Enable/Disable Performance extension 2
1759 "-m[no-]string-ext"
1761 Enable/Disable String extension
1762 "-m[no-]reduced-regs"
1764 Enable/Disable Reduced Register configuration (GPR16) option
1765 "-m[no-]audio-isa-ext"
1767 Enable/Disable AUDIO ISA extension
1768 "-m[no-]fpu-sp-ext"
1770 Enable/Disable FPU SP extension
1771 "-m[no-]fpu-dp-ext"
1773 Enable/Disable FPU DP extension
1774 "-m[no-]fpu-fma"
1776 Enable/Disable FPU fused-multiply-add instructions
1777 "-mall-ext"
1779 Turn on all extensions and instructions support
1780 The following options are available when as is configured for a PowerPC
1782 processor.
1783 -a32
1785 Generate ELF32 or XCOFF32.
1786 -a64
1788 Generate ELF64 or XCOFF64.
1789 -K PIC
1791 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1792 -mpwrx | -mpwr2
1794 Generate code for POWER/2 (RIOS2).
1795 -mpwr
1797 Generate code for POWER (RIOS1)
1798 -m601
1800 Generate code for PowerPC 601.
1801 -mppc, -mppc32, -m603, -m604
1803 Generate code for PowerPC 603/604.
1804 -m403, -m405
1806 Generate code for PowerPC 403/405.
1807 -m440
1809 Generate code for PowerPC 440. BookE and some 405 instructions.
1810 -m464
1812 Generate code for PowerPC 464.
1813 -m476
1815 Generate code for PowerPC 476.
1816 -m7400, -m7410, -m7450, -m7455
1818 Generate code for PowerPC 7400/7410/7450/7455.
1819 -m750cl, -mgekko, -mbroadway
1821 Generate code for PowerPC 750CL/Gekko/Broadway.
1822 -m821, -m850, -m860
1824 Generate code for PowerPC 821/850/860.
1825 -mppc64, -m620
1827 Generate code for PowerPC 620/625/630.
1828 -me500, -me500x2
1830 Generate code for Motorola e500 core complex.
1831 -me500mc
1833 Generate code for Freescale e500mc core complex.
1834 -me500mc64
1836 Generate code for Freescale e500mc64 core complex.
1837 -me5500
1839 Generate code for Freescale e5500 core complex.
1840 -me6500
1842 Generate code for Freescale e6500 core complex.
1843 -mspe
1845 Generate code for Motorola SPE instructions.
1846 -mspe2
1848 Generate code for Freescale SPE2 instructions.
1849 -mtitan
1851 Generate code for AppliedMicro Titan core complex.
1852 -mppc64bridge
1854 Generate code for PowerPC 64, including bridge insns.
1855 -mbooke
1857 Generate code for 32-bit BookE.
1858 -ma2
1860 Generate code for A2 architecture.
1861 -me300
1863 Generate code for PowerPC e300 family.
1864 -maltivec
1866 Generate code for processors with AltiVec instructions.
1867 -mvle
1869 Generate code for Freescale PowerPC VLE instructions.
1870 -mvsx
1872 Generate code for processors with Vector-Scalar (VSX) instructions.
1873 -mhtm
1875 Generate code for processors with Hardware Transactional Memory
1876 instructions.
1877 -mpower4, -mpwr4
1879 Generate code for Power4 architecture.
1880 -mpower5, -mpwr5, -mpwr5x
1882 Generate code for Power5 architecture.
1883 -mpower6, -mpwr6
1885 Generate code for Power6 architecture.
1886 -mpower7, -mpwr7
1888 Generate code for Power7 architecture.
1889 -mpower8, -mpwr8
1891 Generate code for Power8 architecture.
1892 -mpower9, -mpwr9
1894 Generate code for Power9 architecture.
1895 -mpower10, -mpwr10
1897 Generate code for Power10 architecture.
1898 -mcell
1900 -mcell
1901 Generate code for Cell Broadband Engine architecture.
1902 -mcom
1904 Generate code Power/PowerPC common instructions.
1905 -many
1907 Generate code for any architecture (PWR/PWRX/PPC).
1908 -mregnames
1910 Allow symbolic names for registers.
1911 -mno-regnames
1913 Do not allow symbolic names for registers.
1914 -mrelocatable
1916 Support for GCC's -mrelocatable option.
1917 -mrelocatable-lib
1919 Support for GCC's -mrelocatable-lib option.
1920 -memb
1922 Set PPC_EMB bit in ELF flags.
1923 -mlittle, -mlittle-endian, -le
1925 Generate code for a little endian machine.
1926 -mbig, -mbig-endian, -be
1928 Generate code for a big endian machine.
1929 -msolaris
1931 Generate code for Solaris.
1932 -mno-solaris
1934 Do not generate code for Solaris.
1935 -nops=count
1937 If an alignment directive inserts more than count nops, put a
1938 branch at the beginning to skip execution of the nops.
1939 The following options are available when as is configured for a RISC-V
1941 processor.
1942 -fpic
1944 -fPIC
1945 Generate position-independent code
1946 -fno-pic
1948 Don't generate position-independent code (default)
1949 -march=ISA
1951 Select the base isa, as specified by ISA. For example
1952 -march=rv32ima. If this option and the architecture attributes
1953 aren't set, then assembler will check the default configure setting
1954 --with-arch=ISA.
1955 -misa-spec=ISAspec
1957 Select the default isa spec version. If the version of ISA isn't
1958 set by -march, then assembler helps to set the version according to
1959 the default chosen spec. If this option isn't set, then assembler
1960 will check the default configure setting --with-isa-spec=ISAspec.
1961 -mpriv-spec=PRIVspec
1963 Select the privileged spec version. We can decide whether the CSR
1964 is valid or not according to the chosen spec. If this option and
1965 the privilege attributes aren't set, then assembler will check the
1966 default configure setting --with-priv-spec=PRIVspec.
1967 -mabi=ABI
1969 Selects the ABI, which is either "ilp32" or "lp64", optionally
1970 followed by "f", "d", or "q" to indicate single-precision, double-
1971 precision, or quad-precision floating-point calling convention, or
1972 none to indicate the soft-float calling convention. Also, "ilp32"
1973 can optionally be followed by "e" to indicate the RVE ABI, which is
1974 always soft-float.
1975 -mrelax
1977 Take advantage of linker relaxations to reduce the number of
1978 instructions required to materialize symbol addresses. (default)
1979 -mno-relax
1981 Don't do linker relaxations.
1982 -march-attr
1984 Generate the default contents for the riscv elf attribute section
1985 if the .attribute directives are not set. This section is used to
1986 record the information that a linker or runtime loader needs to
1987 check compatibility. This information includes ISA string, stack
1988 alignment requirement, unaligned memory accesses, and the major,
1989 minor and revision version of privileged specification.
1990 -mno-arch-attr
1992 Don't generate the default riscv elf attribute section if the
1993 .attribute directives are not set.
1994 -mcsr-check
1996 Enable the CSR checking for the ISA-dependent CRS and the read-only
1997 CSR. The ISA-dependent CSR are only valid when the specific ISA is
1998 set. The read-only CSR can not be written by the CSR instructions.
1999 -mno-csr-check
2001 Don't do CSR cheching.
2002 See the info pages for documentation of the RX-specific options.
2004 The following options are available when as is configured for the s390
2006 processor family.
2007 -m31
2009 -m64
2010 Select the word size, either 31/32 bits or 64 bits.
2011 -mesa
2013 -mzarch
2014 Select the architecture mode, either the Enterprise System
2015 Architecture (esa) or the z/Architecture mode (zarch).
2016 -march=processor
2018 Specify which s390 processor variant is the target, g5 (or arch3),
2019 g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2020 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2021 z14 (or arch12), or z15 (or arch13).
2022 -mregnames
2024 -mno-regnames
2025 Allow or disallow symbolic names for registers.
2026 -mwarn-areg-zero
2028 Warn whenever the operand for a base or index register has been
2029 specified but evaluates to zero.
2030 The following options are available when as is configured for a
2032 TMS320C6000 processor.
2033 -march=arch
2035 Enable (only) instructions from architecture arch. By default, all
2036 instructions are permitted.
2037 The following values of arch are accepted: "c62x", "c64x", "c64x+",
2039 "c67x", "c67x+", "c674x".
2040 -mdsbt
2042 -mno-dsbt
2043 The -mdsbt option causes the assembler to generate the
2044 "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2045 code is using DSBT addressing. The -mno-dsbt option, the default,
2046 causes the tag to have a value of 0, indicating that the code does
2047 not use DSBT addressing. The linker will emit a warning if objects
2048 of different type (DSBT and non-DSBT) are linked together.
2049 -mpid=no
2051 -mpid=near
2052 -mpid=far
2053 The -mpid= option causes the assembler to generate the
2054 "Tag_ABI_PID" attribute with a value indicating the form of data
2055 addressing used by the code. -mpid=no, the default, indicates
2056 position-dependent data addressing, -mpid=near indicates position-
2057 independent addressing with GOT accesses using near DP addressing,
2058 and -mpid=far indicates position-independent addressing with GOT
2059 accesses using far DP addressing. The linker will emit a warning
2060 if objects built with different settings of this option are linked
2061 together.
2062 -mpic
2064 -mno-pic
2065 The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2066 attribute with a value of 1, indicating that the code is using
2067 position-independent code addressing, The "-mno-pic" option, the
2068 default, causes the tag to have a value of 0, indicating position-
2069 dependent code addressing. The linker will emit a warning if
2070 objects of different type (position-dependent and position-
2071 independent) are linked together.
2072 -mbig-endian
2074 -mlittle-endian
2075 Generate code for the specified endianness. The default is little-
2076 endian.
2077 The following options are available when as is configured for a TILE-Gx
2079 processor.
2080 -m32 | -m64
2082 Select the word size, either 32 bits or 64 bits.
2083 -EB | -EL
2085 Select the endianness, either big-endian (-EB) or little-endian
2086 (-EL).
2087 The following option is available when as is configured for a Visium
2089 processor.
2090 -mtune=arch
2092 This option specifies the target architecture. If an attempt is
2093 made to assemble an instruction that will not execute on the target
2094 architecture, the assembler will issue an error message.
2095 The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2097 The following options are available when as is configured for an Xtensa
2099 processor.
2100 --text-section-literals | --no-text-section-literals
2102 Control the treatment of literal pools. The default is
2103 --no-text-section-literals, which places literals in separate
2104 sections in the output file. This allows the literal pool to be
2105 placed in a data RAM/ROM. With --text-section-literals, the
2106 literals are interspersed in the text section in order to keep them
2107 as close as possible to their references. This may be necessary
2108 for large assembly files, where the literals would otherwise be out
2109 of range of the "L32R" instructions in the text section. Literals
2110 are grouped into pools following ".literal_position" directives or
2111 preceding "ENTRY" instructions. These options only affect literals
2112 referenced via PC-relative "L32R" instructions; literals for
2113 absolute mode "L32R" instructions are handled separately.
2114 --auto-litpools | --no-auto-litpools
2116 Control the treatment of literal pools. The default is
2117 --no-auto-litpools, which in the absence of --text-section-literals
2118 places literals in separate sections in the output file. This
2119 allows the literal pool to be placed in a data RAM/ROM. With
2120 --auto-litpools, the literals are interspersed in the text section
2121 in order to keep them as close as possible to their references,
2122 explicit ".literal_position" directives are not required. This may
2123 be necessary for very large functions, where single literal pool at
2124 the beginning of the function may not be reachable by "L32R"
2125 instructions at the end. These options only affect literals
2126 referenced via PC-relative "L32R" instructions; literals for
2127 absolute mode "L32R" instructions are handled separately. When
2128 used together with --text-section-literals, --auto-litpools takes
2129 precedence.
2130 --absolute-literals | --no-absolute-literals
2132 Indicate to the assembler whether "L32R" instructions use absolute
2133 or PC-relative addressing. If the processor includes the absolute
2134 addressing option, the default is to use absolute "L32R"
2135 relocations. Otherwise, only the PC-relative "L32R" relocations
2136 can be used.
2137 --target-align | --no-target-align
2139 Enable or disable automatic alignment to reduce branch penalties at
2140 some expense in code size. This optimization is enabled by
2141 default. Note that the assembler will always align instructions
2142 like "LOOP" that have fixed alignment requirements.
2143 --longcalls | --no-longcalls
2145 Enable or disable transformation of call instructions to allow
2146 calls across a greater range of addresses. This option should be
2147 used when call targets can potentially be out of range. It may
2148 degrade both code size and performance, but the linker can
2149 generally optimize away the unnecessary overhead when a call ends
2150 up within range. The default is --no-longcalls.
2151 --transform | --no-transform
2153 Enable or disable all assembler transformations of Xtensa
2154 instructions, including both relaxation and optimization. The
2155 default is --transform; --no-transform should only be used in the
2156 rare cases when the instructions must be exactly as specified in
2157 the assembly source. Using --no-transform causes out of range
2158 instruction operands to be errors.
2159 --rename-section oldname=newname
2161 Rename the oldname section to newname. This option can be used
2162 multiple times to rename multiple sections.
2163 --trampolines | --no-trampolines
2165 Enable or disable transformation of jump instructions to allow
2166 jumps across a greater range of addresses. This option should be
2167 used when jump targets can potentially be out of range. In the
2168 absence of such jumps this option does not affect code size or
2169 performance. The default is --trampolines.
2170 --abi-windowed | --abi-call0
2172 Choose ABI tag written to the ".xtensa.info" section. ABI tag
2173 indicates ABI of the assembly code. A warning is issued by the
2174 linker on an attempt to link object files with inconsistent ABI
2175 tags. Default ABI is chosen by the Xtensa core configuration.
2176 The following options are available when as is configured for an Z80
2178 processor.
2179 @chapter Z80 Dependent Features
2181 Command-line Options
2183 -march=CPU[-EXT...][+EXT...]
2184 This option specifies the target processor. The assembler will
2185 issue an error message if an attempt is made to assemble an
2186 instruction which will not execute on the target processor. The
2187 following processor names are recognized: "z80", "z180", "ez80",
2188 "gbz80", "z80n", "r800". In addition to the basic instruction set,
2189 the assembler can be told to accept some extention mnemonics. For
2190 example, "-march=z180+sli+infc" extends z180 with SLI instructions
2191 and IN F,(C). The following extentions are currently supported:
2192 "full" (all known instructions), "adl" (ADL CPU mode by default,
2193 eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2194 (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2195 "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2196 "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2197 (C),0). Note that rather than extending a basic instruction set,
2198 the extention mnemonics starting with "-" revoke the respective
2199 functionality: "-march=z80-full+xyhl" first removes all default
2200 extentions and adds support for index registers halves only.
2201 If this option is not specified then "-march=z80+xyhl+infc" is
2203 assumed.
2204 -local-prefix=prefix
2206 Mark all labels with specified prefix as local. But such label can
2207 be marked global explicitly in the code. This option do not change
2208 default local label prefix ".L", it is just adds new one.
2209 -colonless
2211 Accept colonless labels. All symbols at line begin are treated as
2212 labels.
2213 -sdcc
2215 Accept assembler code produced by SDCC.
2216 -fp-s=FORMAT
2218 Single precision floating point numbers format. Default: ieee754
2219 (32 bit).
2220 -fp-d=FORMAT
2222 Double precision floating point numbers format. Default: ieee754
2223 (64 bit).
2224
2226 gcc(1), ld(1), and the Info entries for binutils and ld.
2227
2229 Copyright (c) 1991-2020 Free Software Foundation, Inc.
2230 Permission is granted to copy, distribute and/or modify this document
2232 under the terms of the GNU Free Documentation License, Version 1.3 or
2233 any later version published by the Free Software Foundation; with no
2234 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2235 Texts. A copy of the license is included in the section entitled "GNU
2236 Free Documentation License".
2237binutils-2.35 2020-07-24 AS(1)