1EXT2SPICE(1) General Commands Manual EXT2SPICE(1)
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6 ext2spice - convert hierarchical ext(5) extracted-circuit files to flat
7 spice files
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10 ext2spice [ -B ] [ extcheck-options ] [ -M|m ] [ -y num ] [ -f
11 hspice|spice3|spice2 ] [ -J hier|flat ] [ -j device:sdRclass[/subR‐
12 class]/defaultSubstrate ] root
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16 Ext2spice will convert an extracted circuit from the hierarchical
17 ext(5) representation produced by Magic to a flat spice file which can
18 be accepted by spice2, spice3, hspice and other simulation tools. The
19 root of the tree to be extracted is the file root.ext; it and all the
20 files it references are recursively flattened. The result is a single,
21 flat representation of the circuit that is written to the file
22 root.spice .
23 The following options are recognized:
25 -o outfile
27 Instead of leaving output in the file root.spice, leave it in
28 outfile.
29 -B Don't output transistor or node attributes in the spice file.
31 Usually the attributes of a node or a device are output as
32 special comments **fetattr and **nodeatrr which can be pro‐
33 cessed further to create things such a initial conditions
34 etc.
35 -F Don't output nodes that aren't connected to fets (floating
37 nodes). Normally capacitance from these nodes is output with
38 the comment **FLOATING attached on the same line.
39 -tchar Trim characters from node names when writing the output file.
41 Char should be either "#" or "!". The option may be used
42 twice if both characters are desired. Trimming "#" and "!" is
43 enabled by default when the format is hspice.
44 -M|m Merge parallel fets. -m means conservative merging of fets
46 that have equal widths only (usefull with hspice format mul‐
47 tiplier if delta W effects need to be taken care of). -M
48 means aggressive merging: the fets are merged if they have
49 the same terminals and the same length.
50 -y num Select the precision for outputing capacitors. The default is
52 1 which means that the capacitors will be printed to a preci‐
53 sion of .1 fF.
54 -f hspice|spice2|spice3
56 Select the output format. Spice3 is the the format understood
57 by the latest version of berkeley spice. Node names have the
58 same names as they would in a sim(5) file and no special con‐
59 structs are used. Spice2 is the format understood by the
60 older version of spice (which usually has better conver‐
61 gence). Node names are numbers and a dictionary of number and
62 corresponding node is output in the end. HSPICE is a format
63 understood by meta-software's hspice and other commercial
64 tools. In this format node names cannot be longer than 15
65 characters long (blame the fortran code): so if a hierarchi‐
66 cal node name is longer it is truncated to something like
67 x1234/name where x1234 is an alias of the normal node hierar‐
68 chical prefix and name its hierarchical postfix (a dictionary
69 mapping prefixes to real hierarchical paths is output at the
70 end of the spice file). If the node name is still longer than
71 15 characters long (again blame the fortran code) it is
72 translated to something like z@1234 and the equivalent name
73 is output as a comment. In addition since hspice supports
74 scaling and multipliers so the output dimensions are in lamb‐
75 das and if parallel fets are merged the hspice construct M is
76 used.
77 -J hier|flat
79 Select the source/drain area and perimeter extraction algo‐
80 rithm. If hier is selected then the areas and perimeters are
81 extracted only within each subcell. For each fet in a subcell
82 the area and perimeter of its source and drain within this
83 subcell are output. If two or more fets share a source/drain
84 node then the total area and perimeter will be output in only
85 one of them and the other will have 0. If flat is selected
86 the same rules apply only that the scope of search for area
87 and perimeter is the whole netlist. In general flat (which is
88 the default) will give accurate results (it will take into
89 account shared sources/drains) but hier is provided for back‐
90 wards compatibility with version 6.4.5. On top of this selec‐
91 tion you can individually control how a terminal of a spe‐
92 cific fet will be extracted if you put a source/drain
93 attribute. ext:aph makes the extraction for that specific
94 terminal hierarchical and ext:apf makes the extraction flat
95 (see the magic tutorial about attaching attribute labels).
96 Additionaly to ease extraction of bipolar transistors the
97 gate attribute ext:aps forces the output of the substrate
98 area and perimeter for a specific fet (in flat mode only).
99 -j device:sdRclass[/subRclass]/defaultSubstrate
101 Gives ext2sim information about the source/drain resistance
102 class of the fet type device. Makes device to have sdRclass
103 source drain resistance class, subRclass substrate (well)
104 resistance class and the node named defaultSubstrate as its
105 default substrate. The defaults are nfet:0/Gnd and
106 pfet:1/6/Vdd which correspond to the MOSIS technology file
107 but things might vary in your site. Ask your local cad admin‐
108 istrator.
109 The way the extraction of node area and perimeter works in magic the
112 total area and perimeter of the source/drain junction is summed up on a
113 single node. That is why all the junction areas and perimeters are
114 summed up on a single node (this should not affect simulation results
115 however).
116 Special care must be taken when the substrate of a fet is tied to a
118 node other than the default substrate (eg in a bootstraping charge
119 pump). To get the correct substrate info in these cases the fet(s)
120 with separate wells should be in their own separate subcell with
121 ext:aph attributes attached to their sensitive terminals (also all the
122 transistors which share sensistive terminals with these should be in
123 another subcell with the same attributes).
124 In addition, all of the options of extcheck(1) are accepted.
128 The awk filter spice2sim is provided with the current distribution for
131 debugging purposes.
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135 extcheck(1), ext2spice(1), magic(1), rsim(1), ext(5), sim(5)
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139 Stefanos Sidiropoulos.
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143 The areas and perimeters of fet sources and drains work only with the
144 simple extraction algorith and not with the extresis flow. So you have
145 to model them as linear capacitors (create a special extraction style)
146 if you want to extract parasitic resistances with extresis.
1474th Berkeley Distribution EXT2SPICE(1)