1RTLBROWSE(1)                     File Viewing                     RTLBROWSE(1)
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NAME

6       rtlbrowse  - Allows hierarchical browsing of Verilog HDL sourcecode and
7       library design files.
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SYNTAX

10       rtlbrowse <stemsfilename>
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DESCRIPTION

13       Allows hierarchical browsing of  Verilog  HDL  sourcecode  and  library
14       design files.  Navigation through the hierarchy may be done by clicking
15       open areas of the tree widget and clicking on the individual levels  of
16       hierarchy.   Inside  the sourcecode, selecting the module instantiation
17       name by double clicking or selecting part of  the  name  through  drag-
18       clicking will descend deeper into the RTL hierarchy.  Note that it per‐
19       forms optional source code annotation when called as a helper  applica‐
20       tion  by   gtkwave(1)  and when the primary marker is set.  Source code
21       annotation is not available for all supported dumpfile  types.   It  is
22       directly  available  for  LXT2,  VZT,  FST, and AET2.  For VCD, use the
23       -o,--optimize option of gtkwave(1) in order to optimize  the  VCD  file
24       into  FST.  All other dumpfile types (LXT, GHW) are unsupported at this
25       time.
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EXAMPLES

28       To run this program the standard way type:
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30       rtlbrowse stemsfile
31              The RTL is then brought up in a GTK  tree  viewer.   Stems  must
32              have  been  previously generated with vermin(1).  Note that gtk‐
33              wave(1) will bring up this program as a client  application  for
34              sourcecode  annotation.   It does that by bringing up the viewer
35              with the shared memory ID of a segment of memory in  the  viewer
36              rather than using a stems filename.
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AUTHORS

39       Anthony Bybell <bybell@nc.rr.com>
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SEE ALSO

42       vermin(1) gtkwave(1)
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46Anthony Bybell                       0.1.0                        RTLBROWSE(1)