Verilog::Netlist::Net(3pm)

1Netlist::Net(3)       User Contributed Perl Documentation      Netlist::Net(3)
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NAME

6       Verilog::Netlist::Net - Net for a Verilog Module
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SYNOPSIS

9         use Verilog::Netlist;
10
11         ...
12         my $net = $module->find_net ('signalname');
13         print $net->name;
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DESCRIPTION

16       A Verilog::Netlist::Net object is created by Verilog::Netlist::Module
17       for every signal and input/output declaration, and parameter in the
18       current module.
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ACCESSORS

21       See also Verilog::Netlist::Subclass for additional accessors and
22       methods.
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24       $self->array
25           Any array (vector) declaration for the net.  This is for
26           multidimensional signals, for the width of a signal, use
27           msb/lsb/width.
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29       $self->comment
30           Returns any comments following the definition.  keep_comments=>1
31           must be passed to Verilog::Netlist::new for comments to be
32           retained.
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34       $self->data_type
35           The data type of the net.  This may be a data type keyword
36           ("integer", "logic", etc), user defined type from a type def, a
37           range ("[11:0]", "signed [1:0]" or "" for an implicit wire.
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39       $self->decl_type
40           How the net was declared.  A declaration keyword ("genvar",
41           "localparam", "parameter", "var") or "port" if only as a port - and
42           see the port method, or "net" - and see the net_type method.
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44       $self->module
45           Reference to the Verilog::Netlist::Module or
46           Verilog::Netlist::Interface the net is under.
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48       $self->lsb
49           The least significant bit number of the net.
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51       $self->msb
52           The most significant bit number of the net.
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54       $self->name
55           The name of the net.
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57       $self->net_type
58           The net type, if one applies.  Always a net type keyword
59           ('supply0', 'supply1', 'tri', 'tri0', 'tri1', 'triand', 'trior',
60           'trireg', 'wand', 'wire', 'wor').
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62       $self->type
63           The type function is provided for backward compatibility to
64           Verilog-Perl versions before 3.200. Applications should change to
65           use data_type() and/or decl_type() instead.
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67           The type function returns an agglomeration of data_type, net_type
68           and decl_type that worked ok in Verilog, but does not work with
69           SystemVerilog.  Calls to type() will be converted to calls to
70           data_type, decl_type or net_type in a way that attempts to maintain
71           backward compatibility, however compatibility is not always
72           possible.
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74       $self->value
75           If the net's type is 'parameter', the value from the parameter's
76           declaration.
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78       $self->width
79           The width of the net in bits.
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MEMBER FUNCTIONS

82       See also Verilog::Netlist::Subclass for additional accessors and
83       methods.
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85       $self->lint
86           Checks the net for errors.  Normally called by
87           Verilog::Netlist::lint.
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89       $self->dump
90           Prints debugging information for this net.
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92       $self->dump_drivers
93           Prints debugging information for this net, and all pins driving the
94           net.
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DISTRIBUTION

97       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
98       software tool suite.  The latest version is available from CPAN and
99       from http://www.veripool.org/verilog-perl
100       <http://www.veripool.org/verilog-perl>.
101
102       Copyright 2000-2009 by Wilson Snyder.  This package is free software;
103       you can redistribute it and/or modify it under the terms of either the
104       GNU Lesser General Public License Version 3 or the Perl Artistic
105       License Version 2.0.
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AUTHORS

108       Wilson Snyder <wsnyder@wsnyder.org>
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