Verilog::Netlist::Net(3pm)

1Netlist::Net(3)       User Contributed Perl Documentation      Netlist::Net(3)
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NAME

6       Verilog::Netlist::Net - Net for a Verilog Module
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SYNOPSIS

9         use Verilog::Netlist;
10
11         ...
12         my $net = $module->find_net('signalname');
13         print $net->name;
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DESCRIPTION

16       A Verilog::Netlist::Net object is created by Verilog::Netlist::Module
17       for every signal and input/output declaration, and parameter in the
18       current module.
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ACCESSORS

21       See also Verilog::Netlist::Subclass for additional accessors and
22       methods.
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24       $self->array
25           Any array (vector) declaration for the net.  This is for Verilog
26           2001 multidimensional signals; for the width of a signal, use
27           msb/lsb/width. For newer applications use data_type() as it
28           supports SystemVerilog types.
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30       $self->comment
31           Returns any comments following the definition.  keep_comments=>1
32           must be passed to Verilog::Netlist::new for comments to be
33           retained.
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35       $self->data_type
36           The data type of the net.  This may be a data type keyword
37           ("integer", "logic", etc), user defined type from a type def, a
38           range ("[11:0]", "signed [1:0]" or "" for an implicit wire.
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40       $self->decl_type
41           How the net was declared.  A declaration keyword ("genvar",
42           "localparam", "parameter", "var") or "port" if only as a port - and
43           see the port method, or "net" - and see the net_type method.
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45       $self->module
46           Reference to the Verilog::Netlist::Module or
47           Verilog::Netlist::Interface the net is under.
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49       $self->lsb
50           The least significant bit number of the net.
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52       $self->msb
53           The most significant bit number of the net.
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55       $self->name
56           The name of the net.
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58       $self->net_type
59           The net type, if one applies.  Always a net type keyword
60           ('supply0', 'supply1', 'tri', 'tri0', 'tri1', 'triand', 'trior',
61           'trireg', 'wand', 'wire', 'wor').
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63       $self->type
64           The type function is provided for backward compatibility to
65           Verilog-Perl versions before 3.200. Applications should change to
66           use data_type() and/or decl_type() instead.
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68           The type function returns an agglomeration of data_type, net_type
69           and decl_type that worked ok in Verilog, but does not work with
70           SystemVerilog.  Calls to type() will be converted to calls to
71           data_type, decl_type or net_type in a way that attempts to maintain
72           backward compatibility, however compatibility is not always
73           possible.
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75       $self->value
76           If the net's type is 'parameter', the value from the parameter's
77           declaration.
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79       $self->width
80           The width of the net in bits.
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MEMBER FUNCTIONS

83       See also Verilog::Netlist::Subclass for additional accessors and
84       methods.
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86       $self->lint
87           Checks the net for errors.  Normally called by
88           Verilog::Netlist::lint.
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90       $self->dump
91           Prints debugging information for this net.
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93       $self->dump_drivers
94           Prints debugging information for this net, and all pins driving the
95           net.
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DISTRIBUTION

98       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
99       EDA software tool suite.  The latest version is available from CPAN and
100       from <https://www.veripool.org/verilog-perl>.
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102       Copyright 2000-2022 by Wilson Snyder.  This package is free software;
103       you can redistribute it and/or modify it under the terms of either the
104       GNU Lesser General Public License Version 3 or the Perl Artistic
105       License Version 2.0.
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AUTHORS

108       Wilson Snyder <wsnyder@wsnyder.org>
109