1OPENSSL_ia32cap(3) OpenSSL OPENSSL_ia32cap(3)
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6 OPENSSL_ia32cap - finding the IA-32 processor capabilities
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9 unsigned long *OPENSSL_ia32cap_loc(void);
10 #define OPENSSL_ia32cap (*(OPENSSL_ia32cap_loc()))
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13 Value returned by OPENSSL_ia32cap_loc() is address of a variable
14 containing IA-32 processor capabilities bit vector as it appears in EDX
15 register after executing CPUID instruction with EAX=1 input value (see
16 Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
17 platforms only. The variable is normally set up automatically upon
18 toolkit initialization, but can be manipulated afterwards to modify
19 crypto library behaviour. For the moment of this writing six bits are
20 significant, namely:
21 1. bit #28 denoting Hyperthreading, which is used to distiguish
23 cores with shared cache; 2. bit #26 denoting SSE2 support; 3. bit
24 #25 denoting SSE support; 4. bit #23 denoting MMX support; 5. bit #20,
25 reserved by Intel, is used to choose between RC4 code
26 pathes; 6. bit #4 denoting presence of Time-Stamp Counter.
27 For example, clearing bit #26 at run-time disables high-performance
29 SSE2 code present in the crypto library. You might have to do this if
30 target OpenSSL application is executed on SSE2 capable CPU, but under
31 control of OS which does not support SSE2 extentions. Even though you
32 can manipulate the value programmatically, you most likely will find it
33 more appropriate to set up an environment variable with the same name
34 prior starting target application, e.g. on Intel P4 processor 'env
35 OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
36 without modifying the application source code. Alternatively you can
37 reconfigure the toolkit with no-sse2 option and recompile.
381.0.0e 2007-04-01 OPENSSL_ia32cap(3)