1OPENSSL_IA32CAP(3) OpenSSL OPENSSL_IA32CAP(3)
2
6 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
7
9 env OPENSSL_ia32cap=... <application>
10
12 OpenSSL supports a range of x86[_64] instruction set extensions. These
13 extensions are denoted by individual bits in capability vector returned
14 by processor in EDX:ECX register pair after executing CPUID instruction
15 with EAX=1 input value (see Intel Application Note #241618). This
16 vector is copied to memory upon toolkit initialization and used to
17 choose between different code paths to provide optimal performance
18 across wide range of processors. For the moment of this writing
19 following bits are significant:
20 bit #4 denoting presence of Time-Stamp Counter.
22 bit #19 denoting availability of CLFLUSH instruction;
23 bit #20, reserved by Intel, is used to choose among RC4 code paths;
24 bit #23 denoting MMX support;
25 bit #24, FXSR bit, denoting availability of XMM registers;
26 bit #25 denoting SSE support;
27 bit #26 denoting SSE2 support;
28 bit #28 denoting Hyperthreading, which is used to distinguish cores
29 with shared cache;
30 bit #30, reserved by Intel, denotes specifically Intel CPUs;
31 bit #33 denoting availability of PCLMULQDQ instruction;
32 bit #41 denoting SSSE3, Supplemental SSE3, support;
33 bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
34 bit #54 denoting availability of MOVBE instruction;
35 bit #57 denoting AES-NI instruction set extension;
36 bit #58, XSAVE bit, lack of which in combination with MOVBE is used to
37 identify Atom Silvermont core;
38 bit #59, OSXSAVE bit, denoting availability of YMM registers;
39 bit #60 denoting AVX extension;
40 bit #62 denoting availability of RDRAND instruction;
41 For example, in 32-bit application context clearing bit #26 at run-time
43 disables high-performance SSE2 code present in the crypto library,
44 while clearing bit #24 disables SSE2 code operating on 128-bit XMM
45 register bank. You might have to do the latter if target OpenSSL
46 application is executed on SSE2 capable CPU, but under control of OS
47 that does not enable XMM registers. Historically address of the
48 capability vector copy was exposed to application through
49 OPENSSL_ia32cap_loc(), but not anymore. Now the only way to affect the
50 capability detection is to set OPENSSL_ia32cap environment variable
51 prior target application start. To give a specific example, on Intel P4
52 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet
53 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' would achieve the desired
54 effect. Alternatively you can reconfigure the toolkit with no-sse2
55 option and recompile.
56 Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
58 variable" terms. The truth is that it's not copied from CPUID output
59 verbatim, but is adjusted to reflect whether or not the data cache is
60 actually shared between logical cores. This in turn affects the
61 decision on whether or not expensive countermeasures against cache-
62 timing attacks are applied, most notably in AES assembler module.
63 The capability vector is further extended with EBX value returned by
65 CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
66 bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
68 bit #64+5 denoting availability of AVX2 instructions;
69 bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and
70 RORX;
71 bit #64+16 denoting availability of AVX512F extension;
72 bit #64+18 denoting availability of RDSEED instruction;
73 bit #64+19 denoting availability of ADCX and ADOX instructions;
74 bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, aka
75 AVX512IFMA extension;
76 bit #64+29 denoting availability of SHA extension;
77 bit #64+30 denoting availability of AVX512BW extension;
78 bit #64+31 denoting availability of AVX512VL extension;
79 bit #64+41 denoting availability of VAES extension;
80 bit #64+42 denoting availability of VPCLMULQDQ extension;
81 To control this extended capability word use ':' as delimiter when
83 setting up OPENSSL_ia32cap environment variable. For example assigning
84 ':~0x20' would disable AVX2 code paths, and ':0' - all post-AVX
85 extensions.
86 It should be noted that whether or not some of the most "fancy"
88 extension code paths are actually assembled depends on current
89 assembler version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA
90 extension code paths are always assembled. Apart from that, minimum
91 assembler version requirements are summarized in below table:
92 Extension | GNU as | nasm | llvm
94 ------------+--------+--------+--------
95 AVX | 2.19 | 2.09 | 3.0
96 AVX2 | 2.22 | 2.10 | 3.1
97 ADCX/ADOX | 2.23 | 2.10 | 3.3
98 AVX512 | 2.25 | 2.11.8 | see NOTES
99 AVX512IFMA | 2.26 | 2.11.8 | see NOTES
100 VAES | 2.30 | 2.13.3 |
101
103 Even though AVX512 support was implemented in llvm 3.6, compilation of
104 assembly modules apparently requires explicit -march flag. But then
105 compiler generates processor-specific code, which in turn contradicts
106 the mere idea of run-time switch execution facilitated by the variable
107 in question. Till the limitation is lifted, it's possible to work
108 around the problem by making build procedure use following script:
109 #!/bin/sh
111 exec clang -no-integrated-as "$@"
112 instead of real clang. In which case it doesn't matter which clang
114 version is used, as it is GNU assembler version that will be checked.
115
117 Not available.
118
120 Copyright 2004-2020 The OpenSSL Project Authors. All Rights Reserved.
121 Licensed under the OpenSSL license (the "License"). You may not use
123 this file except in compliance with the License. You can obtain a copy
124 in the file LICENSE in the source distribution or at
125 <https://www.openssl.org/source/license.html>.
1261.1.1q 2023-07-20 OPENSSL_IA32CAP(3)