1srec_vmem(5)                  File Formats Manual                 srec_vmem(5)
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NAME

6       srec_vmem - vmem file format
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DESCRIPTION

9       This  format is the Verilog VMEM format.  This is a hex format suitable
10       for loading into Verilog simulations using the $readmemh call.
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12       The text file to be read shall contain only the following:
13       White space (spaces, new lines, tabs, and form‐feeds)
14       Comments (both types of C++ comment are allowed)
15       Hexadecimal numbers
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17       White space and/or comments shall be used to separate the numbers.
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19       In the following discussion, the term "address" refers to an index into
20       the array that models the memory.
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22       As  the  file is read, each number encountered is assigned to a succes‐
23       sive word element of the memory.   Addressing  is  controlled  both  by
24       specifying  start and/or finish addresses in the system task invocation
25       and by specifying addresses in the data file.
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27       When addresses appear in the data file, the format is an "at" character
28       (@) followed by a hexadecimal number as follows:
29              @hh...h
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31       Both  uppercase  and  lowercase  digits  are allowed in the number.  No
32       white space is allowed between the @ and the number.  As  many  address
33       specifications  as  needed  within the data file can be used.  When the
34       system task encounters an address specification,  it  loads  subsequent
35       data starting at that memory address.
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37   Commentary
38       There is no checksum in this format, which can generate false positives
39       when guessing file formats on input.
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41       There is no indication of the word size in the file, since it is depen‐
42       dent  on  the  word  type  of the Verilog memory it is being read into.
43       SRecord will guess the word size based on the number of digits it  sees
44       in the numbers, but this is only a guess.
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46       SRecord  will also assume that the numbers are to be loaded big‐endian;
47       that is, most significant  byte  (first  byte  seen)  into  the  lowest
48       address covered by the word.
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50       You can use the -byte‐swap filter to change the byte order; it takes an
51       optional width of bytes to swap within.
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53   Size Multiplier
54       In general, binary data will expand in sized by approximately 2.9 times
55       (32‐bit), 3.1 times (16‐bit) or 3.6 times (8‐bit) when represented with
56       this format.
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EXAMPLE

59       Here is an example Verilog VMEM file.  It  contains  the  data  “Hello,
60       World[rq] to be loaded at address 0x1000.
61              @00000400 48656C6C 6F2C2057 6F726C64 0AFFFFFF
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REFERENCE

64       IEEE  P1364‐2005/D2, Standard for Verilog Hardware Description Language
65       (Draft), section 17.2.8 "Loading memory data from a file", p. 295.
66       Copyright © 2003 IEEE
67       http://www.boyd.com/1364/
68       http://www.boyd.com/1364/1364‐2005‐d2.pdf.gz
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71       srec_cat version 1.55
72       Copyright (C) 1998, 1999, 2000, 2001, 2002,  2003,  2004,  2005,  2006,
73       2007, 2008, 2009, 2010 Peter Miller
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75       The srec_cat program comes with ABSOLUTELY NO WARRANTY; for details use
76       the 'srec_cat -VERSion License' command.  This is free software and you
77       are  welcome  to  redistribute it under certain conditions; for details
78       use the 'srec_cat -VERSion License' command.
79

AUTHOR

81       Peter Miller   E‐Mail:   pmiller@opensource.org.au
82       /\/\*             WWW:   http://miller.emu.id.au/pmiller/
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86Reference Manual                    SRecord                       srec_vmem(5)
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