1VPASSERT(1) User Contributed Perl Documentation VPASSERT(1)
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6 vpassert - Preprocess Verilog code assertions
7
9 vpassert [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [
10 files... ]
11
13 Vpassert will read the specified Verilog files and preprocess special
14 PLI assertions. The files are written to the directory named .vpassert
15 unless another name is given with -o. If a directory is passed, all
16 files in that directory will be preprocessed.
17
19 Standard VCS and GCC-like parameters are used to specify the files to
20 be preprocessed:
21 +libext+I<ext>+I<ext>... Specify extensions to be processed
23 -f I<file> Parse parameters in file
24 -v I<file> Parse the library file (I<file>)
25 -y I<dir> Parse all files in the directory (I<dir>)
26 -II<dir> Parse all files in the directory (I<dir>)
27 +incdir+I<dir> Parse all files in the directory (I<dir>)
28 To prevent recursion and allow reuse of the input.vc being passed to
30 the simulator, if the output directory is requested to be preprocessed,
31 that directory is simply ignored.
32 --allfiles
34 Preprocess and write out files that do not have any macros that
35 need expanding. By default, files that do not need processing are
36 not written out.
37 This option may speed up simulator compile times; the file will
39 always be found in the preprocessed directory, saving the compiler
40 from having to search a large number of -v directories to find it.
41 --axiom
43 Special Axiom ATHDL enables/disables added around unreachable code.
44 --call-error <function>
46 When $uerror (or $uassert etc.) wants to display a message, call
47 the specified function instead of $display and $stop.
48 --call-info <function>
50 When $uinfo wants to display a message, call the specified function
51 instead of $display.
52 --call-warn <function>
54 When $uwarn (or $uwarn_clk etc.) wants to display a message, call
55 the specified function instead of $display and $stop.
56 --date
58 Check file dates and sizes versus the last run of vpassert and
59 don't process if the given source file has not changed.
60 --exclude
62 Exclude processing any files which begin with the specified prefix.
63 --help
65 Displays this message and program version and exits.
66 --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009>
68 Set the language standard for the files. This determines which
69 tokens are signals versus keywords, such as the ever-common "do"
70 (data-out signal, versus a do-while loop keyword).
71 --minimum
73 Include `__message_minimum in the $uinfo test, so that by defining
74 __message_minimum=1 some uinfos may be optimized away at compile
75 time.
76 --noline
78 Do not emit `line directives. If not specified they will be used
79 under --language 1364-2001 and later.
80 --nopli
82 Delete all 'simple' PLI calls. PLI function calls inside
83 parenthesis will not be changed, and thus may still need to be
84 manually ifdef'ed out. Useful for reducing the amount of `ifdef's
85 required to feed non-PLI competent synthesis programs.
86 --nostop
88 By default, $error and $warn insert a $stop statement. With
89 --nostop, this is replaced by incrementing a variable, which may
90 then be used to conditionally halt simulation.
91 --o file
93 Use the given filename for output instead of the input name
94 .vpassert. If the name ends in a / it is used as a output
95 directory with the default name.
96 --quiet
98 Suppress messages about what files are being preprocessed.
99 --realintent
101 Special RealIntent enable/disables added around unreachable code.
102 --synthcov
104 When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the
105 `else or `endif. This does NOT follow child defines, for example:
106 `ifdef SYNTHSIS
108 `define MYSYNTH
109 `endif
110 `ifdef MYSYNTH // This will not be coveraged-off
111 --timeformat-units units
113 If specified, include Verilog $timeformat calls before all
114 messages. Use the provided argument as the units. Units is in
115 powers of 10, so -9 indicates to use nanoseconds.
116 --timeformat-precision prec
118 When using --timeformat-units, use this as the precision value, the
119 number of digits after the decimal point. Defaults to zero.
120 --vericov
122 Special Vericov enable/disables added around unreachable code.
123 --verilator
125 Special Verilator translations enabled.
126 --version
128 Displays program version and exits.
129 --vcs
131 Special Synopsys VCS enables/disables added around unreachable
132 code.
133
135 These Verilog pseudo-pli calls are expanded:
136 /*vp_coverage_off*/
138 Disable coverage for all tools starting at this point. Does not
139 need to be on a unique line.
140 /*vp_coverage_on*/
142 Re-enable coverage after a vp_coverage_off. Does not need to be on
143 a unique line.
144 $uassert (case, "message", [vars...] )
146 Report a $uerror if the given case is FALSE. (Like assert() in C.)
147 $uassert_amone (sig, [sig...], "message", [vars...] )
149 Report a $uerror if more than one signal is asserted, or any are X.
150 (None asserted is ok.) The error message will include a binary
151 display of the signal values.
152 $uassert_info (case, "message", [vars...] )
154 Report a $uinfo if the given case is FALSE. (Like assert() in C.)
155 $uassert_onehot (sig, [sig...], "message", [vars...] )
157 Report a $uerror if other than one signal is asserted, or any are
158 X. The error message will include a binary display of the signal
159 values.
160 $uassert_req_ack (req_sig, ack_sig, [data_sig,...] )
162 Check for a single cycle request pulse, followed by a single cycle
163 acknowledgment pulse. Do not allow any of the data signals to
164 change between the request and acknowledgement.
165 $ucheck_ilevel (level )
167 Return true if the __message level is greater or equal to the given
168 level, and that global messages are turned on.
169 $ucover_clk (clock, label)
171 Similar to $uerror_clk, add a SystemVerilog assertion at the next
172 specified clock's edge, with the label specified. This allows cover
173 properties to be specified "inline" with normal RTL code.
174 $ucover_foreach_clk (clock, label, "msb:lsb", (... $ui ...))
176 Similar to $ucover_clk, however cover a range where $ui in the
177 expression is replaced with the range index.
178 Range is "msb:lsb" to indicate from msb downto lsb inclusive,
180 and/or a comma separated list of values.
181 Similar to:
183 for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin
185 if (expression with $ui)
186 $ucover_clk(clock, label ## "_" ## bit)
187 end
188 However there's no way to form a label from a for loop (as
190 psudocoded with ## above), thus this macro.
191 $ui Loop index used inside $ucover_foreach_clk.
193 $uinfo (level, "message", [vars...] )
195 Report a informational message in standard form. End test if
196 warning limit exceeded.
197 $uerror ("message", [vars...] )
199 Report a error message in standard form. End test if error limit
200 exceeded.
201 $uerror_clk (clock, "message", [vars...] )
203 Report a error message in standard form at the next clock edge. If
204 you place a $uerror etc in a combo logic block (always @*), event
205 based simulators may misfire the assertion due to glitches.
206 $uerror_clk fixes this by instead creating a temporary signal and
207 then moving the assert itself to a new clocked block at the
208 specified edge. Note any variables printed will be the values at
209 the time of the next clock edge, which may differ from the value
210 where the $uerror_clk is assigned.
211 $uwarn ("message", [vars...] )
213 Report a warning message in standard form.
214 $uwarn_clk (clock "message", [vars...] )
216 Report a warning message in standard form at the next clock edge.
217 See $uerror_clk.
218
220 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
221 software tool suite. The latest version is available from CPAN and
222 from http://www.veripool.org/verilog-perl
223 <http://www.veripool.org/verilog-perl>.
224 Copyright 2000-2010 by Wilson Snyder. This package is free software;
226 you can redistribute it and/or modify it under the terms of either the
227 GNU Lesser General Public License Version 3 or the Perl Artistic
228 License Version 2.0.
229
231 Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi
232 <duane.galbi@conexant.com>
233
235 Verilog-Perl, Verilog::Parser, Verilog::Pli
236perl v5.12.2 2010-10-25 VPASSERT(1)