perl-Verilog-Perl/Verilog::Language(3pm)

1Language(3)           User Contributed Perl Documentation          Language(3)
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NAME

6       Verilog::Language - Verilog language utilities
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SYNOPSIS

9         use Verilog::Language;
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11         $result = Verilog::Language::is_keyword ("wire");  # true
12         $result = Verilog::Language::is_compdirect ("`notundef");  # false
13         $result = Verilog::Language::number_value ("4'b111");  # 8
14         $result = Verilog::Language::number_bits  ("32'h1b");  # 32
15         $result = Verilog::Language::number_signed ("1'sh1");  # 1
16         @vec    = Verilog::Language::split_bus ("[31,5:4]"); # 31, 5, 4
17         @vec    = Verilog::Language::split_bus_nocomma ("[31:29]"); # 31, 30, 29
18         $result = Verilog::Language::strip_comments ("a/*b*/c");  # ac
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DESCRIPTION

21       Verilog::Language provides general utilities for using the Verilog
22       Language, such as parsing numbers or determining what keywords exist.
23       General functions will be added as needed.
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FUNCTIONS

26       Verilog::Language::is_keyword ($symbol_string)
27           Return true if the given symbol string is a Verilog reserved
28           keyword.  Value indicates the language standard as per the
29           `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005',
30           '1800-2005' or '1800-2009'.
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32       Verilog::Language::is_compdirect ($symbol_string)
33           Return true if the given symbol string is a Verilog compiler
34           directive.
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36       Verilog::Language::is_gateprim ($symbol_string)
37           Return true if the given symbol is a built in gate primitive; for
38           example "buf", "xor", etc.
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40       Verilog::Language::language_keywords ($year)
41           Returns a hash for keywords for given language standard year, where
42           the value of the hash is the standard in which it was defined.
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44       Verilog::Language::language_standard ($year)
45           Sets the language standard to indicate what are keywords.  If
46           undef, all standards apply.  The year is indicates the language
47           standard as per the `begin_keywords macro, '1364-1995',
48           '1364-2001', '1364-2005', '1800-2005' or '1800-2009'.
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50       Verilog::Language::language_maximum
51           Returns the greatest language currently standardized, presently
52           '1800-2009'.
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54       Verilog::Language::number_bigint ($number_string)
55           Return the numeric value of a Verilog value stored as a
56           Math::BigInt, or undef if incorrectly formed.  You must 'use
57           Math::BigInt' yourself before calling this function.  Note bigints
58           do not have an exact size, so NOT of a Math::BigInt may return a
59           different value than verilog.  See also number_value and
60           number_bitvector.
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62       Verilog::Language::number_bits ($number_string)
63           Return the number of bits in a value string, or undef if
64           incorrectly formed, _or_ not specified.
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66       Verilog::Language::number_bitvector ($number_string)
67           Return the numeric value of a Verilog value stored as a
68           Bit::Vector, or undef if incorrectly formed.  You must 'use
69           Bit::Vector' yourself before calling this function.  The size of
70           the Vector will be that returned by number_bits.
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72       Verilog::Language::number_signed ($number_string)
73           Return true if the Verilog value is signed, else undef.
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75       Verilog::Language::number_value ($number_string)
76           Return the numeric value of a Verilog value, or undef if
77           incorrectly formed.  It ignores any signed Verilog attributes, but
78           is is returned as a perl signed integer, so it may fail for over 31
79           bit values.  See also number_bigint and number_bitvector.
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81       Verilog::Language::split_bus ($bus)
82           Return a list of expanded arrays.  When passed a string like
83           "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]",
84           ...).  It correctly handles connectivity expansion also, so that
85           "x[1:0] = y[3:0]" will get intuitive results.
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87       Verilog::Language::split_bus_nocomma ($bus)
88           As with split_bus, but faster.  Only supports simple decimal colon
89           separated array specifications, such as "foo[3:0]".
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91       Verilog::Language::strip_comments ($text)
92           Return text with any // or /**/ comments stripped, correctly
93           handing quoted strings.  Newlines will be preserved in this
94           process.
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DISTRIBUTION

97       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
98       software tool suite.  The latest version is available from CPAN and
99       from http://www.veripool.org/verilog-perl
100       <http://www.veripool.org/verilog-perl>.
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102       Copyright 2000-2010 by Wilson Snyder.  This package is free software;
103       you can redistribute it and/or modify it under the terms of either the
104       GNU Lesser General Public License Version 3 or the Perl Artistic
105       License Version 2.0.
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AUTHORS

108       Wilson Snyder <wsnyder@wsnyder.org>
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NAME

SYNOPSIS

DESCRIPTION

FUNCTIONS

DISTRIBUTION

AUTHORS

SEE ALSO