Verilog::Language(3pm)

1Language(3)           User Contributed Perl Documentation          Language(3)
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NAME

6       Verilog::Language - Verilog language utilities
7

SYNOPSIS

9         use Verilog::Language;
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11         $result = Verilog::Language::is_keyword("wire");  # true
12         $result = Verilog::Language::is_compdirect("`notundef");  # false
13         $result = Verilog::Language::number_value("4'b111");  # 8
14         $result = Verilog::Language::number_bits("32'h1b");  # 32
15         $result = Verilog::Language::number_signed("1'sh1");  # 1
16         @vec    = Verilog::Language::split_bus("[31,5:4]");  # 31, 5, 4
17         @vec    = Verilog::Language::split_bus_nocomma("[31:29]");  # 31, 30, 29
18         $result = Verilog::Language::strip_comments("a/*b*/c");  # ac
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DESCRIPTION

21       Verilog::Language provides general utilities for using the Verilog
22       Language, such as parsing numbers or determining what keywords exist.
23       General functions will be added as needed.
24

FUNCTIONS

26       Verilog::Language::is_keyword($symbol_string)
27           Return true if the given symbol string is a Verilog reserved
28           keyword.  Value indicates the language standard as per the
29           `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005',
30           '1800-2005', '1800-2009', '1800-2012', '1800-2017' or 'VAMS'.
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32       Verilog::Language::is_compdirect($symbol_string)
33           Return true if the given symbol string is a Verilog compiler
34           directive.
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36       Verilog::Language::is_gateprim($symbol_string)
37           Return true if the given symbol is a built in gate primitive; for
38           example "buf", "xor", etc.
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40       Verilog::Language::language_keywords($year)
41           Returns a hash for keywords for given language standard year, where
42           the value of the hash is the standard in which it was defined.
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44       Verilog::Language::language_standard($year)
45           Sets the language standard to indicate what are keywords.  If
46           undef, all standards apply.  The year is indicates the language
47           standard as per the `begin_keywords macro, '1364-1995',
48           '1364-2001', '1364-2005', '1800-2005' '1800-2009', '1800-2012' or
49           '1800-2017'.
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51       Verilog::Language::language_maximum
52           Returns the greatest language currently standardized, presently
53           '1800-2017'.
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55       Verilog::Language::number_bigint($number_string)
56           Return the numeric value of a Verilog value stored as a
57           Math::BigInt, or undef if incorrectly formed.  You must 'use
58           Math::BigInt' yourself before calling this function.  Note bigints
59           do not have an exact size, so NOT of a Math::BigInt may return a
60           different value than verilog.  See also number_value and
61           number_bitvector.
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63       Verilog::Language::number_bits($number_string)
64           Return the number of bits in a value string, or undef if
65           incorrectly formed, _or_ not specified.
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67       Verilog::Language::number_bitvector($number_string)
68           Return the numeric value of a Verilog value stored as a
69           Bit::Vector, or undef if incorrectly formed.  You must 'use
70           Bit::Vector' yourself before calling this function.  The size of
71           the Vector will be that returned by number_bits.
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73       Verilog::Language::number_signed($number_string)
74           Return true if the Verilog value is signed, else undef.
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76       Verilog::Language::number_value($number_string)
77           Return the numeric value of a Verilog value, or undef if
78           incorrectly formed.  It ignores any signed Verilog attributes, but
79           is is returned as a perl signed integer, so it may fail for over 31
80           bit values.  See also number_bigint and number_bitvector.
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82       Verilog::Language::split_bus($bus)
83           Return a list of expanded arrays.  When passed a string like
84           "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]",
85           ...).  It correctly handles connectivity expansion also, so that
86           "x[1:0] = y[3:0]" will get intuitive results.
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88       Verilog::Language::split_bus_nocomma($bus)
89           As with split_bus, but faster.  Only supports simple decimal colon
90           separated array specifications, such as "foo[3:0]".
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92       Verilog::Language::strip_comments($text)
93           Return text with any // or /**/ comments stripped, correctly
94           handing quoted strings.  Newlines will be preserved in this
95           process.
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DISTRIBUTION

98       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
99       EDA software tool suite.  The latest version is available from CPAN and
100       from <https://www.veripool.org/verilog-perl>.
101
102       Copyright 2000-2022 by Wilson Snyder.  This package is free software;
103       you can redistribute it and/or modify it under the terms of either the
104       GNU Lesser General Public License Version 3 or the Perl Artistic
105       License Version 2.0.
106

AUTHORS

108       Wilson Snyder <wsnyder@wsnyder.org>
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NAME

SYNOPSIS

DESCRIPTION

FUNCTIONS

DISTRIBUTION

AUTHORS

SEE ALSO