1Language(3) User Contributed Perl Documentation Language(3)
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6 Verilog::Language - Verilog language utilities
7
9 use Verilog::Language;
10 $result = Verilog::Language::is_keyword ("wire"); # true
12 $result = Verilog::Language::is_compdirect ("`notundef"); # false
13 $result = Verilog::Language::number_value ("4'b111"); # 8
14 $result = Verilog::Language::number_bits ("32'h1b"); # 32
15 $result = Verilog::Language::number_signed ("1'sh1"); # 1
16 @vec = Verilog::Language::split_bus ("[31,5:4]"); # 31, 5, 4
17 @vec = Verilog::Language::split_bus_nocomma ("[31:29]"); # 31, 30, 29
18 $result = Verilog::Language::strip_comments ("a/*b*/c"); # ac
19
21 Verilog::Language provides general utilities for using the Verilog
22 Language, such as parsing numbers or determining what keywords exist.
23 General functions will be added as needed.
24
26 If you are starting a new application which needs to parse the Verilog
27 language you have several tools available to you. Which you pick
28 depends on how low level and complete the information you need is.
29 Verilog::Preproc
31 Verilog::Preproc is useful when you need only text out, or a list
32 of defines, etc. It can preprocess a file, or be used to provide
33 the Verilog macro language on top of synthesis scripts. It
34 understands the full SystemVerilog 2005 preprocessor syntax.
35 Verilog::Parser
37 Verilog::Parser is useful when you need to tokenize or write source
38 filters (where you need everything including whitespace). It can
39 take raw files, or preprocessed input. It understands all
40 SystemVerilog 2005 keywords.
41 Verilog::SigParser
43 Verilog::SigParser is useful when you need a list of modules,
44 signals, ports, functions, etc. It requires a preprocessed file,
45 and can parse most Verilog 2005 files, but only provides callbacks
46 on certain interesting things.
47 Verilog::Netlist
49 Verilog::Netlist is useful for when you need the hierarchy, and a
50 list of signals per module, pins per cell, etc. It builds upon the
51 output of Verilog::SigParser, so requires preprocessed files.
52 This is probably the most popular choice.
54 VPI Using the VPI is the best way to access the behavior of the design.
56 It is not part of this package as it requires a compliant simulator
57 and C++ code to call the VPI, and understands as much of the
58 language as the simulator supports. This allows writing lint
59 checks and full knowledge of all parts of the code, but generally
60 requires the most work (short of writing a parser from scratch.)
61
63 Verilog::Language::is_keyword ($symbol_string)
64 Return true if the given symbol string is a Verilog reserved
65 keyword. Value indicates the language standard as per the
66 `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', or
67 '1800-2005'.
68 Verilog::Language::is_compdirect ($symbol_string)
70 Return true if the given symbol string is a Verilog compiler
71 directive.
72 Verilog::Language::is_gateprim ($symbol_string)
74 Return true if the given symbol is a built in gate primitive; for
75 example "buf", "xor", etc.
76 Verilog::Language::language_standard ($year)
78 Sets the language standard to indicate what are keywords. If
79 undef, all standards apply. The year is indicates the language
80 standard as per the `begin_keywords macro, '1364-1995',
81 '1364-2001', '1364-2005', or '1800-2005'.
82 Verilog::Language::number_bigint ($number_string)
84 Return the numeric value of a Verilog value stored as a
85 Math::BigInt, or undef if incorrectly formed. You must 'use
86 Math::BigInt' yourself before calling this function. Note bigints
87 do not have an exact size, so NOT of a Math::BigInt may return a
88 different value than verilog. See also number_value and
89 number_bitvector.
90 Verilog::Language::number_bits ($number_string)
92 Return the number of bits in a value string, or undef if
93 incorrectly formed, _or_ not specified.
94 Verilog::Language::number_bitvector ($number_string)
96 Return the numeric value of a Verilog value stored as a
97 Bit::Vector, or undef if incorrectly formed. You must 'use
98 Bit::Vector' yourself before calling this function. The size of
99 the Vector will be that returned by number_bits.
100 Verilog::Language::number_signed ($number_string)
102 Return true if the Verilog value is signed, else undef.
103 Verilog::Language::number_value ($number_string)
105 Return the numeric value of a Verilog value, or undef if
106 incorrectly formed. It ignores any signed Verilog attributes, but
107 is is returned as a perl signed integer, so it may fail for over 31
108 bit values. See also number_bigint and number_bitvector.
109 Verilog::Language::split_bus ($bus)
111 Return a list of expanded arrays. When passed a string like
112 "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]",
113 ...). It correctly handles connectivity expansion also, so that
114 "x[1:0] = y[3:0]" will get intuitive results.
115 Verilog::Language::split_bus_nocomma ($bus)
117 As with split_bus, but faster. Only supports simple decimal colon
118 separated array specifications, such as "foo[3:0]".
119 Verilog::Language::strip_comments ($text)
121 Return text with any // or /**/ comments stripped, correctly
122 handing quoted strings. Newlines will be preserved in this
123 process.
124
126 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
127 software tool suite. The latest version is available from CPAN and
128 from http://www.veripool.org/verilog-perl
129 <http://www.veripool.org/verilog-perl>.
130 Copyright 2000-2009 by Wilson Snyder. This package is free software;
132 you can redistribute it and/or modify it under the terms of either the
133 GNU Lesser General Public License Version 3 or the Perl Artistic
134 License Version 2.0.
135
137 Wilson Snyder <wsnyder@wsnyder.org>
138
140 Verilog-Perl, Verilog::EditFiles Verilog::Parser, Verilog::ParseSig,
141 Verilog::Getopt
142 And the http://www.veripool.org/verilog-mode
144 <http://www.veripool.org/verilog-mode>Verilog-Mode package for Emacs.
145perl v5.12.0 2009-07-20 Language(3)