perl-Verilog-Perl/Verilog::Netlist(3pm)

1Netlist(3)            User Contributed Perl Documentation           Netlist(3)
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NAME

6       Verilog::Netlist - Verilog Netlist
7

SYNOPSIS

9           use Verilog::Netlist;
10
11           # Setup options so files can be found
12           use Verilog::Getopt;
13           my $opt = new Verilog::Getopt;
14           $opt->parameter( "+incdir+verilog",
15                            "-y","verilog",
16                            );
17
18           # Prepare netlist
19           my $nl = new Verilog::Netlist (options => $opt,);
20           foreach my $file ('testnetlist.v') {
21               $nl->read_file (filename=>$file);
22           }
23           # Read in any sub-modules
24           $nl->link();
25           #$nl->lint();  # Optional, see docs; probably not wanted
26           $nl->exit_if_error();
27
28           foreach my $mod ($nl->top_modules_sorted) {
29               show_hier ($mod, "  ", "", "");
30           }
31
32           sub show_hier {
33               my $mod = shift;
34               my $indent = shift;
35               my $hier = shift;
36               my $cellname = shift;
37               if (!$cellname) {$hier = $mod->name;} #top modules get the design name
38               else {$hier .= ".$cellname";} #append the cellname
39               printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
40               foreach my $sig ($mod->ports_sorted) {
41                   printf ($indent."     %sput %s\n", $sig->direction, $sig->name);
42               }
43               foreach my $cell ($mod->cells_sorted) {
44                   printf ($indent. "    Cell %s\n", $cell->name);
45                   foreach my $pin ($cell->pins_sorted) {
46                       printf ($indent."     .%s(%s)\n", $pin->name, $pin->netname);
47                   }
48                   show_hier ($cell->submod, $indent."  ", $hier, $cell->name) if $cell->submod;
49               }
50           }
51

DESCRIPTION

53       Verilog::Netlist reads and holds interconnect information about a whole
54       design database.
55
56       See the "Which Package" section of Verilog::Language if you are unsure
57       which parsing package to use for a new application.
58
59       A Verilog::Netlist is composed of files, which contain the text read
60       from each file.
61
62       A file may contain modules, which are individual blocks that can be
63       instantiated (designs, in Synopsys terminology.)
64
65       Modules have ports, which are the interconnection between nets in that
66       module and the outside world.  Modules also have nets, (aka signals),
67       which interconnect the logic inside that module.
68
69       Modules can also instantiate other modules.  The instantiation of a
70       module is a Cell.  Cells have pins that interconnect the referenced
71       module's pin to a net in the module doing the instantiation.
72
73       Each of these types, files, modules, ports, nets, cells and pins have a
74       class.  For example Verilog::Netlist::Cell has the list of
75       Verilog::Netlist::Pin (s) that interconnect that cell.
76

FUNCTIONS

78       See also Verilog::Netlist::Subclass for additional accessors and
79       methods.
80
81       $netlist->lint
82           Error checks the entire netlist structure.  Currently there are
83           only two checks, that modules are bound to instantiations (which is
84           also checked by $netlist->link), and that signals aren't multiply
85           driven.  Note that as there is no elaboration you may get false
86           errors about multiple drivers from generate statements that are
87           mutually exclusive.  For this reason and the few lint checks you
88           may not want to use this method.  Alternatively to avoid pin
89           interconnect checks, set the $netlist->new (...use_vars=>0...)
90           option.
91
92       $netlist->link()
93           Resolves references between the different modules.
94
95           If link_read=>1 is passed when netlist->new is called (it is by
96           default), undefined modules will be searched for using the
97           Verilog::Getopt package, passed by a reference in the creation of
98           the netlist.  To suppress errors in any missing references, set
99           link_read_nonfatal=>1 also.
100
101       $netlist->new
102           Creates a new netlist structure.  Pass optional parameters by name,
103           with the following parameters:
104
105           implicit_wires_ok => $true_or_false
106                   Indicates whether to allow undeclared wires to be used.
107
108           include_open_nonfatal => $true_or_false
109                   Indicates that include files that do not exist should be
110                   ignored.
111
112           keep_comments => $true_or_false
113                   Indicates that comment fields should be preserved and on
114                   net declarations into the Vtest::Netlist::Net structures.
115                   Otherwise all comments are stripped for speed.
116
117           link_read => $true_or_false
118                   Indicates whether or not the parser should automatically
119                   search for undefined modules through the "options" object.
120
121           link_read_nonfatal => $true_or_false
122                   Indicates that modules that referenced but not found should
123                   be ignored, rather than causing an error message.
124
125           lint_pin_interconnect => $true_or_false
126                   Indicates that lint should Interconnect information is not
127                   needed, do not read it, nor report lint related pin
128                   warnings.  Greatly improves performance.
129
130           logger => object
131                   Specify a message handler object to be used for error
132                   handling, this class should be a Verilog::Netlist::Logger
133                   object, or derived from one.  If unspecified, a
134                   Verilog::Netlist::Logger local to this netlist will be
135                   used.
136
137           options => $opt_object
138                   An optional pointer to a Verilog::Getopt object, to be used
139                   for locating files.
140
141           preproc => $package_name
142                   The name of the preprocessor class. Defaults to
143                   "Verilog::Preproc".
144
145           use_vars => $true_or_false
146                   Indicates that signals, variables, and pin interconnect
147                   information is needed; set by default.  If clear do not
148                   read it, nor report lint related pin warnings, which can
149                   greatly improve performance.
150
151       $netlist->dump
152           Prints debugging information for the entire netlist structure.
153

INTERFACE FUNCTIONS

155       $netlist->find_interface($name)
156           Returns Verilog::Netlist::Interface matching given name.
157
158       $netlist->interfaces
159           Returns list of Verilog::Netlist::Interface.
160
161       $netlist->interfaces_sorted
162           Returns name sorted list of Verilog::Netlist::Interface.
163
164       $netlist->new_interface
165           Creates a new Verilog::Netlist::Interface.
166

MODULE FUNCTIONS

168       $netlist->find_module($name)
169           Returns Verilog::Netlist::Module matching given name.
170
171       $netlist->modules
172           Returns list of Verilog::Netlist::Module.
173
174       $netlist->modules_sorted
175           Returns name sorted list of Verilog::Netlist::Module.
176
177       $netlist->modules_sorted_level
178           Returns level sorted list of Verilog::Netlist::Module.  Leaf
179           modules will be first, the top most module will be last.
180
181       $netlist->new_module
182           Creates a new Verilog::Netlist::Module.
183
184       $netlist->top_modules_sorted
185           Returns name sorted list of Verilog::Netlist::Module, only for
186           those modules which have no children and are not unused library
187           cells.
188

FILE FUNCTIONS

190       $netlist->dependency_write(filename)
191           Writes a dependency file for make, listing all input and output
192           files.
193
194       $netlist->defvalue_nowarn (define)
195           Return the value of the specified define or undef.
196
197       $netlist->dependency_in(filename)
198           Adds an additional input dependency for dependency_write.
199
200       $netlist->dependency_out(filename)
201           Adds an additional output dependency for dependency_write.
202
203       $netlist->delete
204           Delete the netlist, reclaim memory.  Unfortunately netlists will
205           not disappear simply with normal garbage collection from leaving of
206           scope due to complications with reference counting and weaking
207           Class::Struct structures; solutions welcome.
208
209       $netlist->files
210           Returns list of Verilog::Netlist::File.
211
212       $netlist->files_sorted
213           Returns a name sorted list of Verilog::Netlist::File.
214
215       $netlist->find_file($name)
216           Returns Verilog::Netlist::File matching given name.
217
218       $netlist->read_file( filename=>$name)
219           Reads the given Verilog file, and returns a Verilog::Netlist::File
220           reference.
221
222           Generally called as $netlist->read_file.  Pass a hash of
223           parameters.  Reads the filename=> parameter, parsing all
224           instantiations, ports, and signals, and creating
225           Verilog::Netlist::Module structures.
226
227       $netlist->read_libraries ()
228           Read any libraries specified in the options=> argument passed with
229           the netlist constructor.  Automatically invoked when netlist
230           linking results in a module that wasn't found, and thus might be
231           inside the libraries.
232
233       $netlist->remove_defines (string)
234           Expand any `defines in the string and return the results.
235           Undefined defines will remain in the returned string.
236
237       $netlist->resolve_filename (string, [lookup_type])
238           Convert a module name to a filename.  Optional lookup_type is
239           'module', 'include', or 'all', to use only module_dirs, incdirs, or
240           both for the lookup.  Return undef if not found.
241
242       $self->verilog_text
243           Returns verilog code which represents the netlist.  The netlist
244           must be already ->link'ed for this to work correctly.
245

BUGS

247       Cell instantiations without any arguments are not supported, a empty
248       set of parenthesis are required.  (Use "cell cell();", not "cell
249       cell;".)
250
251       Order based pin interconnect is not supported, use name based
252       connections.
253

DISTRIBUTION

255       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
256       software tool suite.  The latest version is available from CPAN and
257       from http://www.veripool.org/verilog-perl
258       <http://www.veripool.org/verilog-perl>.
259
260       Copyright 2000-2010 by Wilson Snyder.  This package is free software;
261       you can redistribute it and/or modify it under the terms of either the
262       GNU Lesser General Public License Version 3 or the Perl Artistic
263       License Version 2.0.
264

AUTHORS

266       Wilson Snyder <wsnyder@wsnyder.org>
267