1SigParser(3) User Contributed Perl Documentation SigParser(3)
2
6 Verilog::SigParser - Signal Parsing for Verilog language files
7
9 use Verilog::Preproc;
10 use Verilog::SigParser;
11 my $pp = Verilog::Preproc->new(keep_comments=>0,);
13 my $parser = new Verilog::SigParser;
15 $parser->parse_preproc_file ($pp);
16 # The below described callbacks are then invoked
17
19 Verilog::SigParser builds upon the Verilog::Parser module to provide
20 callbacks for when a signal is declared, a module instantiated, or a
21 module defined.
22 See the "Which Package" section of Verilog::Language if you are unsure
24 which parsing package to use for a new application. For a higher level
25 interface to this package, see Verilog::Netlist.
26
28 The method interface to Verilog::SigParser is described in the
29 Verilog::Parser module which this package inherits. You will probably
30 want to use the preprocessing option of Verilog::Parser with this
31 package.
32
34 In order to make the parser do anything interesting, you must make a
35 subclass where you override one or more of the following methods as
36 appropriate.
37 Note Verilog::Parser callbacks also are invoked when SigParser is
39 parsing.
40 $self->attribute ( $text )
42 Scanned an attribute or meta-comment. The parser inspects the
43 first word of each comment line ("//key rest" to end of line) or
44 comment block ("/*key rest */). It calls "$self-"attribute(
45 meta_text )" if the first word has a true value in hash
46 "$self-"metacomment>.
47 $self->contassign ( $token, $lhs, $rhs )
49 This method is called at a continuous "assign" keyword, with the
50 left and right hand part of the assignment. Note that "wire"
51 initializations are not considered assignments; those are received
52 via the var callback's value parameter.
53 $self->defparam ( $token, $lhs, $rhs )
55 This method is called at a "defparam" keyword, with the left and
56 right hand part of the assignment.
57 $self->endcell ( $token )
59 This method is called at the end of defining a cell. It is useful
60 for writing clean up routines.
61 $self->endinterface ( $token )
63 This method is called at a endinterface keyword. It is useful for
64 writing clean up routines.
65 $self->endtaskfunc ( $token )
67 This method is called at a endfunction or endtask keyword. It is
68 useful for writing clean up routines.
69 $self->endmodport ( $token )
71 This method is called at a endmodport keyword. It is useful for
72 writing clean up routines.
73 $self->endmodule ( $token )
75 This method is called at a endmodule keyword. It is useful for
76 writing clean up routines.
77 $self->endpackage ( $token )
79 This method is called at a endpackage keyword. It is useful for
80 writing clean up routines.
81 $self->endprogram ( $token )
83 This method is called at a endprogram keyword. It is useful for
84 writing clean up routines.
85 $self->function ( $keyword, $name, $data-type )
87 This method is called when a function is defined. Type is the
88 output size or typename, plus "signed", for example "", "[3:0]",
89 "integer", or "signed [2:0]".
90 $self->import ( $package, $id )
92 This method is called when an import is defined.
93 $self->instant ( $module, $cell, $range )
95 This method is called when a instantiation is defined. The first
96 parameter is the name of the module being instantiated. The second
97 parameter is the name of the cell, which may be "" for primitives.
98 The third is the range if the cell was arrayed.
99 Prior to version 3.000, the name of the parameters were also
101 included in this callback. This has been replaced with the parampin
102 callback.
103 $self->interface ( $keyword, $name )
105 This method is called when an interface is defined.
106 $self->modport ( $keyword, $name )
108 This method is called when an interface modport is defined.
109 $self->module ( $keyword, $name, ignored, $in_celldefine )
111 This method is called when a module is defined.
112 $self->package ( $keyword, $name )
114 This method is called when a package is defined.
115 $self->parampin ( $name, $connection, $index )
117 This method is called when a parameter is connected to an
118 instantiation, IE the "#(...)" syntax. It is also used for UDP
119 delays (Three calls for "#(delay0,delay1,delay2)"), as the parser
120 does not know if the instantiation is for an UDP versus a module.
121 $self->pin ( $name, $connection, $index )
123 This method is called when a pin on a instant is defined. If a pin
124 name was not provided and the connection is by position, name will
125 be '' or undef.
126 If you do not need the pin nor var nor port callbacks, consider the
128 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
129 $self->port ( $name, $objof, $direction, $data_type, $array, $pinnum )
131 This method is called when a module port is defined. It may be
132 called twice on a port if the 1995 style is used; the first call is
133 made at the port header, the second call at the input/output
134 declaration.
135 The first argument $name, is the name of the port. $objof is what
137 the port is an object of ('module', 'function', etc). $direction
138 is the port direction ('input', 'output', 'inout', 'ref', 'const
139 ref', or 'interface'). $data_type is the data type ('reg',
140 'user_type_t', 'signed [31:0]', etc, or for interfaces the
141 "{interface_id}.{modport_name}"). $array is the arraying of the
142 port ('[1:0][2:0]', '', etc). $pinnum is set to the pin number for
143 ANSI style declarations, and 0 for Verilog 1995 declarations made
144 outside the port list.
145 If you do not need the pin nor var nor port callbacks, consider the
147 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
148 $self->ppdefine ( $defvar, $definition )
150 This method is called when a preprocessor definition is
151 encountered.
152 $self->program ( $keyword, $name )
154 This method is called when a program is defined.
155 $self->signal_decl ( $keyword, $signame, $vector, $mem, $signed, $value
157 )
158 This method is no longer used, see $self->var.
159 $self->task ( $keyword, $name )
161 This method is called when a task is defined.
162 $self->var ( $kwd, $name, $objof, $nettype, $data_type, $array, $value
164 )
165 This method is called when a variable or net is defined.
166 The first argument $kwd is how it was declared ('port', 'var',
168 'genvar', 'parameter', 'localparam', 'typedef') or if applicable a
169 net type ('supply0', 'wire', etc). $name is the name of the
170 variable. $objof is what the variable is an object of ('module',
171 'function', etc). $nettype is the net type if any was defined ('',
172 'supply0', 'wire', 'tri', etc). $data_type is the data type
173 ('user_type_t', '[31:0] signed', etc). $array is the arraying of
174 the variable which is the text AFTER the variable name
175 ('[1:0][2:0]', '', etc). $value is what the variable was assigned
176 to ('', or expression).
177 Note typedefs are included here, because "parameter type" is both a
179 variable and a type declaration.
180 If you do not need the pin nor var nor port callbacks, consider the
182 "$self->new (... use_vars=>0 ...)" option to accelerate parsing.
183 Below are some example declarations and the callbacks:
185 reg [4:0] vect = 5'b10100;
187 # VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
188 wire (weak0, weak1) value = pullval;
189 # VAR 'net' 'value' 'module' 'wire' '' '' 'pullval'
190 reg [1:0] mem [12:2];
191 # VAR 'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
192 int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
193 # verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
194 module ( output logic [SZ-1:0] o_sized );
195 # VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
196 struct packed signed { bit [7:0] m_b; };
197 # VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''
198
200 This is being distributed as a baseline for future contributions.
201 Don't expect a lot, the Parser is still naive, and there are many
202 awkward cases that aren't covered.
203 Note the SigParser is focused on extracting signal information. It
205 does NOT extract enough information to derive general interconnect; for
206 example the contents of 'assign' statements are not parsed.
207
209 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
210 software tool suite. The latest version is available from CPAN and
211 from http://www.veripool.org/verilog-perl
212 <http://www.veripool.org/verilog-perl>.
213 Copyright 2000-2010 by Wilson Snyder. This package is free software;
215 you can redistribute it and/or modify it under the terms of either the
216 GNU Lesser General Public License Version 3 or the Perl Artistic
217 License Version 2.0.
218
220 Wilson Snyder <wsnyder@wsnyder.org>
221
223 Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist,
224 Verilog::Getopt
225perl v5.12.2 2010-10-25 SigParser(3)