1Parser(3)             User Contributed Perl Documentation            Parser(3)
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NAME

6       Hardware::Verilog::Parser - A complete grammar for parsing Verilog code
7       using perl
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SYNOPSIS

10         use Hardware::Verilog::Parser;
11         $parser = new Hardware::Verilog::Parser;
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13         $parser->Filename(@ARGV);
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DESCRIPTION

16       This module defines the complete grammar needed to parse any Verilog
17       code.  By overloading this grammar, it is possible to easily create
18       perl scripts which run through Verilog code and perform specific
19       functions.
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21       For example, a Hierarchy.pm uses Hardware::Verilog::Parser to overload
22       the grammar rule for module instantiations. This single modification
23       will print out all instance names that occur in the file being parsed.
24       This might be useful for creating an automatic build script, or a
25       graphical hierarchical browser of a Verilog design.
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27       This module is currently in alpha release. All code is subject to
28       change.  Bug reports are welcome.
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30       DSLI information:
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32       D - Development Stage
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34               a - alpha testing
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36       S - Support Level
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38               d - developer
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40       L - Language used
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42               p - perl only, no compiler needed, should be platform independent
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44       I - Interface Style
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46               O - Object oriented using blessed references and / or inheritance
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AUTHOR

49       Copyright (C) 2000 Greg London   All Rights Reserved.
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51       This program is free software; you can redistribute it and/or modify it
52       under the same terms as Perl itself.
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54       email contact: greg42@bellatlantic.net
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SEE ALSO

57       Parse::RecDescent, version 1.77
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59       perl(1).
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63perl v5.28.1                      2019-02-02                         Parser(3)