1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]] [--alternate] [-D]
10        [--compress-debug-sections]  [--nocompress-debug-sections]
11        [--debug-prefix-map old=new]
12        [--defsym sym=val] [-f] [-g] [--gstabs]
13        [--gstabs+] [--gdwarf-2] [--gdwarf-sections]
14        [--gdwarf-cie-version=VERSION]
15        [--help] [-I dir] [-J]
16        [-K] [-L] [--listing-lhs-width=NUM]
17        [--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
18        [--listing-cont-lines=NUM] [--keep-locals]
19        [--no-pad-sections]
20        [-o objfile] [-R]
21        [--hash-size=NUM] [--reduce-memory-overheads]
22        [--statistics]
23        [-v] [-version] [--version]
24        [-W] [--warn] [--fatal-warnings] [-w] [-x]
25        [-Z] [@FILE]
26        [--sectname-subst] [--size-check=[error|warning]]
27        [--elf-stt-common=[no|yes]]
28        [--generate-missing-build-notes=[no|yes]]
29        [--target-help] [target-options]
30        [--|files ...]
31

TARGET

33       Target AArch64 options:
34          [-EB|-EL]
35          [-mabi=ABI]
36
37       Target Alpha options:
38          [-mcpu]
39          [-mdebug | -no-mdebug]
40          [-replace | -noreplace]
41          [-relax] [-g] [-Gsize]
42          [-F] [-32addr]
43
44       Target ARC options:
45          [-mcpu=cpu]
46          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
47          [-mcode-density]
48          [-mrelax]
49          [-EB|-EL]
50
51       Target ARM options:
52          [-mcpu=processor[+extension...]]
53          [-march=architecture[+extension...]]
54          [-mfpu=floating-point-format]
55          [-mfloat-abi=abi]
56          [-meabi=ver]
57          [-mthumb]
58          [-EB|-EL]
59          [-mapcs-32|-mapcs-26|-mapcs-float|
60           -mapcs-reentrant]
61          [-mthumb-interwork] [-k]
62
63       Target Blackfin options:
64          [-mcpu=processor[-sirevision]]
65          [-mfdpic]
66          [-mno-fdpic]
67          [-mnopic]
68
69       Target BPF options:
70          [-EL] [-EB]
71
72       Target CRIS options:
73          [--underscore | --no-underscore]
74          [--pic] [-N]
75          [--emulation=criself | --emulation=crisaout]
76          [--march=v0_v10 | --march=v10 | --march=v32 |
77       --march=common_v10_v32]
78
79       Target C-SKY options:
80          [-march=arch] [-mcpu=cpu]
81          [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
82          [-fpic] [-pic]
83          [-mljump] [-mno-ljump]
84          [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
85          [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
86          [-mnolrw ] [-mno-lrw]
87          [-melrw] [-mno-elrw]
88          [-mlaf ] [-mliterals-after-func]
89          [-mno-laf] [-mno-literals-after-func]
90          [-mlabr] [-mliterals-after-br]
91          [-mno-labr] [-mnoliterals-after-br]
92          [-mistack] [-mno-istack]
93          [-mhard-float] [-mmp] [-mcp] [-mcache]
94          [-msecurity] [-mtrust]
95          [-mdsp] [-medsp] [-mvdsp]
96
97       Target D10V options:
98          [-O]
99
100       Target D30V options:
101          [-O|-n|-N]
102
103       Target EPIPHANY options:
104          [-mepiphany|-mepiphany16]
105
106       Target H8/300 options:
107          [-h-tick-hex]
108
109       Target i386 options:
110          [--32|--x32|--64] [-n]
111          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
112
113       Target IA-64 options:
114          [-mconstant-gp|-mauto-pic]
115          [-milp32|-milp64|-mlp64|-mp64]
116          [-mle|mbe]
117          [-mtune=itanium1|-mtune=itanium2]
118          [-munwind-check=warning|-munwind-check=error]
119          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
120          [-x|-xexplicit] [-xauto] [-xdebug]
121
122       Target IP2K options:
123          [-mip2022|-mip2022ext]
124
125       Target M32C options:
126          [-m32c|-m16c] [-relax] [-h-tick-hex]
127
128       Target M32R options:
129          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
130          --W[n]p]
131
132       Target M680X0 options:
133          [-l] [-m68000|-m68010|-m68020|...]
134
135       Target M68HC11 options:
136          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
137          [-mshort|-mlong]
138          [-mshort-double|-mlong-double]
139          [--force-long-branches] [--short-branches]
140          [--strict-direct-mode] [--print-insn-syntax]
141          [--print-opcodes] [--generate-example]
142
143       Target MCORE options:
144          [-jsri2bsr] [-sifilter] [-relax]
145          [-mcpu=[210|340]]
146
147       Target Meta options:
148          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
149
150       Target MIPS options:
151          [-nocpp] [-EL] [-EB] [-O[optimization level]]
152          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
153          [-non_shared] [-xgot [-mvxworks-pic]
154          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
155          [-mfp64] [-mgp64] [-mfpxx]
156          [-modd-spreg] [-mno-odd-spreg]
157          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
158          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
159          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
160          [-mips64r3] [-mips64r5] [-mips64r6]
161          [-construct-floats] [-no-construct-floats]
162          [-mignore-branch-isa] [-mno-ignore-branch-isa]
163          [-mnan=encoding]
164          [-trap] [-no-break] [-break] [-no-trap]
165          [-mips16] [-no-mips16]
166          [-mmips16e2] [-mno-mips16e2]
167          [-mmicromips] [-mno-micromips]
168          [-msmartmips] [-mno-smartmips]
169          [-mips3d] [-no-mips3d]
170          [-mdmx] [-no-mdmx]
171          [-mdsp] [-mno-dsp]
172          [-mdspr2] [-mno-dspr2]
173          [-mdspr3] [-mno-dspr3]
174          [-mmsa] [-mno-msa]
175          [-mxpa] [-mno-xpa]
176          [-mmt] [-mno-mt]
177          [-mmcu] [-mno-mcu]
178          [-mcrc] [-mno-crc]
179          [-mginv] [-mno-ginv]
180          [-mloongson-mmi] [-mno-loongson-mmi]
181          [-mloongson-cam] [-mno-loongson-cam]
182          [-mloongson-ext] [-mno-loongson-ext]
183          [-mloongson-ext2] [-mno-loongson-ext2]
184          [-minsn32] [-mno-insn32]
185          [-mfix7000] [-mno-fix7000]
186          [-mfix-rm7000] [-mno-fix-rm7000]
187          [-mfix-vr4120] [-mno-fix-vr4120]
188          [-mfix-vr4130] [-mno-fix-vr4130]
189          [-mfix-r5900] [-mno-fix-r5900]
190          [-mdebug] [-no-mdebug]
191          [-mpdr] [-mno-pdr]
192
193       Target MMIX options:
194          [--fixed-special-register-names] [--globalize-symbols]
195          [--gnu-syntax] [--relax] [--no-predefined-symbols]
196          [--no-expand] [--no-merge-gregs] [-x]
197          [--linker-allocated-gregs]
198
199       Target Nios II options:
200          [-relax-all] [-relax-section] [-no-relax]
201          [-EB] [-EL]
202
203       Target NDS32 options:
204           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
205           [-misa=isa] [-mabi=abi] [-mall-ext]
206           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
207           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
208           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
209           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
210           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
211           [-mb2bb]
212
213       Target PDP11 options:
214          [-mpic|-mno-pic] [-mall] [-mno-extensions]
215          [-mextension|-mno-extension]
216          [-mcpu] [-mmachine]
217
218       Target picoJava options:
219          [-mb|-me]
220
221       Target PowerPC options:
222          [-a32|-a64]
223          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
224           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
225           -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
226           -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
227           -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
228           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
229          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
230          [-mregnames|-mno-regnames]
231          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
232          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
233          [-msolaris|-mno-solaris]
234          [-nops=count]
235
236       Target PRU options:
237          [-link-relax]
238          [-mnolink-relax]
239          [-mno-warn-regname-label]
240
241       Target RISC-V options:
242          [-fpic|-fPIC|-fno-pic]
243          [-march=ISA]
244          [-mabi=ABI]
245
246       Target RL78 options:
247          [-mg10]
248          [-m32bit-doubles|-m64bit-doubles]
249
250       Target RX options:
251          [-mlittle-endian|-mbig-endian]
252          [-m32bit-doubles|-m64bit-doubles]
253          [-muse-conventional-section-names]
254          [-msmall-data-limit]
255          [-mpid]
256          [-mrelax]
257          [-mint-register=number]
258          [-mgcc-abi|-mrx-abi]
259
260       Target s390 options:
261          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
262          [-mregnames|-mno-regnames]
263          [-mwarn-areg-zero]
264
265       Target SCORE options:
266          [-EB][-EL][-FIXDD][-NWARN]
267          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
268          [-march=score7][-march=score3]
269          [-USE_R1][-KPIC][-O0][-G num][-V]
270
271       Target SPARC options:
272          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
273           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
274           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
275           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
276           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
277           -Asparcvisr|-Asparc5]
278          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
279           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
280           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
281           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
282           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
283           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
284           -bump]
285          [-32|-64]
286          [--enforce-aligned-data][--dcti-couples-detect]
287
288       Target TIC54X options:
289        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
290        [-merrors-to-file <filename>|-me <filename>]
291
292       Target TIC6X options:
293          [-march=arch] [-mbig-endian|-mlittle-endian]
294          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
295          [-mpic|-mno-pic]
296
297       Target TILE-Gx options:
298          [-m32|-m64][-EB][-EL]
299
300       Target Visium options:
301          [-mtune=arch]
302
303       Target Xtensa options:
304        [--[no-]text-section-literals] [--[no-]auto-litpools]
305        [--[no-]absolute-literals]
306        [--[no-]target-align] [--[no-]longcalls]
307        [--[no-]transform]
308        [--rename-section oldname=newname]
309        [--[no-]trampolines]
310
311       Target Z80 options:
312         [-z80]|[-z180]|[-r800]|[-ez80]|[-ez80-adl]
313         [-local-prefix=PREFIX]
314         [-colonless]
315         [-sdcc]
316         [-fp-s=FORMAT]
317         [-fp-d=FORMAT]
318         [-strict]|[-full]
319         [-with-inst=INST[,...]] [-Wnins INST[,...]]
320         [-without-inst=INST[,...]] [-Fins INST[,...]]
321         [ -ignore-undocumented-instructions] [-Wnud]
322         [ -ignore-unportable-instructions] [-Wnup]
323         [ -warn-undocumented-instructions] [-Wud]
324         [ -warn-unportable-instructions] [-Wup]
325         [ -forbid-undocumented-instructions] [-Fud]
326         [ -forbid-unportable-instructions] [-Fup]
327

DESCRIPTION

329       GNU as is really a family of assemblers.  If you use (or have used) the
330       GNU assembler on one architecture, you should find a fairly similar
331       environment when you use it on another architecture.  Each version has
332       much in common with the others, including object file formats, most
333       assembler directives (often called pseudo-ops) and assembler syntax.
334
335       as is primarily intended to assemble the output of the GNU C compiler
336       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
337       assemble correctly everything that other assemblers for the same
338       machine would assemble.  Any exceptions are documented explicitly.
339       This doesn't mean as always uses the same syntax as another assembler
340       for the same architecture; for example, we know of several incompatible
341       versions of 680x0 assembly language syntax.
342
343       Each time you run as it assembles exactly one source program.  The
344       source program is made up of one or more files.  (The standard input is
345       also a file.)
346
347       You give as a command line that has zero or more input file names.  The
348       input files are read (from left file name to right).  A command-line
349       argument (in any position) that has no special meaning is taken to be
350       an input file name.
351
352       If you give as no file names it attempts to read one input file from
353       the as standard input, which is normally your terminal.  You may have
354       to type ctl-D to tell as there is no more program to assemble.
355
356       Use -- if you need to explicitly name the standard input file in your
357       command line.
358
359       If the source is empty, as produces a small, empty object file.
360
361       as may write warnings and error messages to the standard error file
362       (usually your terminal).  This should not happen when  a compiler runs
363       as automatically.  Warnings report an assumption made so that as could
364       keep assembling a flawed program; errors report a grave problem that
365       stops the assembly.
366
367       If you are invoking as via the GNU C compiler, you can use the -Wa
368       option to pass arguments through to the assembler.  The assembler
369       arguments must be separated from each other (and the -Wa) by commas.
370       For example:
371
372               gcc -c -g -O -Wa,-alh,-L file.c
373
374       This passes two options to the assembler: -alh (emit a listing to
375       standard output with high-level and assembly source) and -L (retain
376       local symbols in the symbol table).
377
378       Usually you do not need to use this -Wa mechanism, since many compiler
379       command-line options are automatically passed to the assembler by the
380       compiler.  (You can call the GNU compiler driver with the -v option to
381       see precisely what options it passes to each compilation pass,
382       including the assembler.)
383

OPTIONS

385       @file
386           Read command-line options from file.  The options read are inserted
387           in place of the original @file option.  If file does not exist, or
388           cannot be read, then the option will be treated literally, and not
389           removed.
390
391           Options in file are separated by whitespace.  A whitespace
392           character may be included in an option by surrounding the entire
393           option in either single or double quotes.  Any character (including
394           a backslash) may be included by prefixing the character to be
395           included with a backslash.  The file may itself contain additional
396           @file options; any such options will be processed recursively.
397
398       -a[cdghlmns]
399           Turn on listings, in any of a variety of ways:
400
401           -ac omit false conditionals
402
403           -ad omit debugging directives
404
405           -ag include general information, like as version and options passed
406
407           -ah include high-level source
408
409           -al include assembly
410
411           -am include macro expansions
412
413           -an omit forms processing
414
415           -as include symbols
416
417           =file
418               set the name of the listing file
419
420           You may combine these options; for example, use -aln for assembly
421           listing without forms processing.  The =file option, if used, must
422           be the last one.  By itself, -a defaults to -ahls.
423
424       --alternate
425           Begin in alternate macro mode.
426
427       --compress-debug-sections
428           Compress DWARF debug sections using zlib with SHF_COMPRESSED from
429           the ELF ABI.  The resulting object file may not be compatible with
430           older linkers and object file utilities.  Note if compression would
431           make a given section larger then it is not compressed.
432
433       --compress-debug-sections=none
434       --compress-debug-sections=zlib
435       --compress-debug-sections=zlib-gnu
436       --compress-debug-sections=zlib-gabi
437           These options control how DWARF debug sections are compressed.
438           --compress-debug-sections=none is equivalent to
439           --nocompress-debug-sections.  --compress-debug-sections=zlib and
440           --compress-debug-sections=zlib-gabi are equivalent to
441           --compress-debug-sections.  --compress-debug-sections=zlib-gnu
442           compresses DWARF debug sections using zlib.  The debug sections are
443           renamed to begin with .zdebug.  Note if compression would make a
444           given section larger then it is not compressed nor renamed.
445
446       --nocompress-debug-sections
447           Do not compress DWARF debug sections.  This is usually the default
448           for all targets except the x86/x86_64, but a configure time option
449           can be used to override this.
450
451       -D  Ignored.  This option is accepted for script compatibility with
452           calls to other assemblers.
453
454       --debug-prefix-map old=new
455           When assembling files in directory old, record debugging
456           information describing them as in new instead.
457
458       --defsym sym=value
459           Define the symbol sym to be value before assembling the input file.
460           value must be an integer constant.  As in C, a leading 0x indicates
461           a hexadecimal value, and a leading 0 indicates an octal value.  The
462           value of the symbol can be overridden inside a source file via the
463           use of a ".set" pseudo-op.
464
465       -f  "fast"---skip whitespace and comment preprocessing (assume source
466           is compiler output).
467
468       -g
469       --gen-debug
470           Generate debugging information for each assembler source line using
471           whichever debug format is preferred by the target.  This currently
472           means either STABS, ECOFF or DWARF2.
473
474       --gstabs
475           Generate stabs debugging information for each assembler line.  This
476           may help debugging assembler code, if the debugger can handle it.
477
478       --gstabs+
479           Generate stabs debugging information for each assembler line, with
480           GNU extensions that probably only gdb can handle, and that could
481           make other debuggers crash or refuse to read your program.  This
482           may help debugging assembler code.  Currently the only GNU
483           extension is the location of the current working directory at
484           assembling time.
485
486       --gdwarf-2
487           Generate DWARF2 debugging information for each assembler line.
488           This may help debugging assembler code, if the debugger can handle
489           it.  Note---this option is only supported by some targets, not all
490           of them.
491
492       --gdwarf-sections
493           Instead of creating a .debug_line section, create a series of
494           .debug_line.foo sections where foo is the name of the corresponding
495           code section.  For example a code section called .text.func will
496           have its dwarf line number information placed into a section called
497           .debug_line.text.func.  If the code section is just called .text
498           then debug line section will still be called just .debug_line
499           without any suffix.
500
501       --gdwarf-cie-version=version
502           Control which version of DWARF Common Information Entries (CIEs)
503           are produced.  When this flag is not specificed the default is
504           version 1, though some targets can modify this default.  Other
505           possible values for version are 3 or 4.
506
507       --size-check=error
508       --size-check=warning
509           Issue an error or warning for invalid ELF .size directive.
510
511       --elf-stt-common=no
512       --elf-stt-common=yes
513           These options control whether the ELF assembler should generate
514           common symbols with the "STT_COMMON" type.  The default can be
515           controlled by a configure option --enable-elf-stt-common.
516
517       --generate-missing-build-notes=yes
518       --generate-missing-build-notes=no
519           These options control whether the ELF assembler should generate GNU
520           Build attribute notes if none are present in the input sources.
521           The default can be controlled by the --enable-generate-build-notes
522           configure option.
523
524       --help
525           Print a summary of the command-line options and exit.
526
527       --target-help
528           Print a summary of all target specific options and exit.
529
530       -I dir
531           Add directory dir to the search list for ".include" directives.
532
533       -J  Don't warn about signed overflow.
534
535       -K  Issue warnings when difference tables altered for long
536           displacements.
537
538       -L
539       --keep-locals
540           Keep (in the symbol table) local symbols.  These symbols start with
541           system-specific local label prefixes, typically .L for ELF systems
542           or L for traditional a.out systems.
543
544       --listing-lhs-width=number
545           Set the maximum width, in words, of the output data column for an
546           assembler listing to number.
547
548       --listing-lhs-width2=number
549           Set the maximum width, in words, of the output data column for
550           continuation lines in an assembler listing to number.
551
552       --listing-rhs-width=number
553           Set the maximum width of an input source line, as displayed in a
554           listing, to number bytes.
555
556       --listing-cont-lines=number
557           Set the maximum number of lines printed in a listing for a single
558           line of input to number + 1.
559
560       --no-pad-sections
561           Stop the assembler for padding the ends of output sections to the
562           alignment of that section.  The default is to pad the sections, but
563           this can waste space which might be needed on targets which have
564           tight memory constraints.
565
566       -o objfile
567           Name the object-file output from as objfile.
568
569       -R  Fold the data section into the text section.
570
571       --hash-size=number
572           Set the default size of GAS's hash tables to a prime number close
573           to number.  Increasing this value can reduce the length of time it
574           takes the assembler to perform its tasks, at the expense of
575           increasing the assembler's memory requirements.  Similarly reducing
576           this value can reduce the memory requirements at the expense of
577           speed.
578
579       --reduce-memory-overheads
580           This option reduces GAS's memory requirements, at the expense of
581           making the assembly processes slower.  Currently this switch is a
582           synonym for --hash-size=4051, but in the future it may have other
583           effects as well.
584
585       --sectname-subst
586           Honor substitution sequences in section names.
587
588       --statistics
589           Print the maximum space (in bytes) and total time (in seconds) used
590           by assembly.
591
592       --strip-local-absolute
593           Remove local absolute symbols from the outgoing symbol table.
594
595       -v
596       -version
597           Print the as version.
598
599       --version
600           Print the as version and exit.
601
602       -W
603       --no-warn
604           Suppress warning messages.
605
606       --fatal-warnings
607           Treat warnings as errors.
608
609       --warn
610           Don't suppress warning messages or treat them as errors.
611
612       -w  Ignored.
613
614       -x  Ignored.
615
616       -Z  Generate an object file even after errors.
617
618       -- | files ...
619           Standard input, or source files to assemble.
620
621       The following options are available when as is configured for the
622       64-bit mode of the ARM Architecture (AArch64).
623
624       -EB This option specifies that the output generated by the assembler
625           should be marked as being encoded for a big-endian processor.
626
627       -EL This option specifies that the output generated by the assembler
628           should be marked as being encoded for a little-endian processor.
629
630       -mabi=abi
631           Specify which ABI the source code uses.  The recognized arguments
632           are: "ilp32" and "lp64", which decides the generated object file in
633           ELF32 and ELF64 format respectively.  The default is "lp64".
634
635       -mcpu=processor[+extension...]
636           This option specifies the target processor.  The assembler will
637           issue an error message if an attempt is made to assemble an
638           instruction which will not execute on the target processor.  The
639           following processor names are recognized: "cortex-a34",
640           "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
641           "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
642           "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77", "ares",
643           "exynos-m1", "falkor", "neoverse-n1", "neoverse-e1", "qdf24xx",
644           "saphira", "thunderx", "vulcan", "xgene1" and "xgene2".  The
645           special name "all" may be used to allow the assembler to accept
646           instructions valid for any supported processor, including all
647           optional extensions.
648
649           In addition to the basic instruction set, the assembler can be told
650           to accept, or restrict, various extension mnemonics that extend the
651           processor.
652
653           If some implementations of a particular processor can have an
654           extension, then then those extensions are automatically enabled.
655           Consequently, you will not normally have to specify any additional
656           extensions.
657
658       -march=architecture[+extension...]
659           This option specifies the target architecture.  The assembler will
660           issue an error message if an attempt is made to assemble an
661           instruction which will not execute on the target architecture.  The
662           following architecture names are recognized: "armv8-a",
663           "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a", and
664           "armv8.6-a".
665
666           If both -mcpu and -march are specified, the assembler will use the
667           setting for -mcpu.  If neither are specified, the assembler will
668           default to -mcpu=all.
669
670           The architecture option can be extended with the same instruction
671           set extension options as the -mcpu option.  Unlike -mcpu,
672           extensions are not always enabled by default,
673
674       -mverbose-error
675           This option enables verbose error messages for AArch64 gas.  This
676           option is enabled by default.
677
678       -mno-verbose-error
679           This option disables verbose error messages in AArch64 gas.
680
681       The following options are available when as is configured for an Alpha
682       processor.
683
684       -mcpu
685           This option specifies the target processor.  If an attempt is made
686           to assemble an instruction which will not execute on the target
687           processor, the assembler may either expand the instruction as a
688           macro or issue an error message.  This option is equivalent to the
689           ".arch" directive.
690
691           The following processor names are recognized: 21064, "21064a",
692           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
693           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
694           "ev67", "ev68".  The special name "all" may be used to allow the
695           assembler to accept instructions valid for any Alpha processor.
696
697           In order to support existing practice in OSF/1 with respect to
698           ".arch", and existing practice within MILO (the Linux ARC
699           bootloader), the numbered processor names (e.g. 21064) enable the
700           processor-specific PALcode instructions, while the "electro-vlasic"
701           names (e.g. "ev4") do not.
702
703       -mdebug
704       -no-mdebug
705           Enables or disables the generation of ".mdebug" encapsulation for
706           stabs directives and procedure descriptors.  The default is to
707           automatically enable ".mdebug" when the first stabs directive is
708           seen.
709
710       -relax
711           This option forces all relocations to be put into the object file,
712           instead of saving space and resolving some relocations at assembly
713           time.  Note that this option does not propagate all symbol
714           arithmetic into the object file, because not all symbol arithmetic
715           can be represented.  However, the option can still be useful in
716           specific applications.
717
718       -replace
719       -noreplace
720           Enables or disables the optimization of procedure calls, both at
721           assemblage and at link time.  These options are only available for
722           VMS targets and "-replace" is the default.  See section 1.4.1 of
723           the OpenVMS Linker Utility Manual.
724
725       -g  This option is used when the compiler generates debug information.
726           When gcc is using mips-tfile to generate debug information for
727           ECOFF, local labels must be passed through to the object file.
728           Otherwise this option has no effect.
729
730       -Gsize
731           A local common symbol larger than size is placed in ".bss", while
732           smaller symbols are placed in ".sbss".
733
734       -F
735       -32addr
736           These options are ignored for backward compatibility.
737
738       The following options are available when as is configured for an ARC
739       processor.
740
741       -mcpu=cpu
742           This option selects the core processor variant.
743
744       -EB | -EL
745           Select either big-endian (-EB) or little-endian (-EL) output.
746
747       -mcode-density
748           Enable Code Density extenssion instructions.
749
750       The following options are available when as is configured for the ARM
751       processor family.
752
753       -mcpu=processor[+extension...]
754           Specify which ARM processor variant is the target.
755
756       -march=architecture[+extension...]
757           Specify which ARM architecture variant is used by the target.
758
759       -mfpu=floating-point-format
760           Select which Floating Point architecture is the target.
761
762       -mfloat-abi=abi
763           Select which floating point ABI is in use.
764
765       -mthumb
766           Enable Thumb only instruction decoding.
767
768       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
769           Select which procedure calling convention is in use.
770
771       -EB | -EL
772           Select either big-endian (-EB) or little-endian (-EL) output.
773
774       -mthumb-interwork
775           Specify that the code has been generated with interworking between
776           Thumb and ARM code in mind.
777
778       -mccs
779           Turns on CodeComposer Studio assembly syntax compatibility mode.
780
781       -k  Specify that PIC code has been generated.
782
783       The following options are available when as is configured for the
784       Blackfin processor family.
785
786       -mcpu=processor[-sirevision]
787           This option specifies the target processor.  The optional
788           sirevision is not used in assembler.  It's here such that GCC can
789           easily pass down its "-mcpu=" option.  The assembler will issue an
790           error message if an attempt is made to assemble an instruction
791           which will not execute on the target processor.  The following
792           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
793           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
794           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
795           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
796           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
797           "bf549", "bf549m", "bf561", and "bf592".
798
799       -mfdpic
800           Assemble for the FDPIC ABI.
801
802       -mno-fdpic
803       -mnopic
804           Disable -mfdpic.
805
806       The following options are available when as is configured for the Linux
807       kernel BPF processor family.
808
809       @chapter BPF Dependent Features
810
811   Options
812       -EB This option specifies that the assembler should emit big-endian
813           eBPF.
814
815       -EL This option specifies that the assembler should emit little-endian
816           eBPF.
817
818       Note that if no endianness option is specified in the command line, the
819       host endianness is used.  See the info pages for documentation of the
820       CRIS-specific options.
821
822       The following options are available when as is configured for the C-SKY
823       processor family.
824
825       -march=archname
826           Assemble for architecture archname.  The --help option lists valid
827           values for archname.
828
829       -mcpu=cpuname
830           Assemble for architecture cpuname.  The --help option lists valid
831           values for cpuname.
832
833       -EL
834       -mlittle-endian
835           Generate little-endian output.
836
837       -EB
838       -mbig-endian
839           Generate big-endian output.
840
841       -fpic
842       -pic
843           Generate position-independent code.
844
845       -mljump
846       -mno-ljump
847           Enable/disable transformation of the short branch instructions
848           "jbf", "jbt", and "jbr" to "jmpi".  This option is for V2
849           processors only.  It is ignored on CK801 and CK802 targets, which
850           do not support the "jmpi" instruction, and is enabled by default
851           for other processors.
852
853       -mbranch-stub
854       -mno-branch-stub
855           Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
856           instructions to the linker.
857
858           This option is only available for bare-metal C-SKY V2 ELF targets,
859           where it is enabled by default.  It cannot be used in code that
860           will be dynamically linked against shared libraries.
861
862       -force2bsr
863       -mforce2bsr
864       -no-force2bsr
865       -mno-force2bsr
866           Enable/disable transformation of "jbsr" instructions to "bsr".
867           This option is always enabled (and -mno-force2bsr is ignored) for
868           CK801/CK802 targets.  It is also always enabled when -mbranch-stub
869           is in effect.
870
871       -jsri2bsr
872       -mjsri2bsr
873       -no-jsri2bsr
874       -mno-jsri2bsr
875           Enable/disable transformation of "jsri" instructions to "bsr".
876           This option is enabled by default.
877
878       -mnolrw
879       -mno-lrw
880           Enable/disable transformation of "lrw" instructions into a
881           "movih"/"ori" pair.
882
883       -melrw
884       -mno-elrw
885           Enable/disable extended "lrw" instructions.  This option is enabled
886           by default for CK800-series processors.
887
888       -mlaf
889       -mliterals-after-func
890       -mno-laf
891       -mno-literals-after-func
892           Enable/disable placement of literal pools after each function.
893
894       -mlabr
895       -mliterals-after-br
896       -mno-labr
897       -mnoliterals-after-br
898           Enable/disable placement of literal pools after unconditional
899           branches.  This option is enabled by default.
900
901       -mistack
902       -mno-istack
903           Enable/disable interrupt stack instructions.  This option is
904           enabled by default on CK801, CK802, and CK802 processors.
905
906       The following options explicitly enable certain optional instructions.
907       These features are also enabled implicitly by using "-mcpu=" to specify
908       a processor that supports it.
909
910       -mhard-float
911           Enable hard float instructions.
912
913       -mmp
914           Enable multiprocessor instructions.
915
916       -mcp
917           Enable coprocessor instructions.
918
919       -mcache
920           Enable cache prefetch instruction.
921
922       -msecurity
923           Enable C-SKY security instructions.
924
925       -mtrust
926           Enable C-SKY trust instructions.
927
928       -mdsp
929           Enable DSP instructions.
930
931       -medsp
932           Enable enhanced DSP instructions.
933
934       -mvdsp
935           Enable vector DSP instructions.
936
937       The following options are available when as is configured for an
938       Epiphany processor.
939
940       -mepiphany
941           Specifies that the both 32 and 16 bit instructions are allowed.
942           This is the default behavior.
943
944       -mepiphany16
945           Restricts the permitted instructions to just the 16 bit set.
946
947       The following options are available when as is configured for an H8/300
948       processor.  @chapter H8/300 Dependent Features
949
950   Options
951       The Renesas H8/300 version of "as" has one machine-dependent option:
952
953       -h-tick-hex
954           Support H'00 style hex constants in addition to 0x00 style.
955
956       -mach=name
957           Sets the H8300 machine variant.  The following machine names are
958           recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
959           "h8300sxn".
960
961       The following options are available when as is configured for an i386
962       processor.
963
964       --32 | --x32 | --64
965           Select the word size, either 32 bits or 64 bits.  --32 implies
966           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
967           architecture with 32-bit or 64-bit word-size respectively.
968
969           These options are only available with the ELF object file format,
970           and require that the necessary BFD support has been included (on a
971           32-bit platform you have to add --enable-64-bit-bfd to configure
972           enable 64-bit usage and use x86-64 as target platform).
973
974       -n  By default, x86 GAS replaces multiple nop instructions used for
975           alignment within code sections with multi-byte nop instructions
976           such as leal 0(%esi,1),%esi.  This switch disables the optimization
977           if a single byte nop (0x90) is explicitly specified as the fill
978           byte for alignment.
979
980       --divide
981           On SVR4-derived platforms, the character / is treated as a comment
982           character, which means that it cannot be used in expressions.  The
983           --divide option turns / into a normal character.  This does not
984           disable / at the beginning of a line starting a comment, or affect
985           using # for starting a comment.
986
987       -march=CPU[+EXTENSION...]
988           This option specifies the target processor.  The assembler will
989           issue an error message if an attempt is made to assemble an
990           instruction which will not execute on the target processor.  The
991           following processor names are recognized: "i8086", "i186", "i286",
992           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
993           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
994           "core", "core2", "corei7", "l1om", "k1om", "iamcu", "k6", "k6_2",
995           "athlon", "opteron", "k8", "amdfam10", "bdver1", "bdver2",
996           "bdver3", "bdver4", "znver1", "znver2", "btver1", "btver2",
997           "generic32" and "generic64".
998
999           In addition to the basic instruction set, the assembler can be told
1000           to accept various extension mnemonics.  For example,
1001           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
1002           following extensions are currently supported: 8087, 287, 387, 687,
1003           "no87", "no287", "no387", "no687", "cmov", "nocmov", "fxsr",
1004           "nofxsr", "mmx", "nommx", "sse", "sse2", "sse3", "ssse3", "sse4.1",
1005           "sse4.2", "sse4", "nosse", "nosse2", "nosse3", "nossse3",
1006           "nosse4.1", "nosse4.2", "nosse4", "avx", "avx2", "noavx", "noavx2",
1007           "adx", "rdseed", "prfchw", "smap", "mpx", "sha", "rdpid",
1008           "ptwrite", "cet", "gfni", "vaes", "vpclmulqdq", "prefetchwt1",
1009           "clflushopt", "se1", "clwb", "movdiri", "movdir64b", "enqcmd",
1010           "avx512f", "avx512cd", "avx512er", "avx512pf", "avx512vl",
1011           "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
1012           "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
1013           "avx512_vbmi2", "avx512_vnni", "avx512_bitalg", "avx512_bf16",
1014           "noavx512f", "noavx512cd", "noavx512er", "noavx512pf",
1015           "noavx512vl", "noavx512bw", "noavx512dq", "noavx512ifma",
1016           "noavx512vbmi", "noavx512_4fmaps", "noavx512_4vnniw",
1017           "noavx512_vpopcntdq", "noavx512_vbmi2", "noavx512_vnni",
1018           "noavx512_bitalg", "noavx512_vp2intersect", "noavx512_bf16",
1019           "noenqcmd", "vmx", "vmfunc", "smx", "xsave", "xsaveopt", "xsavec",
1020           "xsaves", "aes", "pclmul", "fsgsbase", "rdrnd", "f16c", "bmi2",
1021           "fma", "movbe", "ept", "lzcnt", "hle", "rtm", "invpcid", "clflush",
1022           "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg", "cldemote",
1023           "rdpru", "mcommit", "lwp", "fma4", "xop", "cx16", "syscall",
1024           "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5", "svme", "abm" and
1025           "padlock".  Note that rather than extending a basic instruction
1026           set, the extension mnemonics starting with "no" revoke the
1027           respective functionality.
1028
1029           When the ".arch" directive is used with -march, the ".arch"
1030           directive will take precedent.
1031
1032       -mtune=CPU
1033           This option specifies a processor to optimize for. When used in
1034           conjunction with the -march option, only instructions of the
1035           processor specified by the -march option will be generated.
1036
1037           Valid CPU values are identical to the processor list of -march=CPU.
1038
1039       -msse2avx
1040           This option specifies that the assembler should encode SSE
1041           instructions with VEX prefix.
1042
1043       -msse-check=none
1044       -msse-check=warning
1045       -msse-check=error
1046           These options control if the assembler should check SSE
1047           instructions.  -msse-check=none will make the assembler not to
1048           check SSE instructions,  which is the default.  -msse-check=warning
1049           will make the assembler issue a warning for any SSE instruction.
1050           -msse-check=error will make the assembler issue an error for any
1051           SSE instruction.
1052
1053       -mavxscalar=128
1054       -mavxscalar=256
1055           These options control how the assembler should encode scalar AVX
1056           instructions.  -mavxscalar=128 will encode scalar AVX instructions
1057           with 128bit vector length, which is the default.  -mavxscalar=256
1058           will encode scalar AVX instructions with 256bit vector length.
1059
1060           WARNING: Don't use this for production code - due to CPU errata the
1061           resulting code may not work on certain models.
1062
1063       -mvexwig=0
1064       -mvexwig=1
1065           These options control how the assembler should encode VEX.W-ignored
1066           (WIG) VEX instructions.  -mvexwig=0 will encode WIG VEX
1067           instructions with vex.w = 0, which is the default.  -mvexwig=1 will
1068           encode WIG EVEX instructions with vex.w = 1.
1069
1070           WARNING: Don't use this for production code - due to CPU errata the
1071           resulting code may not work on certain models.
1072
1073       -mevexlig=128
1074       -mevexlig=256
1075       -mevexlig=512
1076           These options control how the assembler should encode length-
1077           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
1078           EVEX instructions with 128bit vector length, which is the default.
1079           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1080           with 256bit and 512bit vector length, respectively.
1081
1082       -mevexwig=0
1083       -mevexwig=1
1084           These options control how the assembler should encode w-ignored
1085           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
1086           instructions with evex.w = 0, which is the default.  -mevexwig=1
1087           will encode WIG EVEX instructions with evex.w = 1.
1088
1089       -mmnemonic=att
1090       -mmnemonic=intel
1091           This option specifies instruction mnemonic for matching
1092           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
1093           will take precedent.
1094
1095       -msyntax=att
1096       -msyntax=intel
1097           This option specifies instruction syntax when processing
1098           instructions.  The ".att_syntax" and ".intel_syntax" directives
1099           will take precedent.
1100
1101       -mnaked-reg
1102           This option specifies that registers don't require a % prefix.  The
1103           ".att_syntax" and ".intel_syntax" directives will take precedent.
1104
1105       -madd-bnd-prefix
1106           This option forces the assembler to add BND prefix to all branches,
1107           even if such prefix was not explicitly specified in the source
1108           code.
1109
1110       -mno-shared
1111           On ELF target, the assembler normally optimizes out non-PLT
1112           relocations against defined non-weak global branch targets with
1113           default visibility.  The -mshared option tells the assembler to
1114           generate code which may go into a shared library where all non-weak
1115           global branch targets with default visibility can be preempted.
1116           The resulting code is slightly bigger.  This option only affects
1117           the handling of branch instructions.
1118
1119       -mbig-obj
1120           On x86-64 PE/COFF target this option forces the use of big object
1121           file format, which allows more than 32768 sections.
1122
1123       -momit-lock-prefix=no
1124       -momit-lock-prefix=yes
1125           These options control how the assembler should encode lock prefix.
1126           This option is intended as a workaround for processors, that fail
1127           on lock prefix. This option can only be safely used with single-
1128           core, single-thread computers -momit-lock-prefix=yes will omit all
1129           lock prefixes.  -momit-lock-prefix=no will encode lock prefix as
1130           usual, which is the default.
1131
1132       -mfence-as-lock-add=no
1133       -mfence-as-lock-add=yes
1134           These options control how the assembler should encode lfence,
1135           mfence and sfence.  -mfence-as-lock-add=yes will encode lfence,
1136           mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1137           addl $0x0, (%esp) in 32-bit mode.  -mfence-as-lock-add=no will
1138           encode lfence, mfence and sfence as usual, which is the default.
1139
1140       -mrelax-relocations=no
1141       -mrelax-relocations=yes
1142           These options control whether the assembler should generate relax
1143           relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1144           and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1145           -mrelax-relocations=yes will generate relax relocations.
1146           -mrelax-relocations=no will not generate relax relocations.  The
1147           default can be controlled by a configure option
1148           --enable-x86-relax-relocations.
1149
1150       -malign-branch-boundary=NUM
1151           This option controls how the assembler should align branches with
1152           segment prefixes or NOP.  NUM must be a power of 2.  It should be 0
1153           or no less than 16.  Branches will be aligned within NUM byte
1154           boundary.  -malign-branch-boundary=0, which is the default, doesn't
1155           align branches.
1156
1157       -malign-branch=TYPE[+TYPE...]
1158           This option specifies types of branches to align. TYPE is
1159           combination of jcc, which aligns conditional jumps, fused, which
1160           aligns fused conditional jumps, jmp, which aligns unconditional
1161           jumps, call which aligns calls, ret, which aligns rets, indirect,
1162           which aligns indirect jumps and calls.  The default is
1163           -malign-branch=jcc+fused+jmp.
1164
1165       -malign-branch-prefix-size=NUM
1166           This option specifies the maximum number of prefixes on an
1167           instruction to align branches.  NUM should be between 0 and 5.  The
1168           default NUM is 5.
1169
1170       -mbranches-within-32B-boundaries
1171           This option aligns conditional jumps, fused conditional jumps and
1172           unconditional jumps within 32 byte boundary with up to 5 segment
1173           prefixes on an instruction.  It is equivalent to
1174           -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1175           -malign-branch-prefix-size=5.  The default doesn't align branches.
1176
1177       -mx86-used-note=no
1178       -mx86-used-note=yes
1179           These options control whether the assembler should generate
1180           GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1181           property notes.  The default can be controlled by the
1182           --enable-x86-used-note configure option.
1183
1184       -mevexrcig=rne
1185       -mevexrcig=rd
1186       -mevexrcig=ru
1187       -mevexrcig=rz
1188           These options control how the assembler should encode SAE-only EVEX
1189           instructions.  -mevexrcig=rne will encode RC bits of EVEX
1190           instruction with 00, which is the default.  -mevexrcig=rd,
1191           -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1192           instructions with 01, 10 and 11 RC bits, respectively.
1193
1194       -mamd64
1195       -mintel64
1196           This option specifies that the assembler should accept only AMD64
1197           or Intel64 ISA in 64-bit mode.  The default is to accept both.
1198
1199       -O0 | -O | -O1 | -O2 | -Os
1200           Optimize instruction encoding with smaller instruction size.  -O
1201           and -O1 encode 64-bit register load instructions with 64-bit
1202           immediate as 32-bit register load instructions with 31-bit or
1203           32-bits immediates, encode 64-bit register clearing instructions
1204           with 32-bit register clearing instructions, encode 256-bit/512-bit
1205           VEX/EVEX vector register clearing instructions with 128-bit VEX
1206           vector register clearing instructions, encode 128-bit/256-bit EVEX
1207           vector register load/store instructions with VEX vector register
1208           load/store instructions, and encode 128-bit/256-bit EVEX packed
1209           integer logical instructions with 128-bit/256-bit VEX packed
1210           integer logical.
1211
1212           -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1213           vector register clearing instructions with 128-bit EVEX vector
1214           register clearing instructions.  In 64-bit mode VEX encoded
1215           instructions with commutative source operands will also have their
1216           source operands swapped if this allows using the 2-byte VEX prefix
1217           form instead of the 3-byte one.  Certain forms of AND as well as OR
1218           with the same (register) operand specified twice will also be
1219           changed to TEST.
1220
1221           -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1222           64-bit register tests with immediate as 8-bit register test with
1223           immediate.  -O0 turns off this optimization.
1224
1225       The following options are available when as is configured for the
1226       Ubicom IP2K series.
1227
1228       -mip2022ext
1229           Specifies that the extended IP2022 instructions are allowed.
1230
1231       -mip2022
1232           Restores the default behaviour, which restricts the permitted
1233           instructions to just the basic IP2022 ones.
1234
1235       The following options are available when as is configured for the
1236       Renesas M32C and M16C processors.
1237
1238       -m32c
1239           Assemble M32C instructions.
1240
1241       -m16c
1242           Assemble M16C instructions (the default).
1243
1244       -relax
1245           Enable support for link-time relaxations.
1246
1247       -h-tick-hex
1248           Support H'00 style hex constants in addition to 0x00 style.
1249
1250       The following options are available when as is configured for the
1251       Renesas M32R (formerly Mitsubishi M32R) series.
1252
1253       --m32rx
1254           Specify which processor in the M32R family is the target.  The
1255           default is normally the M32R, but this option changes it to the
1256           M32RX.
1257
1258       --warn-explicit-parallel-conflicts or --Wp
1259           Produce warning messages when questionable parallel constructs are
1260           encountered.
1261
1262       --no-warn-explicit-parallel-conflicts or --Wnp
1263           Do not produce warning messages when questionable parallel
1264           constructs are encountered.
1265
1266       The following options are available when as is configured for the
1267       Motorola 68000 series.
1268
1269       -l  Shorten references to undefined symbols, to one word instead of
1270           two.
1271
1272       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1273       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1274       | -m68333 | -m68340 | -mcpu32 | -m5200
1275           Specify what processor in the 68000 family is the target.  The
1276           default is normally the 68020, but this can be changed at
1277           configuration time.
1278
1279       -m68881 | -m68882 | -mno-68881 | -mno-68882
1280           The target machine does (or does not) have a floating-point
1281           coprocessor.  The default is to assume a coprocessor for 68020,
1282           68030, and cpu32.  Although the basic 68000 is not compatible with
1283           the 68881, a combination of the two can be specified, since it's
1284           possible to do emulation of the coprocessor instructions with the
1285           main processor.
1286
1287       -m68851 | -mno-68851
1288           The target machine does (or does not) have a memory-management unit
1289           coprocessor.  The default is to assume an MMU for 68020 and up.
1290
1291       The following options are available when as is configured for an Altera
1292       Nios II processor.
1293
1294       -relax-section
1295           Replace identified out-of-range branches with PC-relative "jmp"
1296           sequences when possible.  The generated code sequences are suitable
1297           for use in position-independent code, but there is a practical
1298           limit on the extended branch range because of the length of the
1299           sequences.  This option is the default.
1300
1301       -relax-all
1302           Replace branch instructions not determinable to be in range and all
1303           call instructions with "jmp" and "callr" sequences (respectively).
1304           This option generates absolute relocations against the target
1305           symbols and is not appropriate for position-independent code.
1306
1307       -no-relax
1308           Do not replace any branches or calls.
1309
1310       -EB Generate big-endian output.
1311
1312       -EL Generate little-endian output.  This is the default.
1313
1314       -march=architecture
1315           This option specifies the target architecture.  The assembler
1316           issues an error message if an attempt is made to assemble an
1317           instruction which will not execute on the target architecture.  The
1318           following architecture names are recognized: "r1", "r2".  The
1319           default is "r1".
1320
1321       The following options are available when as is configured for a PRU
1322       processor.
1323
1324       -mlink-relax
1325           Assume that LD would optimize LDI32 instructions by checking the
1326           upper 16 bits of the expression. If they are all zeros, then LD
1327           would shorten the LDI32 instruction to a single LDI. In such case
1328           "as" will output DIFF relocations for diff expressions.
1329
1330       -mno-link-relax
1331           Assume that LD would not optimize LDI32 instructions. As a
1332           consequence, DIFF relocations will not be emitted.
1333
1334       -mno-warn-regname-label
1335           Do not warn if a label name matches a register name. Usually
1336           assembler programmers will want this warning to be emitted. C
1337           compilers may want to turn this off.
1338
1339       The following options are available when as is configured for a MIPS
1340       processor.
1341
1342       -G num
1343           This option sets the largest size of an object that can be
1344           referenced implicitly with the "gp" register.  It is only accepted
1345           for targets that use ECOFF format, such as a DECstation running
1346           Ultrix.  The default value is 8.
1347
1348       -EB Generate "big endian" format output.
1349
1350       -EL Generate "little endian" format output.
1351
1352       -mips1
1353       -mips2
1354       -mips3
1355       -mips4
1356       -mips5
1357       -mips32
1358       -mips32r2
1359       -mips32r3
1360       -mips32r5
1361       -mips32r6
1362       -mips64
1363       -mips64r2
1364       -mips64r3
1365       -mips64r5
1366       -mips64r6
1367           Generate code for a particular MIPS Instruction Set Architecture
1368           level.  -mips1 is an alias for -march=r3000, -mips2 is an alias for
1369           -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1370           alias for -march=r8000.  -mips5, -mips32, -mips32r2, -mips32r3,
1371           -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1372           -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1373           MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1374           MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1375           Release 6 ISA processors, respectively.
1376
1377       -march=cpu
1378           Generate code for a particular MIPS CPU.
1379
1380       -mtune=cpu
1381           Schedule and tune for a particular MIPS CPU.
1382
1383       -mfix7000
1384       -mno-fix7000
1385           Cause nops to be inserted if the read of the destination register
1386           of an mfhi or mflo instruction occurs in the following two
1387           instructions.
1388
1389       -mfix-rm7000
1390       -mno-fix-rm7000
1391           Cause nops to be inserted if a dmult or dmultu instruction is
1392           followed by a load instruction.
1393
1394       -mfix-r5900
1395       -mno-fix-r5900
1396           Do not attempt to schedule the preceding instruction into the delay
1397           slot of a branch instruction placed at the end of a short loop of
1398           six instructions or fewer and always schedule a "nop" instruction
1399           there instead.  The short loop bug under certain conditions causes
1400           loops to execute only once or twice, due to a hardware bug in the
1401           R5900 chip.
1402
1403       -mdebug
1404       -no-mdebug
1405           Cause stabs-style debugging output to go into an ECOFF-style
1406           .mdebug section instead of the standard ELF .stabs sections.
1407
1408       -mpdr
1409       -mno-pdr
1410           Control generation of ".pdr" sections.
1411
1412       -mgp32
1413       -mfp32
1414           The register sizes are normally inferred from the ISA and ABI, but
1415           these flags force a certain group of registers to be treated as 32
1416           bits wide at all times.  -mgp32 controls the size of general-
1417           purpose registers and -mfp32 controls the size of floating-point
1418           registers.
1419
1420       -mgp64
1421       -mfp64
1422           The register sizes are normally inferred from the ISA and ABI, but
1423           these flags force a certain group of registers to be treated as 64
1424           bits wide at all times.  -mgp64 controls the size of general-
1425           purpose registers and -mfp64 controls the size of floating-point
1426           registers.
1427
1428       -mfpxx
1429           The register sizes are normally inferred from the ISA and ABI, but
1430           using this flag in combination with -mabi=32 enables an ABI variant
1431           which will operate correctly with floating-point registers which
1432           are 32 or 64 bits wide.
1433
1434       -modd-spreg
1435       -mno-odd-spreg
1436           Enable use of floating-point operations on odd-numbered single-
1437           precision registers when supported by the ISA.  -mfpxx implies
1438           -mno-odd-spreg, otherwise the default is -modd-spreg.
1439
1440       -mips16
1441       -no-mips16
1442           Generate code for the MIPS 16 processor.  This is equivalent to
1443           putting ".module mips16" at the start of the assembly file.
1444           -no-mips16 turns off this option.
1445
1446       -mmips16e2
1447       -mno-mips16e2
1448           Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is
1449           equivalent to putting ".module mips16e2" at the start of the
1450           assembly file.  -mno-mips16e2 turns off this option.
1451
1452       -mmicromips
1453       -mno-micromips
1454           Generate code for the microMIPS processor.  This is equivalent to
1455           putting ".module micromips" at the start of the assembly file.
1456           -mno-micromips turns off this option.  This is equivalent to
1457           putting ".module nomicromips" at the start of the assembly file.
1458
1459       -msmartmips
1460       -mno-smartmips
1461           Enables the SmartMIPS extension to the MIPS32 instruction set.
1462           This is equivalent to putting ".module smartmips" at the start of
1463           the assembly file.  -mno-smartmips turns off this option.
1464
1465       -mips3d
1466       -no-mips3d
1467           Generate code for the MIPS-3D Application Specific Extension.  This
1468           tells the assembler to accept MIPS-3D instructions.  -no-mips3d
1469           turns off this option.
1470
1471       -mdmx
1472       -no-mdmx
1473           Generate code for the MDMX Application Specific Extension.  This
1474           tells the assembler to accept MDMX instructions.  -no-mdmx turns
1475           off this option.
1476
1477       -mdsp
1478       -mno-dsp
1479           Generate code for the DSP Release 1 Application Specific Extension.
1480           This tells the assembler to accept DSP Release 1 instructions.
1481           -mno-dsp turns off this option.
1482
1483       -mdspr2
1484       -mno-dspr2
1485           Generate code for the DSP Release 2 Application Specific Extension.
1486           This option implies -mdsp.  This tells the assembler to accept DSP
1487           Release 2 instructions.  -mno-dspr2 turns off this option.
1488
1489       -mdspr3
1490       -mno-dspr3
1491           Generate code for the DSP Release 3 Application Specific Extension.
1492           This option implies -mdsp and -mdspr2.  This tells the assembler to
1493           accept DSP Release 3 instructions.  -mno-dspr3 turns off this
1494           option.
1495
1496       -mmsa
1497       -mno-msa
1498           Generate code for the MIPS SIMD Architecture Extension.  This tells
1499           the assembler to accept MSA instructions.  -mno-msa turns off this
1500           option.
1501
1502       -mxpa
1503       -mno-xpa
1504           Generate code for the MIPS eXtended Physical Address (XPA)
1505           Extension.  This tells the assembler to accept XPA instructions.
1506           -mno-xpa turns off this option.
1507
1508       -mmt
1509       -mno-mt
1510           Generate code for the MT Application Specific Extension.  This
1511           tells the assembler to accept MT instructions.  -mno-mt turns off
1512           this option.
1513
1514       -mmcu
1515       -mno-mcu
1516           Generate code for the MCU Application Specific Extension.  This
1517           tells the assembler to accept MCU instructions.  -mno-mcu turns off
1518           this option.
1519
1520       -mcrc
1521       -mno-crc
1522           Generate code for the MIPS cyclic redundancy check (CRC)
1523           Application Specific Extension.  This tells the assembler to accept
1524           CRC instructions.  -mno-crc turns off this option.
1525
1526       -mginv
1527       -mno-ginv
1528           Generate code for the Global INValidate (GINV) Application Specific
1529           Extension.  This tells the assembler to accept GINV instructions.
1530           -mno-ginv turns off this option.
1531
1532       -mloongson-mmi
1533       -mno-loongson-mmi
1534           Generate code for the Loongson MultiMedia extensions Instructions
1535           (MMI) Application Specific Extension.  This tells the assembler to
1536           accept MMI instructions.  -mno-loongson-mmi turns off this option.
1537
1538       -mloongson-cam
1539       -mno-loongson-cam
1540           Generate code for the Loongson Content Address Memory (CAM)
1541           instructions.  This tells the assembler to accept Loongson CAM
1542           instructions.  -mno-loongson-cam turns off this option.
1543
1544       -mloongson-ext
1545       -mno-loongson-ext
1546           Generate code for the Loongson EXTensions (EXT) instructions.  This
1547           tells the assembler to accept Loongson EXT instructions.
1548           -mno-loongson-ext turns off this option.
1549
1550       -mloongson-ext2
1551       -mno-loongson-ext2
1552           Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1553           This option implies -mloongson-ext.  This tells the assembler to
1554           accept Loongson EXT2 instructions.  -mno-loongson-ext2 turns off
1555           this option.
1556
1557       -minsn32
1558       -mno-insn32
1559           Only use 32-bit instruction encodings when generating code for the
1560           microMIPS processor.  This option inhibits the use of any 16-bit
1561           instructions.  This is equivalent to putting ".set insn32" at the
1562           start of the assembly file.  -mno-insn32 turns off this option.
1563           This is equivalent to putting ".set noinsn32" at the start of the
1564           assembly file.  By default -mno-insn32 is selected, allowing all
1565           instructions to be used.
1566
1567       --construct-floats
1568       --no-construct-floats
1569           The --no-construct-floats option disables the construction of
1570           double width floating point constants by loading the two halves of
1571           the value into the two single width floating point registers that
1572           make up the double width register.  By default --construct-floats
1573           is selected, allowing construction of these floating point
1574           constants.
1575
1576       --relax-branch
1577       --no-relax-branch
1578           The --relax-branch option enables the relaxation of out-of-range
1579           branches.  By default --no-relax-branch is selected, causing any
1580           out-of-range branches to produce an error.
1581
1582       -mignore-branch-isa
1583       -mno-ignore-branch-isa
1584           Ignore branch checks for invalid transitions between ISA modes.
1585           The semantics of branches does not provide for an ISA mode switch,
1586           so in most cases the ISA mode a branch has been encoded for has to
1587           be the same as the ISA mode of the branch's target label.
1588           Therefore GAS has checks implemented that verify in branch assembly
1589           that the two ISA modes match.  -mignore-branch-isa disables these
1590           checks.  By default -mno-ignore-branch-isa is selected, causing any
1591           invalid branch requiring a transition between ISA modes to produce
1592           an error.
1593
1594       -mnan=encoding
1595           Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1596           (-mnan=legacy) NaN encoding format.  The latter is the default.
1597
1598       --emulation=name
1599           This option was formerly used to switch between ELF and ECOFF
1600           output on targets like IRIX 5 that supported both.  MIPS ECOFF
1601           support was removed in GAS 2.24, so the option now serves little
1602           purpose.  It is retained for backwards compatibility.
1603
1604           The available configuration names are: mipself, mipslelf and
1605           mipsbelf.  Choosing mipself now has no effect, since the output is
1606           always ELF.  mipslelf and mipsbelf select little- and big-endian
1607           output respectively, but -EL and -EB are now the preferred options
1608           instead.
1609
1610       -nocpp
1611           as ignores this option.  It is accepted for compatibility with the
1612           native tools.
1613
1614       --trap
1615       --no-trap
1616       --break
1617       --no-break
1618           Control how to deal with multiplication overflow and division by
1619           zero.  --trap or --no-break (which are synonyms) take a trap
1620           exception (and only work for Instruction Set Architecture level 2
1621           and higher); --break or --no-trap (also synonyms, and the default)
1622           take a break exception.
1623
1624       -n  When this option is used, as will issue a warning every time it
1625           generates a nop instruction from a macro.
1626
1627       The following options are available when as is configured for a Meta
1628       processor.
1629
1630       "-mcpu=metac11"
1631           Generate code for Meta 1.1.
1632
1633       "-mcpu=metac12"
1634           Generate code for Meta 1.2.
1635
1636       "-mcpu=metac21"
1637           Generate code for Meta 2.1.
1638
1639       "-mfpu=metac21"
1640           Allow code to use FPU hardware of Meta 2.1.
1641
1642       See the info pages for documentation of the MMIX-specific options.
1643
1644       The following options are available when as is configured for a NDS32
1645       processor.
1646
1647       "-O1"
1648           Optimize for performance.
1649
1650       "-Os"
1651           Optimize for space.
1652
1653       "-EL"
1654           Produce little endian data output.
1655
1656       "-EB"
1657           Produce little endian data output.
1658
1659       "-mpic"
1660           Generate PIC.
1661
1662       "-mno-fp-as-gp-relax"
1663           Suppress fp-as-gp relaxation for this file.
1664
1665       "-mb2bb-relax"
1666           Back-to-back branch optimization.
1667
1668       "-mno-all-relax"
1669           Suppress all relaxation for this file.
1670
1671       "-march=<arch name>"
1672           Assemble for architecture <arch name> which could be v3, v3j, v3m,
1673           v3f, v3s, v2, v2j, v2f, v2s.
1674
1675       "-mbaseline=<baseline>"
1676           Assemble for baseline <baseline> which could be v2, v3, v3m.
1677
1678       "-mfpu-freg=FREG"
1679           Specify a FPU configuration.
1680
1681           "0      8 SP /  4 DP registers"
1682           "1     16 SP /  8 DP registers"
1683           "2     32 SP / 16 DP registers"
1684           "3     32 SP / 32 DP registers"
1685       "-mabi=abi"
1686           Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1687
1688       "-m[no-]mac"
1689           Enable/Disable Multiply instructions support.
1690
1691       "-m[no-]div"
1692           Enable/Disable Divide instructions support.
1693
1694       "-m[no-]16bit-ext"
1695           Enable/Disable 16-bit extension
1696
1697       "-m[no-]dx-regs"
1698           Enable/Disable d0/d1 registers
1699
1700       "-m[no-]perf-ext"
1701           Enable/Disable Performance extension
1702
1703       "-m[no-]perf2-ext"
1704           Enable/Disable Performance extension 2
1705
1706       "-m[no-]string-ext"
1707           Enable/Disable String extension
1708
1709       "-m[no-]reduced-regs"
1710           Enable/Disable Reduced Register configuration (GPR16) option
1711
1712       "-m[no-]audio-isa-ext"
1713           Enable/Disable AUDIO ISA extension
1714
1715       "-m[no-]fpu-sp-ext"
1716           Enable/Disable FPU SP extension
1717
1718       "-m[no-]fpu-dp-ext"
1719           Enable/Disable FPU DP extension
1720
1721       "-m[no-]fpu-fma"
1722           Enable/Disable FPU fused-multiply-add instructions
1723
1724       "-mall-ext"
1725           Turn on all extensions and instructions support
1726
1727       The following options are available when as is configured for a PowerPC
1728       processor.
1729
1730       -a32
1731           Generate ELF32 or XCOFF32.
1732
1733       -a64
1734           Generate ELF64 or XCOFF64.
1735
1736       -K PIC
1737           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1738
1739       -mpwrx | -mpwr2
1740           Generate code for POWER/2 (RIOS2).
1741
1742       -mpwr
1743           Generate code for POWER (RIOS1)
1744
1745       -m601
1746           Generate code for PowerPC 601.
1747
1748       -mppc, -mppc32, -m603, -m604
1749           Generate code for PowerPC 603/604.
1750
1751       -m403, -m405
1752           Generate code for PowerPC 403/405.
1753
1754       -m440
1755           Generate code for PowerPC 440.  BookE and some 405 instructions.
1756
1757       -m464
1758           Generate code for PowerPC 464.
1759
1760       -m476
1761           Generate code for PowerPC 476.
1762
1763       -m7400, -m7410, -m7450, -m7455
1764           Generate code for PowerPC 7400/7410/7450/7455.
1765
1766       -m750cl, -mgekko, -mbroadway
1767           Generate code for PowerPC 750CL/Gekko/Broadway.
1768
1769       -m821, -m850, -m860
1770           Generate code for PowerPC 821/850/860.
1771
1772       -mppc64, -m620
1773           Generate code for PowerPC 620/625/630.
1774
1775       -me500, -me500x2
1776           Generate code for Motorola e500 core complex.
1777
1778       -me500mc
1779           Generate code for Freescale e500mc core complex.
1780
1781       -me500mc64
1782           Generate code for Freescale e500mc64 core complex.
1783
1784       -me5500
1785           Generate code for Freescale e5500 core complex.
1786
1787       -me6500
1788           Generate code for Freescale e6500 core complex.
1789
1790       -mspe
1791           Generate code for Motorola SPE instructions.
1792
1793       -mspe2
1794           Generate code for Freescale SPE2 instructions.
1795
1796       -mtitan
1797           Generate code for AppliedMicro Titan core complex.
1798
1799       -mppc64bridge
1800           Generate code for PowerPC 64, including bridge insns.
1801
1802       -mbooke
1803           Generate code for 32-bit BookE.
1804
1805       -ma2
1806           Generate code for A2 architecture.
1807
1808       -me300
1809           Generate code for PowerPC e300 family.
1810
1811       -maltivec
1812           Generate code for processors with AltiVec instructions.
1813
1814       -mvle
1815           Generate code for Freescale PowerPC VLE instructions.
1816
1817       -mvsx
1818           Generate code for processors with Vector-Scalar (VSX) instructions.
1819
1820       -mhtm
1821           Generate code for processors with Hardware Transactional Memory
1822           instructions.
1823
1824       -mpower4, -mpwr4
1825           Generate code for Power4 architecture.
1826
1827       -mpower5, -mpwr5, -mpwr5x
1828           Generate code for Power5 architecture.
1829
1830       -mpower6, -mpwr6
1831           Generate code for Power6 architecture.
1832
1833       -mpower7, -mpwr7
1834           Generate code for Power7 architecture.
1835
1836       -mpower8, -mpwr8
1837           Generate code for Power8 architecture.
1838
1839       -mpower9, -mpwr9
1840           Generate code for Power9 architecture.
1841
1842       -mcell
1843       -mcell
1844           Generate code for Cell Broadband Engine architecture.
1845
1846       -mcom
1847           Generate code Power/PowerPC common instructions.
1848
1849       -many
1850           Generate code for any architecture (PWR/PWRX/PPC).
1851
1852       -mregnames
1853           Allow symbolic names for registers.
1854
1855       -mno-regnames
1856           Do not allow symbolic names for registers.
1857
1858       -mrelocatable
1859           Support for GCC's -mrelocatable option.
1860
1861       -mrelocatable-lib
1862           Support for GCC's -mrelocatable-lib option.
1863
1864       -memb
1865           Set PPC_EMB bit in ELF flags.
1866
1867       -mlittle, -mlittle-endian, -le
1868           Generate code for a little endian machine.
1869
1870       -mbig, -mbig-endian, -be
1871           Generate code for a big endian machine.
1872
1873       -msolaris
1874           Generate code for Solaris.
1875
1876       -mno-solaris
1877           Do not generate code for Solaris.
1878
1879       -nops=count
1880           If an alignment directive inserts more than count nops, put a
1881           branch at the beginning to skip execution of the nops.
1882
1883       The following options are available when as is configured for a RISC-V
1884       processor.
1885
1886       -fpic
1887       -fPIC
1888           Generate position-independent code
1889
1890       -fno-pic
1891           Don't generate position-independent code (default)
1892
1893       -march=ISA
1894           Select the base isa, as specified by ISA.  For example
1895           -march=rv32ima.
1896
1897       -mabi=ABI
1898           Selects the ABI, which is either "ilp32" or "lp64", optionally
1899           followed by "f", "d", or "q" to indicate single-precision, double-
1900           precision, or quad-precision floating-point calling convention, or
1901           none to indicate the soft-float calling convention.  Also, "ilp32"
1902           can optionally be followed by "e" to indicate the RVE ABI, which is
1903           always soft-float.
1904
1905       -mrelax
1906           Take advantage of linker relaxations to reduce the number of
1907           instructions required to materialize symbol addresses. (default)
1908
1909       -mno-relax
1910           Don't do linker relaxations.
1911
1912       See the info pages for documentation of the RX-specific options.
1913
1914       The following options are available when as is configured for the s390
1915       processor family.
1916
1917       -m31
1918       -m64
1919           Select the word size, either 31/32 bits or 64 bits.
1920
1921       -mesa
1922       -mzarch
1923           Select the architecture mode, either the Enterprise System
1924           Architecture (esa) or the z/Architecture mode (zarch).
1925
1926       -march=processor
1927           Specify which s390 processor variant is the target, g5 (or arch3),
1928           g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
1929           (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
1930           z14 (or arch12), or z15 (or arch13).
1931
1932       -mregnames
1933       -mno-regnames
1934           Allow or disallow symbolic names for registers.
1935
1936       -mwarn-areg-zero
1937           Warn whenever the operand for a base or index register has been
1938           specified but evaluates to zero.
1939
1940       The following options are available when as is configured for a
1941       TMS320C6000 processor.
1942
1943       -march=arch
1944           Enable (only) instructions from architecture arch.  By default, all
1945           instructions are permitted.
1946
1947           The following values of arch are accepted: "c62x", "c64x", "c64x+",
1948           "c67x", "c67x+", "c674x".
1949
1950       -mdsbt
1951       -mno-dsbt
1952           The -mdsbt option causes the assembler to generate the
1953           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
1954           code is using DSBT addressing.  The -mno-dsbt option, the default,
1955           causes the tag to have a value of 0, indicating that the code does
1956           not use DSBT addressing.  The linker will emit a warning if objects
1957           of different type (DSBT and non-DSBT) are linked together.
1958
1959       -mpid=no
1960       -mpid=near
1961       -mpid=far
1962           The -mpid= option causes the assembler to generate the
1963           "Tag_ABI_PID" attribute with a value indicating the form of data
1964           addressing used by the code.  -mpid=no, the default, indicates
1965           position-dependent data addressing, -mpid=near indicates position-
1966           independent addressing with GOT accesses using near DP addressing,
1967           and -mpid=far indicates position-independent addressing with GOT
1968           accesses using far DP addressing.  The linker will emit a warning
1969           if objects built with different settings of this option are linked
1970           together.
1971
1972       -mpic
1973       -mno-pic
1974           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
1975           attribute with a value of 1, indicating that the code is using
1976           position-independent code addressing,  The "-mno-pic" option, the
1977           default, causes the tag to have a value of 0, indicating position-
1978           dependent code addressing.  The linker will emit a warning if
1979           objects of different type (position-dependent and position-
1980           independent) are linked together.
1981
1982       -mbig-endian
1983       -mlittle-endian
1984           Generate code for the specified endianness.  The default is little-
1985           endian.
1986
1987       The following options are available when as is configured for a TILE-Gx
1988       processor.
1989
1990       -m32 | -m64
1991           Select the word size, either 32 bits or 64 bits.
1992
1993       -EB | -EL
1994           Select the endianness, either big-endian (-EB) or little-endian
1995           (-EL).
1996
1997       The following option is available when as is configured for a Visium
1998       processor.
1999
2000       -mtune=arch
2001           This option specifies the target architecture.  If an attempt is
2002           made to assemble an instruction that will not execute on the target
2003           architecture, the assembler will issue an error message.
2004
2005           The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2006
2007       The following options are available when as is configured for an Xtensa
2008       processor.
2009
2010       --text-section-literals | --no-text-section-literals
2011           Control the treatment of literal pools.  The default is
2012           --no-text-section-literals, which places literals in separate
2013           sections in the output file.  This allows the literal pool to be
2014           placed in a data RAM/ROM.  With --text-section-literals, the
2015           literals are interspersed in the text section in order to keep them
2016           as close as possible to their references.  This may be necessary
2017           for large assembly files, where the literals would otherwise be out
2018           of range of the "L32R" instructions in the text section.  Literals
2019           are grouped into pools following ".literal_position" directives or
2020           preceding "ENTRY" instructions.  These options only affect literals
2021           referenced via PC-relative "L32R" instructions; literals for
2022           absolute mode "L32R" instructions are handled separately.
2023
2024       --auto-litpools | --no-auto-litpools
2025           Control the treatment of literal pools.  The default is
2026           --no-auto-litpools, which in the absence of --text-section-literals
2027           places literals in separate sections in the output file.  This
2028           allows the literal pool to be placed in a data RAM/ROM.  With
2029           --auto-litpools, the literals are interspersed in the text section
2030           in order to keep them as close as possible to their references,
2031           explicit ".literal_position" directives are not required.  This may
2032           be necessary for very large functions, where single literal pool at
2033           the beginning of the function may not be reachable by "L32R"
2034           instructions at the end.  These options only affect literals
2035           referenced via PC-relative "L32R" instructions; literals for
2036           absolute mode "L32R" instructions are handled separately.  When
2037           used together with --text-section-literals, --auto-litpools takes
2038           precedence.
2039
2040       --absolute-literals | --no-absolute-literals
2041           Indicate to the assembler whether "L32R" instructions use absolute
2042           or PC-relative addressing.  If the processor includes the absolute
2043           addressing option, the default is to use absolute "L32R"
2044           relocations.  Otherwise, only the PC-relative "L32R" relocations
2045           can be used.
2046
2047       --target-align | --no-target-align
2048           Enable or disable automatic alignment to reduce branch penalties at
2049           some expense in code size.    This optimization is enabled by
2050           default.  Note that the assembler will always align instructions
2051           like "LOOP" that have fixed alignment requirements.
2052
2053       --longcalls | --no-longcalls
2054           Enable or disable transformation of call instructions to allow
2055           calls across a greater range of addresses.    This option should be
2056           used when call targets can potentially be out of range.  It may
2057           degrade both code size and performance, but the linker can
2058           generally optimize away the unnecessary overhead when a call ends
2059           up within range.  The default is --no-longcalls.
2060
2061       --transform | --no-transform
2062           Enable or disable all assembler transformations of Xtensa
2063           instructions, including both relaxation and optimization.  The
2064           default is --transform; --no-transform should only be used in the
2065           rare cases when the instructions must be exactly as specified in
2066           the assembly source.  Using --no-transform causes out of range
2067           instruction operands to be errors.
2068
2069       --rename-section oldname=newname
2070           Rename the oldname section to newname.  This option can be used
2071           multiple times to rename multiple sections.
2072
2073       --trampolines | --no-trampolines
2074           Enable or disable transformation of jump instructions to allow
2075           jumps across a greater range of addresses.    This option should be
2076           used when jump targets can potentially be out of range.  In the
2077           absence of such jumps this option does not affect code size or
2078           performance.  The default is --trampolines.
2079
2080       The following options are available when as is configured for an Z80
2081       processor.
2082
2083       @chapter Z80 Dependent Features
2084
2085   Command-line Options
2086       -z80
2087           Produce code for the Z80 processor. By default accepted
2088           undocumented operations with halves of index registers ("IXL",
2089           "IXH", "IYL", "IYH") and instuction "IN F,(C)". Other useful
2090           undocumented instructions produces warnings. Undocumented
2091           instructions may not work on some CPUs, use them on your own risk.
2092
2093       -r800
2094           Produce code for the R800 processor.
2095
2096       -z180
2097           Produce code for the Z180 processor.
2098
2099       -ez80
2100           Produce code for the eZ80 processor in Z80 memory mode by default.
2101
2102       -ez80-adl
2103           Produce code for the eZ80 processor in ADL memory mode by default.
2104
2105       -local-prefix=prefix
2106           Mark all labels with specified prefix as local. But such label can
2107           be marked global explicitly in the code. This option do not change
2108           default local label prefix ".L", it is just adds new one.
2109
2110       -colonless
2111           Accept colonless labels. All names at line begin are treated as
2112           labels.
2113
2114       -sdcc
2115           Accept assembler code produced by SDCC.
2116
2117       -fp-s=FORMAT
2118           Single precision floating point numbers format. Default: ieee754
2119           (32 bit).
2120
2121       -fp-d=FORMAT
2122           Double precision floating point numbers format. Default: ieee754
2123           (64 bit).
2124
2125       -strict
2126           Accept documented instructions only.
2127
2128       -full
2129           Accept all known Z80 instructions.
2130
2131       -with-inst=INST[,...]
2132       -Wnins INST[,...]
2133           Enable specified undocumented instruction(s).
2134
2135       -without-inst=INST[,...]
2136       -Fins INST[,...]
2137           Disable specified undocumented instruction(s).
2138
2139       -ignore-undocumented-instructions
2140       -Wnud
2141           Silently assemble undocumented Z80-instructions that have been
2142           adopted as documented R800-instructions .
2143
2144       -ignore-unportable-instructions
2145       -Wnup
2146           Silently assemble all undocumented Z80-instructions.
2147
2148       -warn-undocumented-instructions
2149       -Wud
2150           Issue warnings for undocumented Z80-instructions that work on R800,
2151           do not assemble other undocumented instructions without warning.
2152
2153       -warn-unportable-instructions
2154       -Wup
2155           Issue warnings for other undocumented Z80-instructions, do not
2156           treat any undocumented instructions as errors.
2157
2158       -forbid-undocumented-instructions
2159       -Fud
2160           Treat all undocumented z80-instructions as errors.
2161
2162       -forbid-unportable-instructions
2163       -Fup
2164           Treat undocumented z80-instructions that do not work on R800 as
2165           errors.
2166

SEE ALSO

2168       gcc(1), ld(1), and the Info entries for binutils and ld.
2169
2171       Copyright (c) 1991-2020 Free Software Foundation, Inc.
2172
2173       Permission is granted to copy, distribute and/or modify this document
2174       under the terms of the GNU Free Documentation License, Version 1.3 or
2175       any later version published by the Free Software Foundation; with no
2176       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2177       Texts.  A copy of the license is included in the section entitled "GNU
2178       Free Documentation License".
2179
2180
2181
2182binutils-2.34                     2020-02-27                             AS(1)
Impressum