1AS(1)                        GNU Development Tools                       AS(1)
2
3
4

NAME

6       AS - the portable GNU assembler.
7

SYNOPSIS

9       as [-a[cdghlns][=file]]
10        [--alternate]
11        [--compress-debug-sections] [--nocompress-debug-sections]
12        [-D]
13        [--dump-config]
14        [--debug-prefix-map old=new]
15        [--defsym sym=val]
16        [--elf-stt-common=[no|yes]]
17        [--emulation=name]
18        [-f]
19        [-g] [--gstabs] [--gstabs+]
20        [--gdwarf-<N>] [--gdwarf-sections]
21        [--gdwarf-cie-version=VERSION]
22        [--generate-missing-build-notes=[no|yes]]
23        [--gsframe]
24        [--hash-size=N]
25        [--help] [--target-help]
26        [-I dir]
27        [-J]
28        [-K]
29        [--keep-locals]
30        [-L]
31        [--listing-lhs-width=NUM]
32        [--listing-lhs-width2=NUM]
33        [--listing-rhs-width=NUM]
34        [--listing-cont-lines=NUM]
35        [--multibyte-handling=[allow|warn|warn-sym-only]]
36        [--no-pad-sections]
37        [-o objfile] [-R]
38        [--sectname-subst]
39        [--size-check=[error|warning]]
40        [--statistics]
41        [-v] [-version] [--version]
42        [-W] [--warn] [--fatal-warnings] [-w] [-x]
43        [-Z] [@FILE]
44        [target-options]
45        [--|files ...]
46

TARGET

48       Target AArch64 options:
49          [-EB|-EL]
50          [-mabi=ABI]
51
52       Target Alpha options:
53          [-mcpu]
54          [-mdebug | -no-mdebug]
55          [-replace | -noreplace]
56          [-relax] [-g] [-Gsize]
57          [-F] [-32addr]
58
59       Target ARC options:
60          [-mcpu=cpu]
61          [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
62          [-mcode-density]
63          [-mrelax]
64          [-EB|-EL]
65
66       Target ARM options:
67          [-mcpu=processor[+extension...]]
68          [-march=architecture[+extension...]]
69          [-mfpu=floating-point-format]
70          [-mfloat-abi=abi]
71          [-meabi=ver]
72          [-mthumb]
73          [-EB|-EL]
74          [-mapcs-32|-mapcs-26|-mapcs-float|
75           -mapcs-reentrant]
76          [-mthumb-interwork] [-k]
77
78       Target Blackfin options:
79          [-mcpu=processor[-sirevision]]
80          [-mfdpic]
81          [-mno-fdpic]
82          [-mnopic]
83
84       Target BPF options:
85          [-EL] [-EB]
86
87       Target CRIS options:
88          [--underscore | --no-underscore]
89          [--pic] [-N]
90          [--emulation=criself | --emulation=crisaout]
91          [--march=v0_v10 | --march=v10 | --march=v32 |
92       --march=common_v10_v32]
93
94       Target C-SKY options:
95          [-march=arch] [-mcpu=cpu]
96          [-EL] [-mlittle-endian] [-EB] [-mbig-endian]
97          [-fpic] [-pic]
98          [-mljump] [-mno-ljump]
99          [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]
100          [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]
101          [-mnolrw ] [-mno-lrw]
102          [-melrw] [-mno-elrw]
103          [-mlaf ] [-mliterals-after-func]
104          [-mno-laf] [-mno-literals-after-func]
105          [-mlabr] [-mliterals-after-br]
106          [-mno-labr] [-mnoliterals-after-br]
107          [-mistack] [-mno-istack]
108          [-mhard-float] [-mmp] [-mcp] [-mcache]
109          [-msecurity] [-mtrust]
110          [-mdsp] [-medsp] [-mvdsp]
111
112       Target D10V options:
113          [-O]
114
115       Target D30V options:
116          [-O|-n|-N]
117
118       Target EPIPHANY options:
119          [-mepiphany|-mepiphany16]
120
121       Target H8/300 options:
122          [-h-tick-hex]
123
124       Target i386 options:
125          [--32|--x32|--64] [-n]
126          [-march=CPU[+EXTENSION...]] [-mtune=CPU]
127
128       Target IA-64 options:
129          [-mconstant-gp|-mauto-pic]
130          [-milp32|-milp64|-mlp64|-mp64]
131          [-mle|mbe]
132          [-mtune=itanium1|-mtune=itanium2]
133          [-munwind-check=warning|-munwind-check=error]
134          [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
135          [-x|-xexplicit] [-xauto] [-xdebug]
136
137       Target IP2K options:
138          [-mip2022|-mip2022ext]
139
140       Target M32C options:
141          [-m32c|-m16c] [-relax] [-h-tick-hex]
142
143       Target M32R options:
144          [--m32rx|--[no-]warn-explicit-parallel-conflicts|
145          --W[n]p]
146
147       Target M680X0 options:
148          [-l] [-m68000|-m68010|-m68020|...]
149
150       Target M68HC11 options:
151          [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
152          [-mshort|-mlong]
153          [-mshort-double|-mlong-double]
154          [--force-long-branches] [--short-branches]
155          [--strict-direct-mode] [--print-insn-syntax]
156          [--print-opcodes] [--generate-example]
157
158       Target MCORE options:
159          [-jsri2bsr] [-sifilter] [-relax]
160          [-mcpu=[210|340]]
161
162       Target Meta options:
163          [-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:
164
165       Target MIPS options:
166          [-nocpp] [-EL] [-EB] [-O[optimization level]]
167          [-g[debug level]] [-G num] [-KPIC] [-call_shared]
168          [-non_shared] [-xgot [-mvxworks-pic]
169          [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
170          [-mfp64] [-mgp64] [-mfpxx]
171          [-modd-spreg] [-mno-odd-spreg]
172          [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
173          [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
174          [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
175          [-mips64r3] [-mips64r5] [-mips64r6]
176          [-construct-floats] [-no-construct-floats]
177          [-mignore-branch-isa] [-mno-ignore-branch-isa]
178          [-mnan=encoding]
179          [-trap] [-no-break] [-break] [-no-trap]
180          [-mips16] [-no-mips16]
181          [-mmips16e2] [-mno-mips16e2]
182          [-mmicromips] [-mno-micromips]
183          [-msmartmips] [-mno-smartmips]
184          [-mips3d] [-no-mips3d]
185          [-mdmx] [-no-mdmx]
186          [-mdsp] [-mno-dsp]
187          [-mdspr2] [-mno-dspr2]
188          [-mdspr3] [-mno-dspr3]
189          [-mmsa] [-mno-msa]
190          [-mxpa] [-mno-xpa]
191          [-mmt] [-mno-mt]
192          [-mmcu] [-mno-mcu]
193          [-mcrc] [-mno-crc]
194          [-mginv] [-mno-ginv]
195          [-mloongson-mmi] [-mno-loongson-mmi]
196          [-mloongson-cam] [-mno-loongson-cam]
197          [-mloongson-ext] [-mno-loongson-ext]
198          [-mloongson-ext2] [-mno-loongson-ext2]
199          [-minsn32] [-mno-insn32]
200          [-mfix7000] [-mno-fix7000]
201          [-mfix-rm7000] [-mno-fix-rm7000]
202          [-mfix-vr4120] [-mno-fix-vr4120]
203          [-mfix-vr4130] [-mno-fix-vr4130]
204          [-mfix-r5900] [-mno-fix-r5900]
205          [-mdebug] [-no-mdebug]
206          [-mpdr] [-mno-pdr]
207
208       Target MMIX options:
209          [--fixed-special-register-names] [--globalize-symbols]
210          [--gnu-syntax] [--relax] [--no-predefined-symbols]
211          [--no-expand] [--no-merge-gregs] [-x]
212          [--linker-allocated-gregs]
213
214       Target Nios II options:
215          [-relax-all] [-relax-section] [-no-relax]
216          [-EB] [-EL]
217
218       Target NDS32 options:
219           [-EL] [-EB] [-O] [-Os] [-mcpu=cpu]
220           [-misa=isa] [-mabi=abi] [-mall-ext]
221           [-m[no-]16-bit]  [-m[no-]perf-ext] [-m[no-]perf2-ext]
222           [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
223           [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
224           [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
225           [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
226           [-mb2bb]
227
228       Target PDP11 options:
229          [-mpic|-mno-pic] [-mall] [-mno-extensions]
230          [-mextension|-mno-extension]
231          [-mcpu] [-mmachine]
232
233       Target picoJava options:
234          [-mb|-me]
235
236       Target PowerPC options:
237          [-a32|-a64]
238          [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
239           -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|
240           -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|
241           -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|
242           -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
243           -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]
244          [-many] [-maltivec|-mvsx|-mhtm|-mvle]
245          [-mregnames|-mno-regnames]
246          [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
247          [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
248          [-msolaris|-mno-solaris]
249          [-nops=count]
250
251       Target PRU options:
252          [-link-relax]
253          [-mnolink-relax]
254          [-mno-warn-regname-label]
255
256       Target RISC-V options:
257          [-fpic|-fPIC|-fno-pic]
258          [-march=ISA]
259          [-mabi=ABI]
260          [-mlittle-endian|-mbig-endian]
261
262       Target RL78 options:
263          [-mg10]
264          [-m32bit-doubles|-m64bit-doubles]
265
266       Target RX options:
267          [-mlittle-endian|-mbig-endian]
268          [-m32bit-doubles|-m64bit-doubles]
269          [-muse-conventional-section-names]
270          [-msmall-data-limit]
271          [-mpid]
272          [-mrelax]
273          [-mint-register=number]
274          [-mgcc-abi|-mrx-abi]
275
276       Target s390 options:
277          [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
278          [-mregnames|-mno-regnames]
279          [-mwarn-areg-zero]
280
281       Target SCORE options:
282          [-EB][-EL][-FIXDD][-NWARN]
283          [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
284          [-march=score7][-march=score3]
285          [-USE_R1][-KPIC][-O0][-G num][-V]
286
287       Target SPARC options:
288          [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
289           -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
290           -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
291           -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
292           -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
293           -Asparcvisr|-Asparc5]
294          [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
295           -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
296           -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
297           -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
298           -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
299           -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
300           -bump]
301          [-32|-64]
302          [--enforce-aligned-data][--dcti-couples-detect]
303
304       Target TIC54X options:
305        [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
306        [-merrors-to-file <filename>|-me <filename>]
307
308       Target TIC6X options:
309          [-march=arch] [-mbig-endian|-mlittle-endian]
310          [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
311          [-mpic|-mno-pic]
312
313       Target TILE-Gx options:
314          [-m32|-m64][-EB][-EL]
315
316       Target Visium options:
317          [-mtune=arch]
318
319       Target Xtensa options:
320        [--[no-]text-section-literals] [--[no-]auto-litpools]
321        [--[no-]absolute-literals]
322        [--[no-]target-align] [--[no-]longcalls]
323        [--[no-]transform]
324        [--rename-section oldname=newname]
325        [--[no-]trampolines]
326        [--abi-windowed|--abi-call0]
327
328       Target Z80 options:
329         [-march=CPU[-EXT][+EXT]]
330         [-local-prefix=PREFIX]
331         [-colonless]
332         [-sdcc]
333         [-fp-s=FORMAT]
334         [-fp-d=FORMAT]
335

DESCRIPTION

337       GNU as is really a family of assemblers.  If you use (or have used) the
338       GNU assembler on one architecture, you should find a fairly similar
339       environment when you use it on another architecture.  Each version has
340       much in common with the others, including object file formats, most
341       assembler directives (often called pseudo-ops) and assembler syntax.
342
343       as is primarily intended to assemble the output of the GNU C compiler
344       "gcc" for use by the linker "ld".  Nevertheless, we've tried to make as
345       assemble correctly everything that other assemblers for the same
346       machine would assemble.  Any exceptions are documented explicitly.
347       This doesn't mean as always uses the same syntax as another assembler
348       for the same architecture; for example, we know of several incompatible
349       versions of 680x0 assembly language syntax.
350
351       Each time you run as it assembles exactly one source program.  The
352       source program is made up of one or more files.  (The standard input is
353       also a file.)
354
355       You give as a command line that has zero or more input file names.  The
356       input files are read (from left file name to right).  A command-line
357       argument (in any position) that has no special meaning is taken to be
358       an input file name.
359
360       If you give as no file names it attempts to read one input file from
361       the as standard input, which is normally your terminal.  You may have
362       to type ctl-D to tell as there is no more program to assemble.
363
364       Use -- if you need to explicitly name the standard input file in your
365       command line.
366
367       If the source is empty, as produces a small, empty object file.
368
369       as may write warnings and error messages to the standard error file
370       (usually your terminal).  This should not happen when  a compiler runs
371       as automatically.  Warnings report an assumption made so that as could
372       keep assembling a flawed program; errors report a grave problem that
373       stops the assembly.
374
375       If you are invoking as via the GNU C compiler, you can use the -Wa
376       option to pass arguments through to the assembler.  The assembler
377       arguments must be separated from each other (and the -Wa) by commas.
378       For example:
379
380               gcc -c -g -O -Wa,-alh,-L file.c
381
382       This passes two options to the assembler: -alh (emit a listing to
383       standard output with high-level and assembly source) and -L (retain
384       local symbols in the symbol table).
385
386       Usually you do not need to use this -Wa mechanism, since many compiler
387       command-line options are automatically passed to the assembler by the
388       compiler.  (You can call the GNU compiler driver with the -v option to
389       see precisely what options it passes to each compilation pass,
390       including the assembler.)
391

OPTIONS

393       @file
394           Read command-line options from file.  The options read are inserted
395           in place of the original @file option.  If file does not exist, or
396           cannot be read, then the option will be treated literally, and not
397           removed.
398
399           Options in file are separated by whitespace.  A whitespace
400           character may be included in an option by surrounding the entire
401           option in either single or double quotes.  Any character (including
402           a backslash) may be included by prefixing the character to be
403           included with a backslash.  The file may itself contain additional
404           @file options; any such options will be processed recursively.
405
406       -a[cdghlmns]
407           Turn on listings, in any of a variety of ways:
408
409           -ac omit false conditionals
410
411           -ad omit debugging directives
412
413           -ag include general information, like as version and options passed
414
415           -ah include high-level source
416
417           -al include assembly
418
419           -am include macro expansions
420
421           -an omit forms processing
422
423           -as include symbols
424
425           =file
426               set the name of the listing file
427
428           You may combine these options; for example, use -aln for assembly
429           listing without forms processing.  The =file option, if used, must
430           be the last one.  By itself, -a defaults to -ahls.
431
432       --alternate
433           Begin in alternate macro mode.
434
435       --compress-debug-sections
436           Compress DWARF debug sections using zlib with SHF_COMPRESSED from
437           the ELF ABI.  The resulting object file may not be compatible with
438           older linkers and object file utilities.  Note if compression would
439           make a given section larger then it is not compressed.
440
441       --compress-debug-sections=none
442       --compress-debug-sections=zlib
443       --compress-debug-sections=zlib-gnu
444       --compress-debug-sections=zlib-gabi
445       --compress-debug-sections=zstd
446           These options control how DWARF debug sections are compressed.
447           --compress-debug-sections=none is equivalent to
448           --nocompress-debug-sections.  --compress-debug-sections=zlib and
449           --compress-debug-sections=zlib-gabi are equivalent to
450           --compress-debug-sections.  --compress-debug-sections=zlib-gnu
451           compresses DWARF debug sections using the obsoleted zlib-gnu
452           format.  The debug sections are renamed to begin with .zdebug.
453           --compress-debug-sections=zstd compresses DWARF debug sections
454           using zstd.  Note - if compression would actually make a section
455           larger, then it is not compressed nor renamed.
456
457       --nocompress-debug-sections
458           Do not compress DWARF debug sections.  This is usually the default
459           for all targets except the x86/x86_64, but a configure time option
460           can be used to override this.
461
462       -D  Enable denugging in target specific backends, if supported.
463           Otherwise ignored.  Even if ignored, this option is accepted for
464           script compatibility with calls to other assemblers.
465
466       --debug-prefix-map old=new
467           When assembling files in directory old, record debugging
468           information describing them as in new instead.
469
470       --defsym sym=value
471           Define the symbol sym to be value before assembling the input file.
472           value must be an integer constant.  As in C, a leading 0x indicates
473           a hexadecimal value, and a leading 0 indicates an octal value.  The
474           value of the symbol can be overridden inside a source file via the
475           use of a ".set" pseudo-op.
476
477       --dump-config
478           Displays how the assembler is configured and then exits.
479
480       --elf-stt-common=no
481       --elf-stt-common=yes
482           These options control whether the ELF assembler should generate
483           common symbols with the "STT_COMMON" type.  The default can be
484           controlled by a configure option --enable-elf-stt-common.
485
486       --emulation=name
487           If the assembler is configured to support multiple different target
488           configurations then this option can be used to select the desired
489           form.
490
491       -f  "fast"---skip whitespace and comment preprocessing (assume source
492           is compiler output).
493
494       -g
495       --gen-debug
496           Generate debugging information for each assembler source line using
497           whichever debug format is preferred by the target.  This currently
498           means either STABS, ECOFF or DWARF2.  When the debug format is
499           DWARF then a ".debug_info" and ".debug_line" section is only
500           emitted when the assembly file doesn't generate one itself.
501
502       --gstabs
503           Generate stabs debugging information for each assembler line.  This
504           may help debugging assembler code, if the debugger can handle it.
505
506       --gstabs+
507           Generate stabs debugging information for each assembler line, with
508           GNU extensions that probably only gdb can handle, and that could
509           make other debuggers crash or refuse to read your program.  This
510           may help debugging assembler code.  Currently the only GNU
511           extension is the location of the current working directory at
512           assembling time.
513
514       --gdwarf-2
515           Generate DWARF2 debugging information for each assembler line.
516           This may help debugging assembler code, if the debugger can handle
517           it.  Note---this option is only supported by some targets, not all
518           of them.
519
520       --gdwarf-3
521           This option is the same as the --gdwarf-2 option, except that it
522           allows for the possibility of the generation of extra debug
523           information as per version 3 of the DWARF specification.  Note -
524           enabling this option does not guarantee the generation of any extra
525           information, the choice to do so is on a per target basis.
526
527       --gdwarf-4
528           This option is the same as the --gdwarf-2 option, except that it
529           allows for the possibility of the generation of extra debug
530           information as per version 4 of the DWARF specification.  Note -
531           enabling this option does not guarantee the generation of any extra
532           information, the choice to do so is on a per target basis.
533
534       --gdwarf-5
535           This option is the same as the --gdwarf-2 option, except that it
536           allows for the possibility of the generation of extra debug
537           information as per version 5 of the DWARF specification.  Note -
538           enabling this option does not guarantee the generation of any extra
539           information, the choice to do so is on a per target basis.
540
541       --gdwarf-sections
542           Instead of creating a .debug_line section, create a series of
543           .debug_line.foo sections where foo is the name of the corresponding
544           code section.  For example a code section called .text.func will
545           have its dwarf line number information placed into a section called
546           .debug_line.text.func.  If the code section is just called .text
547           then debug line section will still be called just .debug_line
548           without any suffix.
549
550       --gdwarf-cie-version=version
551           Control which version of DWARF Common Information Entries (CIEs)
552           are produced.  When this flag is not specificed the default is
553           version 1, though some targets can modify this default.  Other
554           possible values for version are 3 or 4.
555
556       --generate-missing-build-notes=yes
557       --generate-missing-build-notes=no
558           These options control whether the ELF assembler should generate GNU
559           Build attribute notes if none are present in the input sources.
560           The default can be controlled by the --enable-generate-build-notes
561           configure option.
562
563       --gsframe
564       --gsframe
565           Create .sframe section from CFI directives.
566
567       --hash-size N
568           Ignored.  Supported for command line compatibility with other
569           assemblers.
570
571       --help
572           Print a summary of the command-line options and exit.
573
574       --target-help
575           Print a summary of all target specific options and exit.
576
577       -I dir
578           Add directory dir to the search list for ".include" directives.
579
580       -J  Don't warn about signed overflow.
581
582       -K  Issue warnings when difference tables altered for long
583           displacements.
584
585       -L
586       --keep-locals
587           Keep (in the symbol table) local symbols.  These symbols start with
588           system-specific local label prefixes, typically .L for ELF systems
589           or L for traditional a.out systems.
590
591       --listing-lhs-width=number
592           Set the maximum width, in words, of the output data column for an
593           assembler listing to number.
594
595       --listing-lhs-width2=number
596           Set the maximum width, in words, of the output data column for
597           continuation lines in an assembler listing to number.
598
599       --listing-rhs-width=number
600           Set the maximum width of an input source line, as displayed in a
601           listing, to number bytes.
602
603       --listing-cont-lines=number
604           Set the maximum number of lines printed in a listing for a single
605           line of input to number + 1.
606
607       --multibyte-handling=allow
608       --multibyte-handling=warn
609       --multibyte-handling=warn-sym-only
610       --multibyte-handling=warn_sym_only
611           Controls how the assembler handles multibyte characters in the
612           input.  The default (which can be restored by using the allow
613           argument) is to allow such characters without complaint.  Using the
614           warn argument will make the assembler generate a warning message
615           whenever any multibyte character is encountered.  Using the warn-
616           sym-only argument will only cause a warning to be generated when a
617           symbol is defined with a name that contains multibyte characters.
618           (References to undefined symbols will not generate a warning).
619
620       --no-pad-sections
621           Stop the assembler for padding the ends of output sections to the
622           alignment of that section.  The default is to pad the sections, but
623           this can waste space which might be needed on targets which have
624           tight memory constraints.
625
626       -o objfile
627           Name the object-file output from as objfile.
628
629       -R  Fold the data section into the text section.
630
631       --reduce-memory-overheads
632           Ignored.  Supported for compatibility with tools that apss the same
633           option to both the assembler and the linker.
634
635       --sectname-subst
636           Honor substitution sequences in section names.
637
638       --size-check=error
639       --size-check=warning
640           Issue an error or warning for invalid ELF .size directive.
641
642       --statistics
643           Print the maximum space (in bytes) and total time (in seconds) used
644           by assembly.
645
646       --strip-local-absolute
647           Remove local absolute symbols from the outgoing symbol table.
648
649       -v
650       -version
651           Print the as version.
652
653       --version
654           Print the as version and exit.
655
656       -W
657       --no-warn
658           Suppress warning messages.
659
660       --fatal-warnings
661           Treat warnings as errors.
662
663       --warn
664           Don't suppress warning messages or treat them as errors.
665
666       -w  Ignored.
667
668       -x  Ignored.
669
670       -Z  Generate an object file even after errors.
671
672       -- | files ...
673           Standard input, or source files to assemble.
674
675       The following options are available when as is configured for the
676       64-bit mode of the ARM Architecture (AArch64).
677
678       -EB This option specifies that the output generated by the assembler
679           should be marked as being encoded for a big-endian processor.
680
681       -EL This option specifies that the output generated by the assembler
682           should be marked as being encoded for a little-endian processor.
683
684       -mabi=abi
685           Specify which ABI the source code uses.  The recognized arguments
686           are: "ilp32" and "lp64", which decides the generated object file in
687           ELF32 and ELF64 format respectively.  The default is "lp64".
688
689       -mcpu=processor[+extension...]
690           This option specifies the target processor.  The assembler will
691           issue an error message if an attempt is made to assemble an
692           instruction which will not execute on the target processor.  The
693           following processor names are recognized: "cortex-a34",
694           "cortex-a35", "cortex-a53", "cortex-a55", "cortex-a57",
695           "cortex-a65", "cortex-a65ae", "cortex-a72", "cortex-a73",
696           "cortex-a75", "cortex-a76", "cortex-a76ae", "cortex-a77",
697           "cortex-a78", "cortex-a78ae", "cortex-a78c", "cortex-a510",
698           "cortex-a710", "ares", "exynos-m1", "falkor", "neoverse-n1",
699           "neoverse-n2", "neoverse-e1", "neoverse-v1", "qdf24xx", "saphira",
700           "thunderx", "vulcan", "xgene1" "xgene2", "cortex-r82", "cortex-x1",
701           and "cortex-x2".  The special name "all" may be used to allow the
702           assembler to accept instructions valid for any supported processor,
703           including all optional extensions.
704
705           In addition to the basic instruction set, the assembler can be told
706           to accept, or restrict, various extension mnemonics that extend the
707           processor.
708
709           If some implementations of a particular processor can have an
710           extension, then then those extensions are automatically enabled.
711           Consequently, you will not normally have to specify any additional
712           extensions.
713
714       -march=architecture[+extension...]
715           This option specifies the target architecture.  The assembler will
716           issue an error message if an attempt is made to assemble an
717           instruction which will not execute on the target architecture.  The
718           following architecture names are recognized: "armv8-a",
719           "armv8.1-a", "armv8.2-a", "armv8.3-a", "armv8.4-a" "armv8.5-a",
720           "armv8.6-a", "armv8.7-a", "armv8.8-a", "armv8-r", "armv9-a",
721           "armv9.1-a", "armv9.2-a", and "armv9.3-a".
722
723           If both -mcpu and -march are specified, the assembler will use the
724           setting for -mcpu.  If neither are specified, the assembler will
725           default to -mcpu=all.
726
727           The architecture option can be extended with the same instruction
728           set extension options as the -mcpu option.  Unlike -mcpu,
729           extensions are not always enabled by default,
730
731       -mverbose-error
732           This option enables verbose error messages for AArch64 gas.  This
733           option is enabled by default.
734
735       -mno-verbose-error
736           This option disables verbose error messages in AArch64 gas.
737
738       The following options are available when as is configured for an Alpha
739       processor.
740
741       -mcpu
742           This option specifies the target processor.  If an attempt is made
743           to assemble an instruction which will not execute on the target
744           processor, the assembler may either expand the instruction as a
745           macro or issue an error message.  This option is equivalent to the
746           ".arch" directive.
747
748           The following processor names are recognized: 21064, "21064a",
749           21066, 21068, 21164, "21164a", "21164pc", 21264, "21264a",
750           "21264b", "ev4", "ev5", "lca45", "ev5", "ev56", "pca56", "ev6",
751           "ev67", "ev68".  The special name "all" may be used to allow the
752           assembler to accept instructions valid for any Alpha processor.
753
754           In order to support existing practice in OSF/1 with respect to
755           ".arch", and existing practice within MILO (the Linux ARC
756           bootloader), the numbered processor names (e.g. 21064) enable the
757           processor-specific PALcode instructions, while the "electro-vlasic"
758           names (e.g. "ev4") do not.
759
760       -mdebug
761       -no-mdebug
762           Enables or disables the generation of ".mdebug" encapsulation for
763           stabs directives and procedure descriptors.  The default is to
764           automatically enable ".mdebug" when the first stabs directive is
765           seen.
766
767       -relax
768           This option forces all relocations to be put into the object file,
769           instead of saving space and resolving some relocations at assembly
770           time.  Note that this option does not propagate all symbol
771           arithmetic into the object file, because not all symbol arithmetic
772           can be represented.  However, the option can still be useful in
773           specific applications.
774
775       -replace
776       -noreplace
777           Enables or disables the optimization of procedure calls, both at
778           assemblage and at link time.  These options are only available for
779           VMS targets and "-replace" is the default.  See section 1.4.1 of
780           the OpenVMS Linker Utility Manual.
781
782       -g  This option is used when the compiler generates debug information.
783           When gcc is using mips-tfile to generate debug information for
784           ECOFF, local labels must be passed through to the object file.
785           Otherwise this option has no effect.
786
787       -Gsize
788           A local common symbol larger than size is placed in ".bss", while
789           smaller symbols are placed in ".sbss".
790
791       -F
792       -32addr
793           These options are ignored for backward compatibility.
794
795       The following options are available when as is configured for an ARC
796       processor.
797
798       -mcpu=cpu
799           This option selects the core processor variant.
800
801       -EB | -EL
802           Select either big-endian (-EB) or little-endian (-EL) output.
803
804       -mcode-density
805           Enable Code Density extension instructions.
806
807       The following options are available when as is configured for the ARM
808       processor family.
809
810       -mcpu=processor[+extension...]
811           Specify which ARM processor variant is the target.
812
813       -march=architecture[+extension...]
814           Specify which ARM architecture variant is used by the target.
815
816       -mfpu=floating-point-format
817           Select which Floating Point architecture is the target.
818
819       -mfloat-abi=abi
820           Select which floating point ABI is in use.
821
822       -mthumb
823           Enable Thumb only instruction decoding.
824
825       -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
826           Select which procedure calling convention is in use.
827
828       -EB | -EL
829           Select either big-endian (-EB) or little-endian (-EL) output.
830
831       -mthumb-interwork
832           Specify that the code has been generated with interworking between
833           Thumb and ARM code in mind.
834
835       -mccs
836           Turns on CodeComposer Studio assembly syntax compatibility mode.
837
838       -k  Specify that PIC code has been generated.
839
840       The following options are available when as is configured for the
841       Blackfin processor family.
842
843       -mcpu=processor[-sirevision]
844           This option specifies the target processor.  The optional
845           sirevision is not used in assembler.  It's here such that GCC can
846           easily pass down its "-mcpu=" option.  The assembler will issue an
847           error message if an attempt is made to assemble an instruction
848           which will not execute on the target processor.  The following
849           processor names are recognized: "bf504", "bf506", "bf512", "bf514",
850           "bf516", "bf518", "bf522", "bf523", "bf524", "bf525", "bf526",
851           "bf527", "bf531", "bf532", "bf533", "bf534", "bf535" (not
852           implemented yet), "bf536", "bf537", "bf538", "bf539", "bf542",
853           "bf542m", "bf544", "bf544m", "bf547", "bf547m", "bf548", "bf548m",
854           "bf549", "bf549m", "bf561", and "bf592".
855
856       -mfdpic
857           Assemble for the FDPIC ABI.
858
859       -mno-fdpic
860       -mnopic
861           Disable -mfdpic.
862
863       The following options are available when as is configured for the Linux
864       kernel BPF processor family.
865
866       @chapter BPF Dependent Features
867
868   Options
869       -EB This option specifies that the assembler should emit big-endian
870           eBPF.
871
872       -EL This option specifies that the assembler should emit little-endian
873           eBPF.
874
875       Note that if no endianness option is specified in the command line, the
876       host endianness is used.  See the info pages for documentation of the
877       CRIS-specific options.
878
879       The following options are available when as is configured for the C-SKY
880       processor family.
881
882       -march=archname
883           Assemble for architecture archname.  The --help option lists valid
884           values for archname.
885
886       -mcpu=cpuname
887           Assemble for architecture cpuname.  The --help option lists valid
888           values for cpuname.
889
890       -EL
891       -mlittle-endian
892           Generate little-endian output.
893
894       -EB
895       -mbig-endian
896           Generate big-endian output.
897
898       -fpic
899       -pic
900           Generate position-independent code.
901
902       -mljump
903       -mno-ljump
904           Enable/disable transformation of the short branch instructions
905           "jbf", "jbt", and "jbr" to "jmpi".  This option is for V2
906           processors only.  It is ignored on CK801 and CK802 targets, which
907           do not support the "jmpi" instruction, and is enabled by default
908           for other processors.
909
910       -mbranch-stub
911       -mno-branch-stub
912           Pass through "R_CKCORE_PCREL_IMM26BY2" relocations for "bsr"
913           instructions to the linker.
914
915           This option is only available for bare-metal C-SKY V2 ELF targets,
916           where it is enabled by default.  It cannot be used in code that
917           will be dynamically linked against shared libraries.
918
919       -force2bsr
920       -mforce2bsr
921       -no-force2bsr
922       -mno-force2bsr
923           Enable/disable transformation of "jbsr" instructions to "bsr".
924           This option is always enabled (and -mno-force2bsr is ignored) for
925           CK801/CK802 targets.  It is also always enabled when -mbranch-stub
926           is in effect.
927
928       -jsri2bsr
929       -mjsri2bsr
930       -no-jsri2bsr
931       -mno-jsri2bsr
932           Enable/disable transformation of "jsri" instructions to "bsr".
933           This option is enabled by default.
934
935       -mnolrw
936       -mno-lrw
937           Enable/disable transformation of "lrw" instructions into a
938           "movih"/"ori" pair.
939
940       -melrw
941       -mno-elrw
942           Enable/disable extended "lrw" instructions.  This option is enabled
943           by default for CK800-series processors.
944
945       -mlaf
946       -mliterals-after-func
947       -mno-laf
948       -mno-literals-after-func
949           Enable/disable placement of literal pools after each function.
950
951       -mlabr
952       -mliterals-after-br
953       -mno-labr
954       -mnoliterals-after-br
955           Enable/disable placement of literal pools after unconditional
956           branches.  This option is enabled by default.
957
958       -mistack
959       -mno-istack
960           Enable/disable interrupt stack instructions.  This option is
961           enabled by default on CK801, CK802, and CK802 processors.
962
963       The following options explicitly enable certain optional instructions.
964       These features are also enabled implicitly by using "-mcpu=" to specify
965       a processor that supports it.
966
967       -mhard-float
968           Enable hard float instructions.
969
970       -mmp
971           Enable multiprocessor instructions.
972
973       -mcp
974           Enable coprocessor instructions.
975
976       -mcache
977           Enable cache prefetch instruction.
978
979       -msecurity
980           Enable C-SKY security instructions.
981
982       -mtrust
983           Enable C-SKY trust instructions.
984
985       -mdsp
986           Enable DSP instructions.
987
988       -medsp
989           Enable enhanced DSP instructions.
990
991       -mvdsp
992           Enable vector DSP instructions.
993
994       The following options are available when as is configured for an
995       Epiphany processor.
996
997       -mepiphany
998           Specifies that the both 32 and 16 bit instructions are allowed.
999           This is the default behavior.
1000
1001       -mepiphany16
1002           Restricts the permitted instructions to just the 16 bit set.
1003
1004       The following options are available when as is configured for an H8/300
1005       processor.  @chapter H8/300 Dependent Features
1006
1007   Options
1008       The Renesas H8/300 version of "as" has one machine-dependent option:
1009
1010       -h-tick-hex
1011           Support H'00 style hex constants in addition to 0x00 style.
1012
1013       -mach=name
1014           Sets the H8300 machine variant.  The following machine names are
1015           recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx" and
1016           "h8300sxn".
1017
1018       The following options are available when as is configured for an i386
1019       processor.
1020
1021       --32 | --x32 | --64
1022           Select the word size, either 32 bits or 64 bits.  --32 implies
1023           Intel i386 architecture, while --x32 and --64 imply AMD x86-64
1024           architecture with 32-bit or 64-bit word-size respectively.
1025
1026           These options are only available with the ELF object file format,
1027           and require that the necessary BFD support has been included (on a
1028           32-bit platform you have to add --enable-64-bit-bfd to configure
1029           enable 64-bit usage and use x86-64 as target platform).
1030
1031       -n  By default, x86 GAS replaces multiple nop instructions used for
1032           alignment within code sections with multi-byte nop instructions
1033           such as leal 0(%esi,1),%esi.  This switch disables the optimization
1034           if a single byte nop (0x90) is explicitly specified as the fill
1035           byte for alignment.
1036
1037       --divide
1038           On SVR4-derived platforms, the character / is treated as a comment
1039           character, which means that it cannot be used in expressions.  The
1040           --divide option turns / into a normal character.  This does not
1041           disable / at the beginning of a line starting a comment, or affect
1042           using # for starting a comment.
1043
1044       -march=CPU[+EXTENSION...]
1045           This option specifies the target processor.  The assembler will
1046           issue an error message if an attempt is made to assemble an
1047           instruction which will not execute on the target processor.  The
1048           following processor names are recognized: "i8086", "i186", "i286",
1049           "i386", "i486", "i586", "i686", "pentium", "pentiumpro",
1050           "pentiumii", "pentiumiii", "pentium4", "prescott", "nocona",
1051           "core", "core2", "corei7", "iamcu", "k6", "k6_2", "athlon",
1052           "opteron", "k8", "amdfam10", "bdver1", "bdver2", "bdver3",
1053           "bdver4", "znver1", "znver2", "znver3", "znver4", "btver1",
1054           "btver2", "generic32" and "generic64".
1055
1056           In addition to the basic instruction set, the assembler can be told
1057           to accept various extension mnemonics.  For example,
1058           "-march=i686+sse4+vmx" extends i686 with sse4 and vmx.  The
1059           following extensions are currently supported: 8087, 287, 387, 687,
1060           "cmov", "fxsr", "mmx", "sse", "sse2", "sse3", "sse4a", "ssse3",
1061           "sse4.1", "sse4.2", "sse4", "avx", "avx2", "adx", "rdseed",
1062           "prfchw", "smap", "mpx", "sha", "rdpid", "ptwrite", "cet", "gfni",
1063           "vaes", "vpclmulqdq", "prefetchwt1", "clflushopt", "se1", "clwb",
1064           "movdiri", "movdir64b", "enqcmd", "serialize", "tsxldtrk", "kl",
1065           "widekl", "hreset", "avx512f", "avx512cd", "avx512er", "avx512pf",
1066           "avx512vl", "avx512bw", "avx512dq", "avx512ifma", "avx512vbmi",
1067           "avx512_4fmaps", "avx512_4vnniw", "avx512_vpopcntdq",
1068           "avx512_vbmi2", "avx512_vnni", "avx512_bitalg",
1069           "avx512_vp2intersect", "tdx", "avx512_bf16", "avx_vnni",
1070           "avx512_fp16", "prefetchi", "avx_ifma", "avx_vnni_int8",
1071           "cmpccxadd", "wrmsrns", "msrlist", "avx_ne_convert", "rao_int",
1072           "amx_int8", "amx_bf16", "amx_fp16", "amx_tile", "vmx", "vmfunc",
1073           "smx", "xsave", "xsaveopt", "xsavec", "xsaves", "aes", "pclmul",
1074           "fsgsbase", "rdrnd", "f16c", "bmi2", "fma", "movbe", "ept",
1075           "lzcnt", "popcnt", "hle", "rtm", "tsx", "invpcid", "clflush",
1076           "mwaitx", "clzero", "wbnoinvd", "pconfig", "waitpkg", "uintr",
1077           "cldemote", "rdpru", "mcommit", "sev_es", "lwp", "fma4", "xop",
1078           "cx16", "syscall", "rdtscp", "3dnow", "3dnowa", "sse4a", "sse5",
1079           "snp", "invlpgb", "tlbsync", "svme" and "padlock".  Note that these
1080           extension mnemonics can be prefixed with "no" to revoke the
1081           respective (and any dependent) functionality.
1082
1083           When the ".arch" directive is used with -march, the ".arch"
1084           directive will take precedent.
1085
1086       -mtune=CPU
1087           This option specifies a processor to optimize for. When used in
1088           conjunction with the -march option, only instructions of the
1089           processor specified by the -march option will be generated.
1090
1091           Valid CPU values are identical to the processor list of -march=CPU.
1092
1093       -msse2avx
1094           This option specifies that the assembler should encode SSE
1095           instructions with VEX prefix.
1096
1097       -muse-unaligned-vector-move
1098           This option specifies that the assembler should encode aligned
1099           vector move as unaligned vector move.
1100
1101       -msse-check=none
1102       -msse-check=warning
1103       -msse-check=error
1104           These options control if the assembler should check SSE
1105           instructions.  -msse-check=none will make the assembler not to
1106           check SSE instructions,  which is the default.  -msse-check=warning
1107           will make the assembler issue a warning for any SSE instruction.
1108           -msse-check=error will make the assembler issue an error for any
1109           SSE instruction.
1110
1111       -mavxscalar=128
1112       -mavxscalar=256
1113           These options control how the assembler should encode scalar AVX
1114           instructions.  -mavxscalar=128 will encode scalar AVX instructions
1115           with 128bit vector length, which is the default.  -mavxscalar=256
1116           will encode scalar AVX instructions with 256bit vector length.
1117
1118           WARNING: Don't use this for production code - due to CPU errata the
1119           resulting code may not work on certain models.
1120
1121       -mvexwig=0
1122       -mvexwig=1
1123           These options control how the assembler should encode VEX.W-ignored
1124           (WIG) VEX instructions.  -mvexwig=0 will encode WIG VEX
1125           instructions with vex.w = 0, which is the default.  -mvexwig=1 will
1126           encode WIG EVEX instructions with vex.w = 1.
1127
1128           WARNING: Don't use this for production code - due to CPU errata the
1129           resulting code may not work on certain models.
1130
1131       -mevexlig=128
1132       -mevexlig=256
1133       -mevexlig=512
1134           These options control how the assembler should encode length-
1135           ignored (LIG) EVEX instructions.  -mevexlig=128 will encode LIG
1136           EVEX instructions with 128bit vector length, which is the default.
1137           -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions
1138           with 256bit and 512bit vector length, respectively.
1139
1140       -mevexwig=0
1141       -mevexwig=1
1142           These options control how the assembler should encode w-ignored
1143           (WIG) EVEX instructions.  -mevexwig=0 will encode WIG EVEX
1144           instructions with evex.w = 0, which is the default.  -mevexwig=1
1145           will encode WIG EVEX instructions with evex.w = 1.
1146
1147       -mmnemonic=att
1148       -mmnemonic=intel
1149           This option specifies instruction mnemonic for matching
1150           instructions.  The ".att_mnemonic" and ".intel_mnemonic" directives
1151           will take precedent.
1152
1153       -msyntax=att
1154       -msyntax=intel
1155           This option specifies instruction syntax when processing
1156           instructions.  The ".att_syntax" and ".intel_syntax" directives
1157           will take precedent.
1158
1159       -mnaked-reg
1160           This option specifies that registers don't require a % prefix.  The
1161           ".att_syntax" and ".intel_syntax" directives will take precedent.
1162
1163       -madd-bnd-prefix
1164           This option forces the assembler to add BND prefix to all branches,
1165           even if such prefix was not explicitly specified in the source
1166           code.
1167
1168       -mno-shared
1169           On ELF target, the assembler normally optimizes out non-PLT
1170           relocations against defined non-weak global branch targets with
1171           default visibility.  The -mshared option tells the assembler to
1172           generate code which may go into a shared library where all non-weak
1173           global branch targets with default visibility can be preempted.
1174           The resulting code is slightly bigger.  This option only affects
1175           the handling of branch instructions.
1176
1177       -mbig-obj
1178           On PE/COFF target this option forces the use of big object file
1179           format, which allows more than 32768 sections.
1180
1181       -momit-lock-prefix=no
1182       -momit-lock-prefix=yes
1183           These options control how the assembler should encode lock prefix.
1184           This option is intended as a workaround for processors, that fail
1185           on lock prefix. This option can only be safely used with single-
1186           core, single-thread computers -momit-lock-prefix=yes will omit all
1187           lock prefixes.  -momit-lock-prefix=no will encode lock prefix as
1188           usual, which is the default.
1189
1190       -mfence-as-lock-add=no
1191       -mfence-as-lock-add=yes
1192           These options control how the assembler should encode lfence,
1193           mfence and sfence.  -mfence-as-lock-add=yes will encode lfence,
1194           mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock
1195           addl $0x0, (%esp) in 32-bit mode.  -mfence-as-lock-add=no will
1196           encode lfence, mfence and sfence as usual, which is the default.
1197
1198       -mrelax-relocations=no
1199       -mrelax-relocations=yes
1200           These options control whether the assembler should generate relax
1201           relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
1202           and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
1203           -mrelax-relocations=yes will generate relax relocations.
1204           -mrelax-relocations=no will not generate relax relocations.  The
1205           default can be controlled by a configure option
1206           --enable-x86-relax-relocations.
1207
1208       -malign-branch-boundary=NUM
1209           This option controls how the assembler should align branches with
1210           segment prefixes or NOP.  NUM must be a power of 2.  It should be 0
1211           or no less than 16.  Branches will be aligned within NUM byte
1212           boundary.  -malign-branch-boundary=0, which is the default, doesn't
1213           align branches.
1214
1215       -malign-branch=TYPE[+TYPE...]
1216           This option specifies types of branches to align. TYPE is
1217           combination of jcc, which aligns conditional jumps, fused, which
1218           aligns fused conditional jumps, jmp, which aligns unconditional
1219           jumps, call which aligns calls, ret, which aligns rets, indirect,
1220           which aligns indirect jumps and calls.  The default is
1221           -malign-branch=jcc+fused+jmp.
1222
1223       -malign-branch-prefix-size=NUM
1224           This option specifies the maximum number of prefixes on an
1225           instruction to align branches.  NUM should be between 0 and 5.  The
1226           default NUM is 5.
1227
1228       -mbranches-within-32B-boundaries
1229           This option aligns conditional jumps, fused conditional jumps and
1230           unconditional jumps within 32 byte boundary with up to 5 segment
1231           prefixes on an instruction.  It is equivalent to
1232           -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp
1233           -malign-branch-prefix-size=5.  The default doesn't align branches.
1234
1235       -mlfence-after-load=no
1236       -mlfence-after-load=yes
1237           These options control whether the assembler should generate lfence
1238           after load instructions.  -mlfence-after-load=yes will generate
1239           lfence.  -mlfence-after-load=no will not generate lfence, which is
1240           the default.
1241
1242       -mlfence-before-indirect-branch=none
1243       -mlfence-before-indirect-branch=all
1244       -mlfence-before-indirect-branch=register
1245       -mlfence-before-indirect-branch=memory
1246           These options control whether the assembler should generate lfence
1247           before indirect near branch instructions.
1248           -mlfence-before-indirect-branch=all will generate lfence before
1249           indirect near branch via register and issue a warning before
1250           indirect near branch via memory.  It also implicitly sets
1251           -mlfence-before-ret=shl when there's no explicit
1252           -mlfence-before-ret=.  -mlfence-before-indirect-branch=register
1253           will generate lfence before indirect near branch via register.
1254           -mlfence-before-indirect-branch=memory will issue a warning before
1255           indirect near branch via memory.
1256           -mlfence-before-indirect-branch=none will not generate lfence nor
1257           issue warning, which is the default.  Note that lfence won't be
1258           generated before indirect near branch via register with
1259           -mlfence-after-load=yes since lfence will be generated after
1260           loading branch target register.
1261
1262       -mlfence-before-ret=none
1263       -mlfence-before-ret=shl
1264       -mlfence-before-ret=or
1265       -mlfence-before-ret=yes
1266       -mlfence-before-ret=not
1267           These options control whether the assembler should generate lfence
1268           before ret.  -mlfence-before-ret=or will generate generate or
1269           instruction with lfence.  -mlfence-before-ret=shl/yes will generate
1270           shl instruction with lfence. -mlfence-before-ret=not will generate
1271           not instruction with lfence. -mlfence-before-ret=none will not
1272           generate lfence, which is the default.
1273
1274       -mx86-used-note=no
1275       -mx86-used-note=yes
1276           These options control whether the assembler should generate
1277           GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
1278           property notes.  The default can be controlled by the
1279           --enable-x86-used-note configure option.
1280
1281       -mevexrcig=rne
1282       -mevexrcig=rd
1283       -mevexrcig=ru
1284       -mevexrcig=rz
1285           These options control how the assembler should encode SAE-only EVEX
1286           instructions.  -mevexrcig=rne will encode RC bits of EVEX
1287           instruction with 00, which is the default.  -mevexrcig=rd,
1288           -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX
1289           instructions with 01, 10 and 11 RC bits, respectively.
1290
1291       -mamd64
1292       -mintel64
1293           This option specifies that the assembler should accept only AMD64
1294           or Intel64 ISA in 64-bit mode.  The default is to accept common,
1295           Intel64 only and AMD64 ISAs.
1296
1297       -O0 | -O | -O1 | -O2 | -Os
1298           Optimize instruction encoding with smaller instruction size.  -O
1299           and -O1 encode 64-bit register load instructions with 64-bit
1300           immediate as 32-bit register load instructions with 31-bit or
1301           32-bits immediates, encode 64-bit register clearing instructions
1302           with 32-bit register clearing instructions, encode 256-bit/512-bit
1303           VEX/EVEX vector register clearing instructions with 128-bit VEX
1304           vector register clearing instructions, encode 128-bit/256-bit EVEX
1305           vector register load/store instructions with VEX vector register
1306           load/store instructions, and encode 128-bit/256-bit EVEX packed
1307           integer logical instructions with 128-bit/256-bit VEX packed
1308           integer logical.
1309
1310           -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX
1311           vector register clearing instructions with 128-bit EVEX vector
1312           register clearing instructions.  In 64-bit mode VEX encoded
1313           instructions with commutative source operands will also have their
1314           source operands swapped if this allows using the 2-byte VEX prefix
1315           form instead of the 3-byte one.  Certain forms of AND as well as OR
1316           with the same (register) operand specified twice will also be
1317           changed to TEST.
1318
1319           -Os includes -O2 optimization plus encodes 16-bit, 32-bit and
1320           64-bit register tests with immediate as 8-bit register test with
1321           immediate.  -O0 turns off this optimization.
1322
1323       The following options are available when as is configured for the
1324       Ubicom IP2K series.
1325
1326       -mip2022ext
1327           Specifies that the extended IP2022 instructions are allowed.
1328
1329       -mip2022
1330           Restores the default behaviour, which restricts the permitted
1331           instructions to just the basic IP2022 ones.
1332
1333       The following options are available when as is configured for the
1334       Renesas M32C and M16C processors.
1335
1336       -m32c
1337           Assemble M32C instructions.
1338
1339       -m16c
1340           Assemble M16C instructions (the default).
1341
1342       -relax
1343           Enable support for link-time relaxations.
1344
1345       -h-tick-hex
1346           Support H'00 style hex constants in addition to 0x00 style.
1347
1348       The following options are available when as is configured for the
1349       Renesas M32R (formerly Mitsubishi M32R) series.
1350
1351       --m32rx
1352           Specify which processor in the M32R family is the target.  The
1353           default is normally the M32R, but this option changes it to the
1354           M32RX.
1355
1356       --warn-explicit-parallel-conflicts or --Wp
1357           Produce warning messages when questionable parallel constructs are
1358           encountered.
1359
1360       --no-warn-explicit-parallel-conflicts or --Wnp
1361           Do not produce warning messages when questionable parallel
1362           constructs are encountered.
1363
1364       The following options are available when as is configured for the
1365       Motorola 68000 series.
1366
1367       -l  Shorten references to undefined symbols, to one word instead of
1368           two.
1369
1370       -m68000 | -m68008 | -m68010 | -m68020 | -m68030
1371       | -m68040 | -m68060 | -m68302 | -m68331 | -m68332
1372       | -m68333 | -m68340 | -mcpu32 | -m5200
1373           Specify what processor in the 68000 family is the target.  The
1374           default is normally the 68020, but this can be changed at
1375           configuration time.
1376
1377       -m68881 | -m68882 | -mno-68881 | -mno-68882
1378           The target machine does (or does not) have a floating-point
1379           coprocessor.  The default is to assume a coprocessor for 68020,
1380           68030, and cpu32.  Although the basic 68000 is not compatible with
1381           the 68881, a combination of the two can be specified, since it's
1382           possible to do emulation of the coprocessor instructions with the
1383           main processor.
1384
1385       -m68851 | -mno-68851
1386           The target machine does (or does not) have a memory-management unit
1387           coprocessor.  The default is to assume an MMU for 68020 and up.
1388
1389       The following options are available when as is configured for an Altera
1390       Nios II processor.
1391
1392       -relax-section
1393           Replace identified out-of-range branches with PC-relative "jmp"
1394           sequences when possible.  The generated code sequences are suitable
1395           for use in position-independent code, but there is a practical
1396           limit on the extended branch range because of the length of the
1397           sequences.  This option is the default.
1398
1399       -relax-all
1400           Replace branch instructions not determinable to be in range and all
1401           call instructions with "jmp" and "callr" sequences (respectively).
1402           This option generates absolute relocations against the target
1403           symbols and is not appropriate for position-independent code.
1404
1405       -no-relax
1406           Do not replace any branches or calls.
1407
1408       -EB Generate big-endian output.
1409
1410       -EL Generate little-endian output.  This is the default.
1411
1412       -march=architecture
1413           This option specifies the target architecture.  The assembler
1414           issues an error message if an attempt is made to assemble an
1415           instruction which will not execute on the target architecture.  The
1416           following architecture names are recognized: "r1", "r2".  The
1417           default is "r1".
1418
1419       The following options are available when as is configured for a PRU
1420       processor.
1421
1422       -mlink-relax
1423           Assume that LD would optimize LDI32 instructions by checking the
1424           upper 16 bits of the expression. If they are all zeros, then LD
1425           would shorten the LDI32 instruction to a single LDI. In such case
1426           "as" will output DIFF relocations for diff expressions.
1427
1428       -mno-link-relax
1429           Assume that LD would not optimize LDI32 instructions. As a
1430           consequence, DIFF relocations will not be emitted.
1431
1432       -mno-warn-regname-label
1433           Do not warn if a label name matches a register name. Usually
1434           assembler programmers will want this warning to be emitted. C
1435           compilers may want to turn this off.
1436
1437       The following options are available when as is configured for a MIPS
1438       processor.
1439
1440       -G num
1441           This option sets the largest size of an object that can be
1442           referenced implicitly with the "gp" register.  It is only accepted
1443           for targets that use ECOFF format, such as a DECstation running
1444           Ultrix.  The default value is 8.
1445
1446       -EB Generate "big endian" format output.
1447
1448       -EL Generate "little endian" format output.
1449
1450       -mips1
1451       -mips2
1452       -mips3
1453       -mips4
1454       -mips5
1455       -mips32
1456       -mips32r2
1457       -mips32r3
1458       -mips32r5
1459       -mips32r6
1460       -mips64
1461       -mips64r2
1462       -mips64r3
1463       -mips64r5
1464       -mips64r6
1465           Generate code for a particular MIPS Instruction Set Architecture
1466           level.  -mips1 is an alias for -march=r3000, -mips2 is an alias for
1467           -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an
1468           alias for -march=r8000.  -mips5, -mips32, -mips32r2, -mips32r3,
1469           -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and
1470           -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
1471           MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64,
1472           MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64
1473           Release 6 ISA processors, respectively.
1474
1475       -march=cpu
1476           Generate code for a particular MIPS CPU.
1477
1478       -mtune=cpu
1479           Schedule and tune for a particular MIPS CPU.
1480
1481       -mfix7000
1482       -mno-fix7000
1483           Cause nops to be inserted if the read of the destination register
1484           of an mfhi or mflo instruction occurs in the following two
1485           instructions.
1486
1487       -mfix-rm7000
1488       -mno-fix-rm7000
1489           Cause nops to be inserted if a dmult or dmultu instruction is
1490           followed by a load instruction.
1491
1492       -mfix-r5900
1493       -mno-fix-r5900
1494           Do not attempt to schedule the preceding instruction into the delay
1495           slot of a branch instruction placed at the end of a short loop of
1496           six instructions or fewer and always schedule a "nop" instruction
1497           there instead.  The short loop bug under certain conditions causes
1498           loops to execute only once or twice, due to a hardware bug in the
1499           R5900 chip.
1500
1501       -mdebug
1502       -no-mdebug
1503           Cause stabs-style debugging output to go into an ECOFF-style
1504           .mdebug section instead of the standard ELF .stabs sections.
1505
1506       -mpdr
1507       -mno-pdr
1508           Control generation of ".pdr" sections.
1509
1510       -mgp32
1511       -mfp32
1512           The register sizes are normally inferred from the ISA and ABI, but
1513           these flags force a certain group of registers to be treated as 32
1514           bits wide at all times.  -mgp32 controls the size of general-
1515           purpose registers and -mfp32 controls the size of floating-point
1516           registers.
1517
1518       -mgp64
1519       -mfp64
1520           The register sizes are normally inferred from the ISA and ABI, but
1521           these flags force a certain group of registers to be treated as 64
1522           bits wide at all times.  -mgp64 controls the size of general-
1523           purpose registers and -mfp64 controls the size of floating-point
1524           registers.
1525
1526       -mfpxx
1527           The register sizes are normally inferred from the ISA and ABI, but
1528           using this flag in combination with -mabi=32 enables an ABI variant
1529           which will operate correctly with floating-point registers which
1530           are 32 or 64 bits wide.
1531
1532       -modd-spreg
1533       -mno-odd-spreg
1534           Enable use of floating-point operations on odd-numbered single-
1535           precision registers when supported by the ISA.  -mfpxx implies
1536           -mno-odd-spreg, otherwise the default is -modd-spreg.
1537
1538       -mips16
1539       -no-mips16
1540           Generate code for the MIPS 16 processor.  This is equivalent to
1541           putting ".module mips16" at the start of the assembly file.
1542           -no-mips16 turns off this option.
1543
1544       -mmips16e2
1545       -mno-mips16e2
1546           Enable the use of MIPS16e2 instructions in MIPS16 mode.  This is
1547           equivalent to putting ".module mips16e2" at the start of the
1548           assembly file.  -mno-mips16e2 turns off this option.
1549
1550       -mmicromips
1551       -mno-micromips
1552           Generate code for the microMIPS processor.  This is equivalent to
1553           putting ".module micromips" at the start of the assembly file.
1554           -mno-micromips turns off this option.  This is equivalent to
1555           putting ".module nomicromips" at the start of the assembly file.
1556
1557       -msmartmips
1558       -mno-smartmips
1559           Enables the SmartMIPS extension to the MIPS32 instruction set.
1560           This is equivalent to putting ".module smartmips" at the start of
1561           the assembly file.  -mno-smartmips turns off this option.
1562
1563       -mips3d
1564       -no-mips3d
1565           Generate code for the MIPS-3D Application Specific Extension.  This
1566           tells the assembler to accept MIPS-3D instructions.  -no-mips3d
1567           turns off this option.
1568
1569       -mdmx
1570       -no-mdmx
1571           Generate code for the MDMX Application Specific Extension.  This
1572           tells the assembler to accept MDMX instructions.  -no-mdmx turns
1573           off this option.
1574
1575       -mdsp
1576       -mno-dsp
1577           Generate code for the DSP Release 1 Application Specific Extension.
1578           This tells the assembler to accept DSP Release 1 instructions.
1579           -mno-dsp turns off this option.
1580
1581       -mdspr2
1582       -mno-dspr2
1583           Generate code for the DSP Release 2 Application Specific Extension.
1584           This option implies -mdsp.  This tells the assembler to accept DSP
1585           Release 2 instructions.  -mno-dspr2 turns off this option.
1586
1587       -mdspr3
1588       -mno-dspr3
1589           Generate code for the DSP Release 3 Application Specific Extension.
1590           This option implies -mdsp and -mdspr2.  This tells the assembler to
1591           accept DSP Release 3 instructions.  -mno-dspr3 turns off this
1592           option.
1593
1594       -mmsa
1595       -mno-msa
1596           Generate code for the MIPS SIMD Architecture Extension.  This tells
1597           the assembler to accept MSA instructions.  -mno-msa turns off this
1598           option.
1599
1600       -mxpa
1601       -mno-xpa
1602           Generate code for the MIPS eXtended Physical Address (XPA)
1603           Extension.  This tells the assembler to accept XPA instructions.
1604           -mno-xpa turns off this option.
1605
1606       -mmt
1607       -mno-mt
1608           Generate code for the MT Application Specific Extension.  This
1609           tells the assembler to accept MT instructions.  -mno-mt turns off
1610           this option.
1611
1612       -mmcu
1613       -mno-mcu
1614           Generate code for the MCU Application Specific Extension.  This
1615           tells the assembler to accept MCU instructions.  -mno-mcu turns off
1616           this option.
1617
1618       -mcrc
1619       -mno-crc
1620           Generate code for the MIPS cyclic redundancy check (CRC)
1621           Application Specific Extension.  This tells the assembler to accept
1622           CRC instructions.  -mno-crc turns off this option.
1623
1624       -mginv
1625       -mno-ginv
1626           Generate code for the Global INValidate (GINV) Application Specific
1627           Extension.  This tells the assembler to accept GINV instructions.
1628           -mno-ginv turns off this option.
1629
1630       -mloongson-mmi
1631       -mno-loongson-mmi
1632           Generate code for the Loongson MultiMedia extensions Instructions
1633           (MMI) Application Specific Extension.  This tells the assembler to
1634           accept MMI instructions.  -mno-loongson-mmi turns off this option.
1635
1636       -mloongson-cam
1637       -mno-loongson-cam
1638           Generate code for the Loongson Content Address Memory (CAM)
1639           instructions.  This tells the assembler to accept Loongson CAM
1640           instructions.  -mno-loongson-cam turns off this option.
1641
1642       -mloongson-ext
1643       -mno-loongson-ext
1644           Generate code for the Loongson EXTensions (EXT) instructions.  This
1645           tells the assembler to accept Loongson EXT instructions.
1646           -mno-loongson-ext turns off this option.
1647
1648       -mloongson-ext2
1649       -mno-loongson-ext2
1650           Generate code for the Loongson EXTensions R2 (EXT2) instructions.
1651           This option implies -mloongson-ext.  This tells the assembler to
1652           accept Loongson EXT2 instructions.  -mno-loongson-ext2 turns off
1653           this option.
1654
1655       -minsn32
1656       -mno-insn32
1657           Only use 32-bit instruction encodings when generating code for the
1658           microMIPS processor.  This option inhibits the use of any 16-bit
1659           instructions.  This is equivalent to putting ".set insn32" at the
1660           start of the assembly file.  -mno-insn32 turns off this option.
1661           This is equivalent to putting ".set noinsn32" at the start of the
1662           assembly file.  By default -mno-insn32 is selected, allowing all
1663           instructions to be used.
1664
1665       --construct-floats
1666       --no-construct-floats
1667           The --no-construct-floats option disables the construction of
1668           double width floating point constants by loading the two halves of
1669           the value into the two single width floating point registers that
1670           make up the double width register.  By default --construct-floats
1671           is selected, allowing construction of these floating point
1672           constants.
1673
1674       --relax-branch
1675       --no-relax-branch
1676           The --relax-branch option enables the relaxation of out-of-range
1677           branches.  By default --no-relax-branch is selected, causing any
1678           out-of-range branches to produce an error.
1679
1680       -mignore-branch-isa
1681       -mno-ignore-branch-isa
1682           Ignore branch checks for invalid transitions between ISA modes.
1683           The semantics of branches does not provide for an ISA mode switch,
1684           so in most cases the ISA mode a branch has been encoded for has to
1685           be the same as the ISA mode of the branch's target label.
1686           Therefore GAS has checks implemented that verify in branch assembly
1687           that the two ISA modes match.  -mignore-branch-isa disables these
1688           checks.  By default -mno-ignore-branch-isa is selected, causing any
1689           invalid branch requiring a transition between ISA modes to produce
1690           an error.
1691
1692       -mnan=encoding
1693           Select between the IEEE 754-2008 (-mnan=2008) or the legacy
1694           (-mnan=legacy) NaN encoding format.  The latter is the default.
1695
1696       --emulation=name
1697           This option was formerly used to switch between ELF and ECOFF
1698           output on targets like IRIX 5 that supported both.  MIPS ECOFF
1699           support was removed in GAS 2.24, so the option now serves little
1700           purpose.  It is retained for backwards compatibility.
1701
1702           The available configuration names are: mipself, mipslelf and
1703           mipsbelf.  Choosing mipself now has no effect, since the output is
1704           always ELF.  mipslelf and mipsbelf select little- and big-endian
1705           output respectively, but -EL and -EB are now the preferred options
1706           instead.
1707
1708       -nocpp
1709           as ignores this option.  It is accepted for compatibility with the
1710           native tools.
1711
1712       --trap
1713       --no-trap
1714       --break
1715       --no-break
1716           Control how to deal with multiplication overflow and division by
1717           zero.  --trap or --no-break (which are synonyms) take a trap
1718           exception (and only work for Instruction Set Architecture level 2
1719           and higher); --break or --no-trap (also synonyms, and the default)
1720           take a break exception.
1721
1722       -n  When this option is used, as will issue a warning every time it
1723           generates a nop instruction from a macro.
1724
1725       The following options are available when as is configured for a
1726       LoongArch processor.
1727
1728       -fpic
1729       -fPIC
1730           Generate position-independent code
1731
1732       -fno-pic
1733           Don't generate position-independent code (default)
1734
1735       The following options are available when as is configured for a Meta
1736       processor.
1737
1738       "-mcpu=metac11"
1739           Generate code for Meta 1.1.
1740
1741       "-mcpu=metac12"
1742           Generate code for Meta 1.2.
1743
1744       "-mcpu=metac21"
1745           Generate code for Meta 2.1.
1746
1747       "-mfpu=metac21"
1748           Allow code to use FPU hardware of Meta 2.1.
1749
1750       See the info pages for documentation of the MMIX-specific options.
1751
1752       The following options are available when as is configured for a NDS32
1753       processor.
1754
1755       "-O1"
1756           Optimize for performance.
1757
1758       "-Os"
1759           Optimize for space.
1760
1761       "-EL"
1762           Produce little endian data output.
1763
1764       "-EB"
1765           Produce little endian data output.
1766
1767       "-mpic"
1768           Generate PIC.
1769
1770       "-mno-fp-as-gp-relax"
1771           Suppress fp-as-gp relaxation for this file.
1772
1773       "-mb2bb-relax"
1774           Back-to-back branch optimization.
1775
1776       "-mno-all-relax"
1777           Suppress all relaxation for this file.
1778
1779       "-march=<arch name>"
1780           Assemble for architecture <arch name> which could be v3, v3j, v3m,
1781           v3f, v3s, v2, v2j, v2f, v2s.
1782
1783       "-mbaseline=<baseline>"
1784           Assemble for baseline <baseline> which could be v2, v3, v3m.
1785
1786       "-mfpu-freg=FREG"
1787           Specify a FPU configuration.
1788
1789           "0      8 SP /  4 DP registers"
1790           "1     16 SP /  8 DP registers"
1791           "2     32 SP / 16 DP registers"
1792           "3     32 SP / 32 DP registers"
1793       "-mabi=abi"
1794           Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
1795
1796       "-m[no-]mac"
1797           Enable/Disable Multiply instructions support.
1798
1799       "-m[no-]div"
1800           Enable/Disable Divide instructions support.
1801
1802       "-m[no-]16bit-ext"
1803           Enable/Disable 16-bit extension
1804
1805       "-m[no-]dx-regs"
1806           Enable/Disable d0/d1 registers
1807
1808       "-m[no-]perf-ext"
1809           Enable/Disable Performance extension
1810
1811       "-m[no-]perf2-ext"
1812           Enable/Disable Performance extension 2
1813
1814       "-m[no-]string-ext"
1815           Enable/Disable String extension
1816
1817       "-m[no-]reduced-regs"
1818           Enable/Disable Reduced Register configuration (GPR16) option
1819
1820       "-m[no-]audio-isa-ext"
1821           Enable/Disable AUDIO ISA extension
1822
1823       "-m[no-]fpu-sp-ext"
1824           Enable/Disable FPU SP extension
1825
1826       "-m[no-]fpu-dp-ext"
1827           Enable/Disable FPU DP extension
1828
1829       "-m[no-]fpu-fma"
1830           Enable/Disable FPU fused-multiply-add instructions
1831
1832       "-mall-ext"
1833           Turn on all extensions and instructions support
1834
1835       The following options are available when as is configured for a PowerPC
1836       processor.
1837
1838       -a32
1839           Generate ELF32 or XCOFF32.
1840
1841       -a64
1842           Generate ELF64 or XCOFF64.
1843
1844       -K PIC
1845           Set EF_PPC_RELOCATABLE_LIB in ELF flags.
1846
1847       -mpwrx | -mpwr2
1848           Generate code for POWER/2 (RIOS2).
1849
1850       -mpwr
1851           Generate code for POWER (RIOS1)
1852
1853       -m601
1854           Generate code for PowerPC 601.
1855
1856       -mppc, -mppc32, -m603, -m604
1857           Generate code for PowerPC 603/604.
1858
1859       -m403, -m405
1860           Generate code for PowerPC 403/405.
1861
1862       -m440
1863           Generate code for PowerPC 440.  BookE and some 405 instructions.
1864
1865       -m464
1866           Generate code for PowerPC 464.
1867
1868       -m476
1869           Generate code for PowerPC 476.
1870
1871       -m7400, -m7410, -m7450, -m7455
1872           Generate code for PowerPC 7400/7410/7450/7455.
1873
1874       -m750cl, -mgekko, -mbroadway
1875           Generate code for PowerPC 750CL/Gekko/Broadway.
1876
1877       -m821, -m850, -m860
1878           Generate code for PowerPC 821/850/860.
1879
1880       -mppc64, -m620
1881           Generate code for PowerPC 620/625/630.
1882
1883       -me200z2, -me200z4
1884           Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE.
1885
1886       -me300
1887           Generate code for PowerPC e300 family.
1888
1889       -me500, -me500x2
1890           Generate code for Motorola e500 core complex.
1891
1892       -me500mc
1893           Generate code for Freescale e500mc core complex.
1894
1895       -me500mc64
1896           Generate code for Freescale e500mc64 core complex.
1897
1898       -me5500
1899           Generate code for Freescale e5500 core complex.
1900
1901       -me6500
1902           Generate code for Freescale e6500 core complex.
1903
1904       -mlsp
1905           Enable LSP instructions.  (Disables SPE and SPE2.)
1906
1907       -mspe
1908           Generate code for Motorola SPE instructions.  (Disables LSP.)
1909
1910       -mspe2
1911           Generate code for Freescale SPE2 instructions.  (Disables LSP.)
1912
1913       -mtitan
1914           Generate code for AppliedMicro Titan core complex.
1915
1916       -mppc64bridge
1917           Generate code for PowerPC 64, including bridge insns.
1918
1919       -mbooke
1920           Generate code for 32-bit BookE.
1921
1922       -ma2
1923           Generate code for A2 architecture.
1924
1925       -maltivec
1926           Generate code for processors with AltiVec instructions.
1927
1928       -mvle
1929           Generate code for Freescale PowerPC VLE instructions.
1930
1931       -mvsx
1932           Generate code for processors with Vector-Scalar (VSX) instructions.
1933
1934       -mhtm
1935           Generate code for processors with Hardware Transactional Memory
1936           instructions.
1937
1938       -mpower4, -mpwr4
1939           Generate code for Power4 architecture.
1940
1941       -mpower5, -mpwr5, -mpwr5x
1942           Generate code for Power5 architecture.
1943
1944       -mpower6, -mpwr6
1945           Generate code for Power6 architecture.
1946
1947       -mpower7, -mpwr7
1948           Generate code for Power7 architecture.
1949
1950       -mpower8, -mpwr8
1951           Generate code for Power8 architecture.
1952
1953       -mpower9, -mpwr9
1954           Generate code for Power9 architecture.
1955
1956       -mpower10, -mpwr10
1957           Generate code for Power10 architecture.
1958
1959       -mfuture
1960           Generate code for 'future' architecture.
1961
1962       -mcell
1963       -mcell
1964           Generate code for Cell Broadband Engine architecture.
1965
1966       -mcom
1967           Generate code Power/PowerPC common instructions.
1968
1969       -many
1970           Generate code for any architecture (PWR/PWRX/PPC).
1971
1972       -mregnames
1973           Allow symbolic names for registers.
1974
1975       -mno-regnames
1976           Do not allow symbolic names for registers.
1977
1978       -mrelocatable
1979           Support for GCC's -mrelocatable option.
1980
1981       -mrelocatable-lib
1982           Support for GCC's -mrelocatable-lib option.
1983
1984       -memb
1985           Set PPC_EMB bit in ELF flags.
1986
1987       -mlittle, -mlittle-endian, -le
1988           Generate code for a little endian machine.
1989
1990       -mbig, -mbig-endian, -be
1991           Generate code for a big endian machine.
1992
1993       -msolaris
1994           Generate code for Solaris.
1995
1996       -mno-solaris
1997           Do not generate code for Solaris.
1998
1999       -nops=count
2000           If an alignment directive inserts more than count nops, put a
2001           branch at the beginning to skip execution of the nops.
2002
2003       The following options are available when as is configured for a RISC-V
2004       processor.
2005
2006       -fpic
2007       -fPIC
2008           Generate position-independent code
2009
2010       -fno-pic
2011           Don't generate position-independent code (default)
2012
2013       -march=ISA
2014           Select the base isa, as specified by ISA.  For example
2015           -march=rv32ima.  If this option and the architecture attributes
2016           aren't set, then assembler will check the default configure setting
2017           --with-arch=ISA.
2018
2019       -misa-spec=ISAspec
2020           Select the default isa spec version.  If the version of ISA isn't
2021           set by -march, then assembler helps to set the version according to
2022           the default chosen spec.  If this option isn't set, then assembler
2023           will check the default configure setting --with-isa-spec=ISAspec.
2024
2025       -mpriv-spec=PRIVspec
2026           Select the privileged spec version.  We can decide whether the CSR
2027           is valid or not according to the chosen spec.  If this option and
2028           the privilege attributes aren't set, then assembler will check the
2029           default configure setting --with-priv-spec=PRIVspec.
2030
2031       -mabi=ABI
2032           Selects the ABI, which is either "ilp32" or "lp64", optionally
2033           followed by "f", "d", or "q" to indicate single-precision, double-
2034           precision, or quad-precision floating-point calling convention, or
2035           none to indicate the soft-float calling convention.  Also, "ilp32"
2036           can optionally be followed by "e" to indicate the RVE ABI, which is
2037           always soft-float.
2038
2039       -mrelax
2040           Take advantage of linker relaxations to reduce the number of
2041           instructions required to materialize symbol addresses. (default)
2042
2043       -mno-relax
2044           Don't do linker relaxations.
2045
2046       -march-attr
2047           Generate the default contents for the riscv elf attribute section
2048           if the .attribute directives are not set.  This section is used to
2049           record the information that a linker or runtime loader needs to
2050           check compatibility.  This information includes ISA string, stack
2051           alignment requirement, unaligned memory accesses, and the major,
2052           minor and revision version of privileged specification.
2053
2054       -mno-arch-attr
2055           Don't generate the default riscv elf attribute section if the
2056           .attribute directives are not set.
2057
2058       -mcsr-check
2059           Enable the CSR checking for the ISA-dependent CRS and the read-only
2060           CSR.  The ISA-dependent CSR are only valid when the specific ISA is
2061           set.  The read-only CSR can not be written by the CSR instructions.
2062
2063       -mno-csr-check
2064           Don't do CSR checking.
2065
2066       -mlittle-endian
2067           Generate code for a little endian machine.
2068
2069       -mbig-endian
2070           Generate code for a big endian machine.
2071
2072       See the info pages for documentation of the RX-specific options.
2073
2074       The following options are available when as is configured for the s390
2075       processor family.
2076
2077       -m31
2078       -m64
2079           Select the word size, either 31/32 bits or 64 bits.
2080
2081       -mesa
2082       -mzarch
2083           Select the architecture mode, either the Enterprise System
2084           Architecture (esa) or the z/Architecture mode (zarch).
2085
2086       -march=processor
2087           Specify which s390 processor variant is the target, g5 (or arch3),
2088           g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10
2089           (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11),
2090           z14 (or arch12), z15 (or arch13), or z16 (or arch14).
2091
2092       -mregnames
2093       -mno-regnames
2094           Allow or disallow symbolic names for registers.
2095
2096       -mwarn-areg-zero
2097           Warn whenever the operand for a base or index register has been
2098           specified but evaluates to zero.
2099
2100       The following options are available when as is configured for a
2101       TMS320C6000 processor.
2102
2103       -march=arch
2104           Enable (only) instructions from architecture arch.  By default, all
2105           instructions are permitted.
2106
2107           The following values of arch are accepted: "c62x", "c64x", "c64x+",
2108           "c67x", "c67x+", "c674x".
2109
2110       -mdsbt
2111       -mno-dsbt
2112           The -mdsbt option causes the assembler to generate the
2113           "Tag_ABI_DSBT" attribute with a value of 1, indicating that the
2114           code is using DSBT addressing.  The -mno-dsbt option, the default,
2115           causes the tag to have a value of 0, indicating that the code does
2116           not use DSBT addressing.  The linker will emit a warning if objects
2117           of different type (DSBT and non-DSBT) are linked together.
2118
2119       -mpid=no
2120       -mpid=near
2121       -mpid=far
2122           The -mpid= option causes the assembler to generate the
2123           "Tag_ABI_PID" attribute with a value indicating the form of data
2124           addressing used by the code.  -mpid=no, the default, indicates
2125           position-dependent data addressing, -mpid=near indicates position-
2126           independent addressing with GOT accesses using near DP addressing,
2127           and -mpid=far indicates position-independent addressing with GOT
2128           accesses using far DP addressing.  The linker will emit a warning
2129           if objects built with different settings of this option are linked
2130           together.
2131
2132       -mpic
2133       -mno-pic
2134           The -mpic option causes the assembler to generate the "Tag_ABI_PIC"
2135           attribute with a value of 1, indicating that the code is using
2136           position-independent code addressing,  The "-mno-pic" option, the
2137           default, causes the tag to have a value of 0, indicating position-
2138           dependent code addressing.  The linker will emit a warning if
2139           objects of different type (position-dependent and position-
2140           independent) are linked together.
2141
2142       -mbig-endian
2143       -mlittle-endian
2144           Generate code for the specified endianness.  The default is little-
2145           endian.
2146
2147       The following options are available when as is configured for a TILE-Gx
2148       processor.
2149
2150       -m32 | -m64
2151           Select the word size, either 32 bits or 64 bits.
2152
2153       -EB | -EL
2154           Select the endianness, either big-endian (-EB) or little-endian
2155           (-EL).
2156
2157       The following option is available when as is configured for a Visium
2158       processor.
2159
2160       -mtune=arch
2161           This option specifies the target architecture.  If an attempt is
2162           made to assemble an instruction that will not execute on the target
2163           architecture, the assembler will issue an error message.
2164
2165           The following names are recognized: "mcm24" "mcm" "gr5" "gr6"
2166
2167       The following options are available when as is configured for an Xtensa
2168       processor.
2169
2170       --text-section-literals | --no-text-section-literals
2171           Control the treatment of literal pools.  The default is
2172           --no-text-section-literals, which places literals in separate
2173           sections in the output file.  This allows the literal pool to be
2174           placed in a data RAM/ROM.  With --text-section-literals, the
2175           literals are interspersed in the text section in order to keep them
2176           as close as possible to their references.  This may be necessary
2177           for large assembly files, where the literals would otherwise be out
2178           of range of the "L32R" instructions in the text section.  Literals
2179           are grouped into pools following ".literal_position" directives or
2180           preceding "ENTRY" instructions.  These options only affect literals
2181           referenced via PC-relative "L32R" instructions; literals for
2182           absolute mode "L32R" instructions are handled separately.
2183
2184       --auto-litpools | --no-auto-litpools
2185           Control the treatment of literal pools.  The default is
2186           --no-auto-litpools, which in the absence of --text-section-literals
2187           places literals in separate sections in the output file.  This
2188           allows the literal pool to be placed in a data RAM/ROM.  With
2189           --auto-litpools, the literals are interspersed in the text section
2190           in order to keep them as close as possible to their references,
2191           explicit ".literal_position" directives are not required.  This may
2192           be necessary for very large functions, where single literal pool at
2193           the beginning of the function may not be reachable by "L32R"
2194           instructions at the end.  These options only affect literals
2195           referenced via PC-relative "L32R" instructions; literals for
2196           absolute mode "L32R" instructions are handled separately.  When
2197           used together with --text-section-literals, --auto-litpools takes
2198           precedence.
2199
2200       --absolute-literals | --no-absolute-literals
2201           Indicate to the assembler whether "L32R" instructions use absolute
2202           or PC-relative addressing.  If the processor includes the absolute
2203           addressing option, the default is to use absolute "L32R"
2204           relocations.  Otherwise, only the PC-relative "L32R" relocations
2205           can be used.
2206
2207       --target-align | --no-target-align
2208           Enable or disable automatic alignment to reduce branch penalties at
2209           some expense in code size.    This optimization is enabled by
2210           default.  Note that the assembler will always align instructions
2211           like "LOOP" that have fixed alignment requirements.
2212
2213       --longcalls | --no-longcalls
2214           Enable or disable transformation of call instructions to allow
2215           calls across a greater range of addresses.    This option should be
2216           used when call targets can potentially be out of range.  It may
2217           degrade both code size and performance, but the linker can
2218           generally optimize away the unnecessary overhead when a call ends
2219           up within range.  The default is --no-longcalls.
2220
2221       --transform | --no-transform
2222           Enable or disable all assembler transformations of Xtensa
2223           instructions, including both relaxation and optimization.  The
2224           default is --transform; --no-transform should only be used in the
2225           rare cases when the instructions must be exactly as specified in
2226           the assembly source.  Using --no-transform causes out of range
2227           instruction operands to be errors.
2228
2229       --rename-section oldname=newname
2230           Rename the oldname section to newname.  This option can be used
2231           multiple times to rename multiple sections.
2232
2233       --trampolines | --no-trampolines
2234           Enable or disable transformation of jump instructions to allow
2235           jumps across a greater range of addresses.    This option should be
2236           used when jump targets can potentially be out of range.  In the
2237           absence of such jumps this option does not affect code size or
2238           performance.  The default is --trampolines.
2239
2240       --abi-windowed | --abi-call0
2241           Choose ABI tag written to the ".xtensa.info" section.  ABI tag
2242           indicates ABI of the assembly code.  A warning is issued by the
2243           linker on an attempt to link object files with inconsistent ABI
2244           tags.  Default ABI is chosen by the Xtensa core configuration.
2245
2246       The following options are available when as is configured for an Z80
2247       processor.
2248
2249       @chapter Z80 Dependent Features
2250
2251   Command-line Options
2252       -march=CPU[-EXT...][+EXT...]
2253           This option specifies the target processor. The assembler will
2254           issue an error message if an attempt is made to assemble an
2255           instruction which will not execute on the target processor. The
2256           following processor names are recognized: "z80", "z180", "ez80",
2257           "gbz80", "z80n", "r800".  In addition to the basic instruction set,
2258           the assembler can be told to accept some extention mnemonics. For
2259           example, "-march=z180+sli+infc" extends z180 with SLI instructions
2260           and IN F,(C). The following extentions are currently supported:
2261           "full" (all known instructions), "adl" (ADL CPU mode by default,
2262           eZ80 only), "sli" (instruction known as SLI, SLL or SL1), "xyhl"
2263           (instructions with halves of index registers: IXL, IXH, IYL, IYH),
2264           "xdcb" (instructions like RotOp (II+d),R and BitOp n,(II+d),R),
2265           "infc" (instruction IN F,(C) or IN (C)), "outc0" (instruction OUT
2266           (C),0).  Note that rather than extending a basic instruction set,
2267           the extention mnemonics starting with "-" revoke the respective
2268           functionality: "-march=z80-full+xyhl" first removes all default
2269           extentions and adds support for index registers halves only.
2270
2271           If this option is not specified then "-march=z80+xyhl+infc" is
2272           assumed.
2273
2274       -local-prefix=prefix
2275           Mark all labels with specified prefix as local. But such label can
2276           be marked global explicitly in the code. This option do not change
2277           default local label prefix ".L", it is just adds new one.
2278
2279       -colonless
2280           Accept colonless labels. All symbols at line begin are treated as
2281           labels.
2282
2283       -sdcc
2284           Accept assembler code produced by SDCC.
2285
2286       -fp-s=FORMAT
2287           Single precision floating point numbers format. Default: ieee754
2288           (32 bit).
2289
2290       -fp-d=FORMAT
2291           Double precision floating point numbers format. Default: ieee754
2292           (64 bit).
2293

SEE ALSO

2295       gcc(1), ld(1), and the Info entries for binutils and ld.
2296
2298       Copyright (c) 1991-2023 Free Software Foundation, Inc.
2299
2300       Permission is granted to copy, distribute and/or modify this document
2301       under the terms of the GNU Free Documentation License, Version 1.3 or
2302       any later version published by the Free Software Foundation; with no
2303       Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
2304       Texts.  A copy of the license is included in the section entitled "GNU
2305       Free Documentation License".
2306
2307
2308
2309binutils-2.40                     2023-07-30                             AS(1)
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