1DPGEN_RF1(3)            Alliance - genlib User's Manual           DPGEN_RF1(3)
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NAME

6       DPGEN_RF1, DPGEN_RF1R0 - Register File Macro-Generator
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SYNOPSIS

9       #include  <genlib.h>
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11       void GENLIB_MACRO (DPGEN_RF1, char *modelname, long flags, long N);
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13       void GENLIB_MACRO (DPGEN_RF1R0, char *modelname, long flags, long N);
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DESCRIPTION

16       Generate  a  register file of regNumber words of N bits whitout decoder
17       named modelname. The DPGEN_RF1R0 variant differs from the DPGEN_RF1  in
18       that  the register of address zero is stuck to zero. You can write into
19       it, it will not change the value. When  read,  it  will  always  return
20       zero.
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22       How it works :
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24       · datain0 and datain1 : the two write busses. Only one is used to actu‐
25         ally write the register word, it is selected by the sel signal.
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27       · sel : when set to '0' the datain0 is used to write the register word,
28         otherwise it will be datain1.
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30       · selr,  selw  : this register file have no decoder, so selr have a bus
31         width equal to regNumber. One bit for each word.
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33   TERMINAL NAMES
34       1. ckok : clock signal (input, 1 bit).
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36       2. sel : select the write bus (input, 1 bit).
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38       3. selr : the decoded read address (input, regNumber bits).
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40       4. selw : the decoded write address (input, regNumber bits).
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42       5. datain0 :  first write bus (input, N bits).
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44       6. datain1 :  second write bus (input, N bits).
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46       7. dataout : read bus (output, N bits).
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48       8. vdd : power.
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50       9. vss : ground.
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EXAMPLE

53       GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32"
54                             , F_BEHAV|F_PLACE
55                             , 32  /* Words size.      */
56                             , 8   /* Number of words. */
57                             );
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59       GENLIB_LOINS( "model_rf1x8_32"
60                   , "instance1_rf1_32"
61                   , "ckok"
62                   , "sel"
63                   , "selr[7:0]"
64                   , "selw[7:0]"
65                   , "datain0[31:0]"
66                   , "datain1[31:0]"
67                   , "dataout[31:0]"
68                   , "vdd", "vss", NULL
69                   );
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SEE ALSO

73       GENLIB_MACRO(3), genlib(1)
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77ASIM/LIP6                        30 July 2004                     DPGEN_RF1(3)
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