1TBLGEN(1) LLVM TBLGEN(1)
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6 tblgen - Target Description To C++ Code Generator
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9 tblgen [options] [filename]
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12 tblgen translates from target description (.td) files into C++ code
13 that can be included in the definition of an LLVM target library. Most
14 users of LLVM will not need to use this program. It is only for
15 assisting with writing an LLVM target backend.
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17 The input and output of tblgen is beyond the scope of this short intro‐
18 duction; please see the introduction to TableGen.
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20 The filename argument specifies the name of a Target Description (.td)
21 file to read as input.
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24 -help Print a summary of command line options.
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26 -o filename
27 Specify the output file name. If filename is -, then tblgen
28 sends its output to standard output.
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30 -I directory
31 Specify where to find other target description files for inclu‐
32 sion. The directory value should be a full or partial path to a
33 directory that contains target description files.
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35 -asmparsernum N
36 Make -gen-asm-parser emit assembly writer number N.
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38 -asmwriternum N
39 Make -gen-asm-writer emit assembly writer number N.
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41 -class className
42 Print the enumeration list for this class.
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44 -print-records
45 Print all records to standard output (default).
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47 -print-enums
48 Print enumeration values for a class.
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50 -print-sets
51 Print expanded sets for testing DAG exprs.
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53 -gen-emitter
54 Generate machine code emitter.
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56 -gen-register-info
57 Generate registers and register classes info.
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59 -gen-instr-info
60 Generate instruction descriptions.
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62 -gen-asm-writer
63 Generate the assembly writer.
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65 -gen-disassembler
66 Generate disassembler.
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68 -gen-pseudo-lowering
69 Generate pseudo instruction lowering.
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71 -gen-dag-isel
72 Generate a DAG (Directed Acycle Graph) instruction selector.
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74 -gen-asm-matcher
75 Generate assembly instruction matcher.
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77 -gen-dfa-packetizer
78 Generate DFA Packetizer for VLIW targets.
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80 -gen-fast-isel
81 Generate a "fast" instruction selector.
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83 -gen-subtarget
84 Generate subtarget enumerations.
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86 -gen-intrinsic
87 Generate intrinsic information.
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89 -gen-tgt-intrinsic
90 Generate target intrinsic information.
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92 -gen-enhanced-disassembly-info
93 Generate enhanced disassembly info.
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95 -version
96 Show the version number of this program.
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99 If tblgen succeeds, it will exit with 0. Otherwise, if an error
100 occurs, it will exit with a non-zero value.
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103 Maintained by The LLVM Team (http://llvm.org/).
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106 2003-2020, LLVM Project
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1115 2020-01-29 TBLGEN(1)