Verilog::Netlist::Cell(3pm)

1Netlist::Cell(3)      User Contributed Perl Documentation     Netlist::Cell(3)
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NAME

6       Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
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SYNOPSIS

9         use Verilog::Netlist;
10
11         ...
12         my $cell = $module->find_cell('cellname');
13         print $cell->name;
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DESCRIPTION

16       A Verilog::Netlist::Cell object is created by Verilog::Netlist for
17       every instantiation in the current module.
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ACCESSORS

20       See also Verilog::Netlist::Subclass for additional accessors and
21       methods.
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23       $self->comment
24           Returns any comments following the definition.  keep_comments=>1
25           must be passed to Verilog::Netlist::new for comments to be
26           retained.
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28       $self->delete
29           Delete the cell from the module it's under.
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31       $self->gateprim
32           True if the cell is a gate primitive instantiation (buf/cmos/etc),
33           but not a UDP.
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35       $self->module
36           Pointer to the module the cell is in.
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38       $self->name
39           The instantiation name of the cell.
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41       $self->netlist
42           Reference to the Verilog::Netlist the cell is under.
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44       $self->pins
45           List of Verilog::Netlist::Pin connections for the cell.
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47       $self->pins_sorted
48           List of name sorted Verilog::Netlist::Pin connections for the cell.
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50       $self->range
51           The range for the cell (e.g. "[1:0]") or false (i.e. undef or "")
52           if not ranged.
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54       $self->submod
55           Reference to the Verilog::Netlist::Module the cell instantiates.
56           Only valid after the design is linked.
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58       $self->submodname
59           The module name the cell instantiates (under the cell).
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MEMBER FUNCTIONS

62       See also Verilog::Netlist::Subclass for additional accessors and
63       methods.
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65       $self->lint
66           Checks the cell for errors.  Normally called by
67           Verilog::Netlist::lint.
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69       $self->new_pin
70           Creates a new Verilog::Netlist::Pin connection for this cell.
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72       $self->pins_sorted
73           Returns all Verilog::Netlist::Pin connections for this cell.
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75       $self->dump
76           Prints debugging information for this cell.
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DISTRIBUTION

79       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
80       EDA software tool suite.  The latest version is available from CPAN and
81       from <https://www.veripool.org/verilog-perl>.
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83       Copyright 2000-2020 by Wilson Snyder.  This package is free software;
84       you can redistribute it and/or modify it under the terms of either the
85       GNU Lesser General Public License Version 3 or the Perl Artistic
86       License Version 2.0.
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AUTHORS

89       Wilson Snyder <wsnyder@wsnyder.org>
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