1EditFiles(3)          User Contributed Perl Documentation         EditFiles(3)
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NAME

6       Verilog::EditFiles - Split Verilog modules into separate files.
7

SYNOPSIS

9       See splitmodule command.
10
11          use Verilog::EditFiles;
12          my $split = Verilog::EditFiles->new
13              (outdir => "processed_rtl",
14               translate_synthesis => 0,
15               lint_header => undef,
16               celldefine => 1,
17               );
18          $split->read_and_split(glob("inbound_rtl/*.v"));
19          $split->write_files();
20          $split->edit_file(filename=>"foo", cb => sub { return $_[0]; });
21

DESCRIPTION

23       Verilog::EditFiles provides a easy way to split library Verilog files
24       that contain multiple modules into many files with one module per file.
25

FUNCTIONS

27       new (...)
28           Create a new Verilog::EditFiles object.  Named parameters may be
29           specified:
30
31           celldefine
32               If true, add "`celldefine" before every module statement.
33
34           lint_command
35               For the write_lint method, the name of the linter to use.
36               Defaults to "vlint --brief".
37
38           lint_header
39               If defined, add the provided text before every module
40               statement.  Generally used to insert lint off pragmas.
41
42           outdir
43               Name of the directory to write the output modules to.  Defaults
44               to ".".
45
46           program
47               Name of the program to add to comments.  Defaults to
48               "Verilog::EditFiles".
49
50           timescale_header
51               If defined, add the provided text before every module
52               statement.  Generally set to the next needed to #include a
53               timescale file.  Use with timescale_removal.
54
55           timescale_removal
56               If set, remove any `timescales.
57
58           translate_synthesis
59               If 1, replace any synopsys translate on/offs with "`ifdef
60               SYNTHESIS" and "`endif"s.  If set to a string, use that string
61               instead of "SYNTHESIS".
62
63           v_suffix
64               The suffix to add to convert a module name into a filename.
65               Defaults to ".v".
66
67           verbose
68               If true, print what files are being read and written.
69
70       $self->read_and_split([filenames])
71           Read from the specified filenames.
72
73           If there is no module statement in the file, assume it is a include
74           file, and when write_files is called, place all of the file
75           contents into the output.  If there is a module statement, when
76           write_files is called place all following output into a file named
77           based on the module, with .v added.
78
79       $self->write_files()
80           Write all of the files created by read_and_split to the outdir.
81
82       $self->write_lint([filename=>...])
83           Create a shell script that will lint every file created by
84           write_files.  If a "filename" parameter is not provided, "0LINT.sh"
85           will be written in the default outdir.
86
87       $self->edit_file(filename=>..., cb=>sub{...})
88           Read a file, edit it with the provided callback, and save it if it
89           has changed.  The "filename" parameter is the filename to read.
90           The "write_filename" parameter is the filename to write, defaulting
91           to the same name as the filename to read.  The "cb" parameter is a
92           reference to a callback which takes the string of file contents and
93           returns the string to write back.  Often the callback will simply
94           perform a search and replace.
95

DISTRIBUTION

97       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog
98       EDA software tool suite.  The latest version is available from CPAN and
99       from <https://www.veripool.org/verilog-perl>.
100
101       Copyright 2006-2021 by Wilson Snyder.  This package is free software;
102       you can redistribute it and/or modify it under the terms of either the
103       GNU Lesser General Public License Version 3 or the Perl Artistic
104       License Version 2.0.
105

AUTHORS

107       Wilson Snyder <wsnyder@wsnyder.org>
108

SEE ALSO

110       Verilog-Perl
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114perl v5.32.1                      2021-04-14                      EditFiles(3)
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