1RDTSET(8) System Manager's Manual RDTSET(8)
2
6 rtdset - Task CPU affinity and Intel(R) Resource Director Technol‐
7 ogy/AMD PQoS control tool
8
10 rdtset -t <feature=value;...cpu=cpulist>... -c <cpulist> [-I] (-p
11 <pidlist> | [-k] cmd [<args>...])
12 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... -c <cpulist>
13 [-I] (-p <pidlist> | [-k] cmd [<args>...])
14 rdtset -r <cpulist> -c <cpulist> (-p <pidlist> | [-k] cmd [<args>...])
15 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... [-I] -p
16 <pidlist>
17 rdtset -t <feature=value> -I [-c <cpulist>] (-p <pidlist> | [-k] cmd
18 [<args>...])
19
21 For more details on Intel(R) Resource Director Technology see
22 http://www.intel.com/content/www/us/en/ architecture-and-technol‐
23 ogy/resource-director-technology.html
24 or https://github.com/intel/intel-cmt-cat/wiki
25 The rdtset tool provides support to set up the CAT (Cache Allocation
27 Technology) and MBA (Memory Bandwidth Allocation) capabilities for a
28 task and set its CPU affinity. For MBA, rdtset offers two modes of
29 operation, fixed MBA rate or closed-loop one monitoring local memory
30 B/W usage and adjust MBA accordingly. For OS interface, it uses MBA
31 CTRL via libpqos (OS support available in Linux kernel 4.18 or later).
32 For MSRs, the tool adjusts MBA configuration by itself based on local
33 memory B/W. Intel(R) RDT/AMD PQoS allocation operations of the utility
34 are done via libpqos library. Class of service 0 (CLOS0) is assumed as
35 default one. In command mode, rdtset forks and one process executes the
36 command. Another process waits for the task to terminate and restores
37 default allocation state by assigning cpu's back to CLOS0. This behav‐
38 ior is not in place in PID mode.
39
41 rdtset options are as follow:
42 -h, --help
44 Show help
45 -v, --verbose
47 Verbose mode
48 -I, --iface-os
50 Set the library to use the kernel implementation. If not set the
51 default implementation is to program the MSR's directly.
52 -t --rdt feature=value;...cpu=cpulist
54 Specify Intel(R) RDT configuration, single class configuration
55 per -t, multiple -t options allowed.
56 Accepted values for features:
57 2, l2 for level 2 cache
58 3, l3 for level 3 cache
59 m, mba for MBA
60 b, mba_max for max allowable local memory bandwidth
61 For example:
63 -t 'l3=0xf;cpu=1'
65 CPU 1 uses four L3 cache-ways (mask 0xf)
66 -t 'l3=0xf;cpu=2' -t 'l3=0xf0;cpu=3,4,5'
68 CPU 2 uses four L3 cache-ways (mask 0xf), CPUs 3-5 share four L3
69 cache-ways (mask 0xf0), L3 cache-ways used by CPU 2 and 3-5 are
70 non-overlapping
71 -t 'l3=0xf;cpu=0-2' -t 'l3=0xf0;cpu=3,4,5'
73 CPUs 0-2 share four L3 cache-ways (mask 0xf), CPUs 3-5 share
74 four L3 cache-ways (mask 0xf0), L3 cache-ways used by CPUs 0-2
75 and 3-5 are non-overlapping
76 -t 'l3=0xf,0xf0;cpu=1'
78 On CDP enabled system, CPU 1 uses four cache-ways for code (mask
79 0xf) and four cache-ways for data (mask 0xf0), data and code
80 cache-ways are non-overlapping
81 -t 'mba=70;cpu=0-2'
83 CPUs 0-2 can utilize up to 70% of available memory bandwidth
84 -t 'mba=50;l3=0xf;cpu=1'
86 CPU 1 uses four L3 (mask 0xf) cache-ways and can utilize up to
87 50% of available memory bandwidth
88 -t 'mba_max=2000;cpu=1-2' Use SW controller to limit local mem‐
90 ory B/W on cores 1-2 to 2000MBps (SW controller uses MBL moni‐
91 toring and adjust MBA rate).
92 Example PID type allocation configuration (requires -I option):
94 -t 'l3=0xf'
96 Allocate four L3 (mask 0xf) cache-ways to specified PIDs (-p
97 option) or command
98 -t 'l3=0xf;cpu=1;l3=0x1'
100 CPU 1 uses four L3 (mask 0xf) cache-ways
101 Specified PIDs (-p option) or command uses one L3 (mask 0x1)
102 cache-way
103 -c <cpulist>, --cpu <cpulist>
106 Specify CPU affinity configuration, a numerical list of proces‐
107 sors. The numbers are separated by commas and may include
108 ranges. For example: 1-3,4,5.
109 -p <pidlist>, --pid <pidlist>
111 Operate on existing PIDs
112 -r <cpulist>, --reset <cpulist>
114 Reset allocation for CPUs (assign COS#0 to listed CPUs)
115 For example:
116 -r 0-5
118 Reset allocation for CPUs 0-5
119 -r 0-5 -t 'l3=0xf0;cpu=0-5' -c 0-5 -p $BASHPID
121 Reconfigure allocation for CPUs 0-5
122 In order to reconfigure allocation, it is needed to reset cur‐
123 rent configuration
124 -k, --sudokeep
127 Do not drop sudo elevated privileges
128
130 Without --iface-os (-I) parameter, CAT and MBA are configured using
131 Model Specific Registers (MSRs) to set up the class of service masks
132 and manage the association of the cores/logical threads to a class of
133 service. The rdtset software executes in user space, and access to the
134 MSRs is obtained through a standard Linux*/FreeBSD* interface. Under
135 Linux, the virtual file system structure /dev/cpu/CPUNUM/msr provides
136 an interface to read and write the MSRs, under FreeBSD it is
137 /dev/cpuctlCPUNUM. The msr/cpuctl file interface is protected and
138 requires root privileges. The msr/cpuctl driver might not be auto-
139 loaded and on some modular kernels the driver may need to be loaded
140 manually:
141 Under Linux:
143 sudo modprobe msr
144 Under FreeBSD:
146 sudo kldload cpuctl
147 Interface enforcement:
149 If you require system wide interface enforcement you can do so by set‐
150 ting the "RDT_IFACE" environment variable.
151 OS interface (--iface-os, -I)
153 With --iface-os (-I) parameter, rdtset uses resctrl filesystem
154 (/sys/fs/resctrl) instead of accessing MSRs directly.
155
157 msr(4)
158
160 rdtset was written by Wojciech Andralojc <woj‐
161 ciechx.andralojc@intel.com>, Tomasz Kantecki <tomasz.kan‐
162 tecki@intel.com>, Michal Aleksinski <michalx.aleksinski@intel.com>,
163 Marcel Cornu <marcel.d.cornu@intel.com>
164 This is free software; see the source for copying conditions. There is
166 NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
167 PURPOSE.
168 January 10, 2019 RDTSET(8)