1RDTSET(8) System Manager's Manual RDTSET(8)
2
6 rtdset - Task CPU affinity and Intel(R) Resource Director Technol‐
7 ogy/AMD PQoS control tool
8
10 rdtset -t <feature=value;...cpu=cpulist>... -c <cpulist> [-I] (-p
11 <pidlist> | [-k] cmd [<args>...])
12 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... -c <cpulist>
13 [-I] (-p <pidlist> | [-k] cmd [<args>...])
14 rdtset -r <cpulist> -c <cpulist> (-p <pidlist> | [-k] cmd [<args>...])
15 rdtset -r <cpulist> -t <feature=value;...cpu=cpulist>... [-I] -p
16 <pidlist>
17 rdtset -t <feature=value> -I [-c <cpulist>] (-p <pidlist> | [-k] cmd
18 [<args>...])
19
21 For more details on Intel(R) Resource Director Technology see
22 http://www.intel.com/content/www/us/en/ architecture-and-technology/re‐
23 source-director-technology.html
24 or https://github.com/intel/intel-cmt-cat/wiki
25 The rdtset tool provides support to set up the CAT (Cache Allocation
27 Technology) and MBA (Memory Bandwidth Allocation) capabilities for a
28 task and set its CPU affinity. For MBA, rdtset offers two modes of op‐
29 eration, fixed MBA rate or closed-loop one monitoring local memory B/W
30 usage and adjust MBA accordingly. For OS interface, it uses MBA CTRL
31 via libpqos (OS support available in Linux kernel 4.18 or later). For
32 MSRs, the tool adjusts MBA configuration by itself based on local mem‐
33 ory B/W. Intel(R) RDT/AMD PQoS allocation operations of the utility
34 are done via libpqos library. Class of service 0 (CLOS0) is assumed as
35 default one. In command mode, rdtset forks and one process executes the
36 command. Another process waits for the task to terminate and restores
37 default allocation state by assigning cpu's back to CLOS0. This behav‐
38 ior is not in place in PID mode.
39
41 rdtset options are as follow:
42 -h, --help
44 Show help
45 -v, --verbose
47 Verbose mode
48 -I, --iface-os
50 Set the library to use the kernel implementation. If not set the
51 default implementation is to detect the interface automatically
52 (MSR or kernel).
53 -F <interface>, --iface <interface>
55 Set the library interface to automatically detected one
56 ('auto'), MSR ('msr') or kernel interface ('os').
57 <interface> can be set to either 'auto' (default), 'msr' or
58 'os'.
59 If automatic detection is selected ('auto'), it:
60 1) Takes RDT_IFACE environment variable into account if this
61 variable is set
62 2) Selects OS interface if the kernel interface is supported
63 3) Selects MSR interface otherwise
64 -t --rdt feature=value;...cpu=cpulist
66 Specify Intel(R) RDT configuration, single class configuration
67 per -t, multiple -t options allowed.
68 Accepted values for features:
69 2, l2 for level 2 cache
70 3, l3 for level 3 cache
71 m, mba for MBA
72 b, mba_max for max allowable local memory bandwidth
73 For example:
75 -t 'l3=0xf;cpu=1'
77 CPU 1 uses four L3 cache-ways (mask 0xf)
78 -t 'l3=0xf;cpu=2' -t 'l3=0xf0;cpu=3,4,5'
80 CPU 2 uses four L3 cache-ways (mask 0xf), CPUs 3-5 share four L3
81 cache-ways (mask 0xf0), L3 cache-ways used by CPU 2 and 3-5 are
82 non-overlapping
83 -t 'l3=0xf;cpu=0-2' -t 'l3=0xf0;cpu=3,4,5'
85 CPUs 0-2 share four L3 cache-ways (mask 0xf), CPUs 3-5 share
86 four L3 cache-ways (mask 0xf0), L3 cache-ways used by CPUs 0-2
87 and 3-5 are non-overlapping
88 -t 'l3=0xf,0xf0;cpu=1'
90 On CDP enabled system, CPU 1 uses four cache-ways for code (mask
91 0xf) and four cache-ways for data (mask 0xf0), data and code
92 cache-ways are non-overlapping
93 -t 'mba=70;cpu=0-2'
95 CPUs 0-2 can utilize up to 70% of available memory bandwidth
96 -t 'mba=50;l3=0xf;cpu=1'
98 CPU 1 uses four L3 (mask 0xf) cache-ways and can utilize up to
99 50% of available memory bandwidth
100 -t 'mba_max=2000;cpu=1-2' Use SW controller to limit local mem‐
102 ory B/W on cores 1-2 to 2000MBps (SW controller uses MBL moni‐
103 toring and adjust MBA rate).
104 Example PID type allocation configuration (requires -I option):
106 -t 'l3=0xf'
108 Allocate four L3 (mask 0xf) cache-ways to specified PIDs (-p op‐
109 tion) or command
110 -t 'l3=0xf;cpu=1;l3=0x1'
112 CPU 1 uses four L3 (mask 0xf) cache-ways
113 Specified PIDs (-p option) or command uses one L3 (mask 0x1)
114 cache-way
115 -c <cpulist>, --cpu <cpulist>
118 Specify CPU affinity configuration, a numerical list of proces‐
119 sors. The numbers are separated by commas and may include
120 ranges. For example: 1-3,4,5.
121 -p <pidlist>, --pid <pidlist>
123 Operate on existing PIDs
124 -r <cpulist>, --reset <cpulist>
126 Reset allocation for CPUs (assign COS#0 to listed CPUs)
127 For example:
128 -r 0-5
130 Reset allocation for CPUs 0-5
131 -r 0-5 -t 'l3=0xf0;cpu=0-5' -c 0-5 -p $BASHPID
133 Reconfigure allocation for CPUs 0-5
134 In order to reconfigure allocation, it is needed to reset cur‐
135 rent configuration
136 -k, --sudokeep
139 Do not drop sudo elevated privileges
140
142 If kernel interface is not selected neither manually (e.g. --iface=msr)
143 nor automatically, CAT and MBA are configured using Model Specific Reg‐
144 isters (MSRs) to set up the class of service masks and manage the asso‐
145 ciation of the cores/logical threads to a class of service. The rdtset
146 software executes in user space, and access to the MSRs is obtained
147 through a standard Linux*/FreeBSD* interface. Under Linux, the virtual
148 file system structure /dev/cpu/CPUNUM/msr provides an interface to read
149 and write the MSRs, under FreeBSD it is /dev/cpuctlCPUNUM. The
150 msr/cpuctl file interface is protected and requires root privileges.
151 The msr/cpuctl driver might not be auto-loaded and on some modular ker‐
152 nels the driver may need to be loaded manually:
153 Under Linux:
155 sudo modprobe msr
156 Under FreeBSD:
158 sudo kldload cpuctl
159 Interface enforcement:
161 If you require system wide interface enforcement you can do so by set‐
162 ting the "RDT_IFACE" environment variable.
163 OS interface (--iface-os, -I)
165 With --iface-os (-I) parameter, rdtset uses resctrl filesystem
166 (/sys/fs/resctrl) instead of accessing MSRs directly.
167
169 msr(4)
170
172 rdtset was written by Wojciech Andralojc <wojciechx.andralojc@in‐
173 tel.com>, Tomasz Kantecki <tomasz.kantecki@intel.com>, Michal Aleksin‐
174 ski <michalx.aleksinski@intel.com>, Marcel Cornu <marcel.d.cornu@in‐
175 tel.com>
176 This is free software; see the source for copying conditions. There is
178 NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
179 PURPOSE.
180 January 10, 2019 RDTSET(8)