1LIBPFM(3)                  Linux Programmer's Manual                 LIBPFM(3)
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NAME

6       libpfm_intel_slm - support for Intel Silvermont core PMU
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SYNOPSIS

9       #include <perfmon/pfmlib.h>
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11       PMU name: slm
12       PMU desc: Intel Silvermont
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DESCRIPTION

16       The library supports the Intel Silvermont core PMU.
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MODIFIERS

20       The following modifiers are supported on Intel Silvermont processors:
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22       u      Measure  at  user level which includes privilege levels 1, 2, 3.
23              This corresponds to PFM_PLM3.  This is a boolean modifier.
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25       k      Measure at kernel level which includes privilege level  0.  This
26              corresponds to PFM_PLM0.  This is a boolean modifier.
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28       i      Invert  the  meaning  of  the  event. The counter will now count
29              cycles in which the event is not occurring. This  is  a  boolean
30              modifier
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32       e      Enable  edge  detection,  i.e., count only when there is a state
33              transition from no occurrence of  the  event  to  at  least  one
34              occurrence.  This  modifier must be combined with a counter mask
35              modifier (m) with a value greater or equal to one.   This  is  a
36              boolean modifier.
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38       c      Set  the  counter  mask value. The mask acts as a threshold. The
39              counter will count the number of cycles in which the  number  of
40              occurrences  of  the event is greater or equal to the threshold.
41              This is an integer modifier with values in the range [0:255].
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OFFCORE_RESPONSE events

45       Intel   Silvermont   provides   two   offcore_response   events:   OFF‐
46       CORE_RESPONSE_0 and OFFCORE_RESPONSE_1.
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48       Those  events  need special treatment in the performance monitoring in‐
49       frastructure because each event uses an extra register  to  store  some
50       settings.  Thus, in case multiple offcore_response events are monitored
51       simultaneously, the kernel needs to manage the sharing  of  that  extra
52       register.
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54       The  offcore_response  events  are  exposed  as  a  normal event by the
55       library. The extra settings are exposed as regular umasks. The  library
56       takes  care  of  encoding the events according to the underlying kernel
57       interface.
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59       On Intel Silvermont, the umasks  are  divided  into  three  categories:
60       request,  supplier  and snoop. The user must provide at least one umask
61       for each category. The categories are shown in the umask  descriptions.
62       The  library  provides  a default umask per category if not provided by
63       the user.
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65       There is also the special response umask called ANY_RESPONSE. When this
66       umask is used then it overrides any supplier and snoop umasks. In other
67       words, users can specify either ANY_RESPONSE  OR  any  combinations  of
68       supplier + snoops.
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70       In  case  no  supplier  or  snoop is specified, the library defaults to
71       using ANY_RESPONSE.
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73       For instance, the following are valid event selections:
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75       OFFCORE_RESPONSE_0:DMND_DATA_RD:ANY_RESPONSE
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77       OFFCORE_RESPONSE_0:ANY_REQUEST
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79       OFFCORE_RESPONSE_0:ANY_RFO:LLC_HITM:SNOOP_ANY
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82       But the following are illegal:
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85       OFFCORE_RESPONSE_0:ANY_RFO:NON_DRAM:ANY_RESPONSE
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87       OFFCORE_RESPONSE_0:ANY_RFO:L2_HIT:SNOOP_ANY:ANY_RESPONSE
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AUTHORS

91       Stephane Eranian <eranian@gmail.com>
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95                                November, 2013                       LIBPFM(3)