Verilog::CodeGen(3pm)

1CodeGen(3)            User Contributed Perl Documentation           CodeGen(3)
2
3
4

NAME

6       Verilog::CodeGen - Verilog code generator
7

SYNOPSIS

9         use Verilog::CodeGen;
10
11         mkdir 'DeviceLibs/Objects/YourDesign', 0755;
12         chdir 'DeviceLibs/Objects/YourDesign';
13
14         # if the directory YourDesign exists, the second argument can be omitted
15         # create YourModule.pl in YourDesign
16         &create_template_file('YourModule','YourDesign');
17
18         # create a device library for testing in DeviceLibs/Objects/DeviceLibs
19         &make_module('YourModule','YourDesign');
20
21         # create the final device library in DeviceLibs (once YourModule code is clean)
22         &make_module('','YourDesign');
23

USAGE

25       The most efficient way to use the code generator is using the GUI
26       ("gui.pl" in scripts in the distribution). Read the documentation in
27       Verilog::CodeGen::Gui.pm). Alternatively, you can use the scripts that
28       the GUI uses to do the work (in the scripts/GUI folder). If you want to
29       make your own, follow the SYNOPSIS.
30
31       Then edit the file YourModule.pl in the folder
32       DeviceLibs/Objects/YourDesign.
33
34       For example:
35
36               sub gen_YourModule {
37               my $objref=shift;
38               my $par=$objref->{parname}||1;
39
40               # Create Objects
41
42               my $submodule=new('SubModule',parname1=>$par);
43
44               # Instantiate
45
46               my $pins="(A,Z)";
47               my $modname=$objref->{modulename};
48               my $code = "
49               module $modname $pins;
50               input A;
51               output Z;
52               ";
53               $code.=$submodule->inst('suffix',P1=>'A');
54               $code .="
55               endmodule // $modname
56               ";
57               $objref->{pins}=$pins;
58               return $code;
59               } # END of gen_YourModule
60
61       Then run "perl YourModule.pl" to check if the code produces valid a
62       Verilog module.
63
64       If this is the case, add YourModule to the device library with
65       "&make_module()"
66
67       Next, create a testbench test_YourModule.pl in a directory on the same
68       level as DeviceLibs (TestObj if you use the GUI):
69
70               use lib '..';
71               use DeviceLibs::YourDesign;
72
73               my $device=new("S_buffer_demux",depth=>7,);
74
75               open (VER,">test_S_buffer_demux.v");
76
77               output(*VER);
78
79               modules();
80
81               print VER "
82               module test_S_buffer_demux;
83                  wire A;
84                  wire [7:0] S;
85                  wire [6:0] Z;
86                  wire D;
87
88                  reg a;
89                  reg [7:0] s;
90
91               assign    A=   a;
92               assign     S=    s;
93
94               reg _ck;
95               ";
96               $device->instance();
97               my $x=$device->{""};
98
99               print VER "
100               // clock generator
101               always begin: clock_wave
102                  #10 _ck = 0;
103                  #10 _ck = 1;
104
105               end
106
107               always @(posedge _ck)
108               begin
109               \$display(\" \%0d  \%b \%b \",\$time,$x.   Z,$x.   D);
110               end
111
112               initial
113               begin
114               \$display(\"Time     Z    D\");
115               a<=1;
116               #25;
117               a<=0;
118               #25;
119               \$finish;
120               end
121               endmodule
122               ";
123               close VER;
124               run("test_S_buffer_demux.v");
125               #plot("test_S_buffer_demux.v");
126
127       Execute the testbench script with "perl test_YourModule.pl".
128

DESCRIPTION

130       Provides an  object-oriented environment to generate Verilog code for
131       modules and testbenches. The Verilog::CodeGen module provides two
132       functions, one to create a code template and another to create a Perl
133       module which contains the device library. This module ,
134       DeviceLibs::YourDesign, provides the class methods and contains the
135       objects for every Verilog module; the objects are created based on a
136       fixed template.  The purpose of this module is to allow the generation
137       of customized Verilog modules. A Verilog module can have a large number
138       of parameters like input and output bus width, buffer depth, signal
139       delay etc. The code generator allows to create an object that will
140       generate the Verilog module code for arbitraty values of the
141       parameters.
142

UTILITY SCRIPTS

144       With the Perl module distribution come a number of utility scripts. The
145       most important one is gui.pl, a GUI frontend for Verilog development
146       using the code generator.
147

MAIN METHODS

149   new($object_name[,%attributes]);
150       Create a new Verilog module object. The object attributes are optional,
151       the object should provide reasonable defaults.
152
153   output([*filehandle_ref||$filename])
154       output() takes a reference to a filehandle or a filename as argument.
155       These are stored in the global %printcfg. Without arguments, this
156       defaults to STDOUT.  If output() is called with as argument a string
157       containing \n and/or \s, this string is printed on the current
158       filehandle.
159
160   modules
161       The code generator stores all submodules of a given module in the
162       global %modules. Calling modules() prints the code for these modules on
163       the current filehandle.
164
165   instance([$instance_suffix,%connectivity])
166       The instance() method will print the code for the instantiation of the
167       object on the current filehandle. An optional instance suffix can be
168       specified (to distinguish between different instances of the same
169       module), as well as the pin connectivity. If the connectivity for a pin
170       is not specified, it defaults to the pin name.
171
172   inst([$instance_suffix,%connectivity])
173       The inst() method will return the code for the instantiation of the
174       object as a string. An optional instance suffix can be specified (to
175       distinguish between different instances of the same module), as well as
176       the pin connectivity. If the connectivity for a pin is not specified,
177       it defaults to the pin name.
178
179   run([$filename])
180       Run the netlist through the Icarus Verilog (http://www.icarus.com) open
181       source verilog simulator. The filename is optional if it was specified
182       with the output() method.
183
184   plot([$filename])
185       Plot the result of the simulation with gtkwave. For this purpose, the
186       \$dumpvar and \$dumpfile compiler directives must be present in the
187       testbench code. The filename is optional if it was specified with the
188       output() method.
189
190   module('modulename')
191       This method can be used to print the code for a specified module on the
192       current filehandle.
193
194   search(/pattern/)
195       Search the verilog code for a given pattern.
196
197   find_inst(/pattern/)
198       Find all instances matching /pattern/ in the netlist.
199

MAIN ATTRIBUTES

201   {$instance_suffix}
202       Returns the full instance name of the object.
203       $x=$object->{$instance_suffix};
204

TODO

206       •   Convert the utility scripts to functions to be called from
207           Verilog::CodeGen.
208
209       •   Put the GUI scripts in a module Gui.pm.
210
211       •   Separate the code for testing purposes from the module object code.
212

AUTHOR

217       W. Vanderbauwhede wim@motherearth.org.
218
219       <http://www.comms.eee.strath.ac.uk/~wim>
220

COPYRIGHT

222       Copyright (c) 2002 Wim Vanderbauwhede. All rights reserved. This
223       program is free software; you can redistribute it and/or modify it
224       under the same terms as Perl itself.
225
226
227
228perl v5.34.0                      2021-07-27                        CodeGen(3)