1CTAGS-LANG-VERILOG(7) Universal Ctags CTAGS-LANG-VERILOG(7)
2
6 ctags-lang-verilog - The man page about SystemVerilog/Verilog parser
7 for Universal Ctags
8
10 ctags ... [--kinds-systemverilog=+Q] [--fields-SystemVerilog=+{parameter}] ...
11 ctags ... [--fields-Verilog=+{parameter}] ...
12 ┌──────────────┬───────────────┬────────────────┐
15 │Language │ Language ID │ File Mapping │
16 ├──────────────┼───────────────┼────────────────┤
17 │SystemVerilog │ SystemVerilog │ .sv, .svh, svi │
18 ├──────────────┼───────────────┼────────────────┤
19 │Verilog │ Verilog │ .v │
20 └──────────────┴───────────────┴────────────────┘
21
23 This man page describes about the SystemVerilog/Verilog parser for Uni‐
24 versal Ctags. SystemVerilog parser supports IEEE Std 1800-2017 key‐
25 words. Verilog parser supports IEEE Std 1364-2005 keywords.
26 Supported Kinds
28 $ ctags --list-kinds-full=SystemVerilog
29 #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION
30 A assert yes no 0 NONE assertions (assert, assume, cover, restrict)
31 C class yes no 0 NONE classes
32 E enum yes no 0 NONE enumerators
33 H checker yes no 0 NONE checkers
34 I interface yes no 0 NONE interfaces
35 K package yes no 0 NONE packages
36 L clocking yes no 0 NONE clocking
37 M modport yes no 0 NONE modports
38 N nettype yes no 0 NONE nettype declarations
39 O constraint yes no 0 NONE constraints
40 P program yes no 0 NONE programs
41 Q prototype no no 0 NONE prototypes (extern, pure)
42 R property yes no 0 NONE properties
43 S struct yes no 0 NONE structs and unions
44 T typedef yes no 0 NONE type declarations
45 V covergroup yes no 0 NONE covergroups
46 b block yes no 0 NONE blocks (begin, fork)
47 c constant yes no 0 NONE constants (define, parameter, specparam, enum values)
48 e event yes no 0 NONE events
49 f function yes no 0 NONE functions
50 i instance yes no 0 NONE instances of module or interface
51 l ifclass yes no 0 NONE interface class
52 m module yes no 0 NONE modules
53 n net yes no 0 NONE net data types
54 p port yes no 0 NONE ports
55 q sequence yes no 0 NONE sequences
56 r register yes no 0 NONE variable data types
57 t task yes no 0 NONE tasks
58 w member yes no 0 NONE struct and union members
59 Note that prototype (Q) is disabled by default.
61 $ ctags --list-kinds-full=Verilog
63 #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION
64 b block yes no 0 NONE blocks (begin, fork)
65 c constant yes no 0 NONE constants (define, parameter, specparam)
66 e event yes no 0 NONE events
67 f function yes no 0 NONE functions
68 i instance yes no 0 NONE instances of module
69 m module yes no 0 NONE modules
70 n net yes no 0 NONE net data types
71 p port yes no 0 NONE ports
72 r register yes no 0 NONE variable data types
73 t task yes no 0 NONE tasks
74 Supported Language Specific Fields
76 $ ctags --list-fields=Verilog
77 #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION
78 - parameter no Verilog --b no parameter whose value can be overridden.
79 $ ctags --list-fields=SystemVerilog
80 #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION
81 - parameter no SystemVerilog --b no parameter whose value can be overridden.
82 parameter field
84 If the field parameter is enabled, a field parameter: is added on a pa‐
85 rameter whose value can be overridden on an instantiated module, inter‐
86 face, or program. This is useful for a editor plugin or extension to
87 enable auto-instantiation of modules with parameters which can be over‐
88 ridden.
89 $ ctags ... --fields-Verilog=+{parameter} ...
91 $ ctags ... --fields-SystemVerilog=+{parameter} ...
92 On the following source code fields parameter: are added on parameters
94 P*, not on ones L*. Note that L4 and L6 is declared by parameter
95 statement, but fields parameter: are not added, because they cannot be
96 overridden.
97 "input.sv"
99 // compilation unit scope
101 parameter L1 = "synonym for the localparam";
102 module with_parameter_port_list #(
104 P1,
105 localparam L2 = P1+1,
106 parameter P2)
107 ( /*port list...*/ );
108 parameter L3 = "synonym for the localparam";
109 localparam L4 = "localparam";
110 // ...
111 endmodule
112 module with_empty_parameter_port_list #()
114 ( /*port list...*/ );
115 parameter L5 = "synonym for the localparam";
116 localparam L6 = "localparam";
117 // ...
118 endmodule
119 module no_parameter_port_list
121 ( /*port list...*/ );
122 parameter P3 = "parameter";
123 localparam L7 = "localparam";
124 // ...
125 endmodule
126 $ ctags -uo - --fields-SystemVerilog=+{parameter} input.sv
128 L1 input.sv /^parameter L1 = "synonym for the localparam";$/;" c parameter:
129 with_parameter_port_list input.sv /^module with_parameter_port_list #($/;" m
130 P1 input.sv /^ P1,$/;" c module:with_parameter_port_list parameter:
131 L2 input.sv /^ localparam L2 = P1+1,$/;" c module:with_parameter_port_list
132 P2 input.sv /^ parameter P2)$/;" c module:with_parameter_port_list parameter:
133 L3 input.sv /^ parameter L3 = "synonym for the localparam";$/;" c module:with_parameter_port_list
134 L4 input.sv /^ localparam L4 = "localparam";$/;" c module:with_parameter_port_list
135 with_empty_parameter_port_list input.sv /^module with_empty_parameter_port_list #()$/;" m
136 L5 input.sv /^ parameter L5 = "synonym for the localparam";$/;" c module:with_empty_parameter_port_list
137 L6 input.sv /^ localparam L6 = "localparam";$/;" c module:with_empty_parameter_port_list
138 no_parameter_port_list input.sv /^module no_parameter_port_list$/;" m
139 P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter:
140 L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list
141 TIPS
143 If you want to map files *.v to SystemVerilog, add --langmap=SystemVer‐
144 ilog:.v option.
145
147 See https://github.com/universal-ctags/ctags/issues/2674 for more in‐
148 formation.
149
151 • ctags(1)
152 • ctags-client-tools(7)
154 •
156 Language Reference Manuals (LRM)
158 • IEEE Standard for SystemVerilog — Unified Hardware Design,
160 Specification, and Verification Language, IEEE Std
161 1800-2017, https://ieeexplore.ieee.org/document/8299595
162 • IEEE Standard for Verilog Hardware Description Language,
164 IEEE Std 1364-2005,
165 https://ieeexplore.ieee.org/document/1620780
1665.9.0 CTAGS-LANG-VERILOG(7)