1CXL-RESERVE-DPA(1) CXL-RESERVE-DPA(1)
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6 cxl-reserve-dpa - allocate device-physical address space
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9 cxl reserve-dpa <mem0> [<mem1>..<memN>] [<options>]
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11 The CXL region provisioning process proceeds in multiple steps. One of
12 the steps is identifying and reserving the DPA span that each member of
13 the interleave-set (region) contributes in advance of attaching that
14 allocation to a region. For development, test, and debug purposes this
15 command is a helper to find the next available decoder on endpoint
16 (memdev) and mark a span of DPA as busy.
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19 <memory device(s)>
20 A memX device name, or a memdev id number. Restrict the operation
21 to the specified memdev(s). The keyword all can be specified to
22 indicate the lack of any restriction.
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24 -S, --serial
25 Rather an a memdev id number, interpret the <memdev> argument(s) as
26 a list of serial numbers.
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28 -d, --decoder
29 Specify the decoder to attempt the allocation. The CXL
30 specification mandates that allocations must be ordered by DPA and
31 decoder instance. I.e. the lowest DPA allocation on the device is
32 covered by decoder0, and the last / highest DPA allocation is
33 covered by the last decoder. This ordering is enforced by the
34 kernel. By default the tool picks the next available decoder.
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36 -t, --type
37 Select the partition for the allocation. CXL devices implement a
38 partition that divdes ram and pmem capacity, where pmem capacity
39 consumes the higher DPA capacity above the partition boundary. The
40 type defaults to pmem. Note that given CXL DPA allocation
41 constraints, once any pmem allocation is established then all
42 remaining ram capacity becomes reserved (skipped).
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44 -f, --force
45 The kernel enforces CXL DPA allocation ordering constraints, and
46 the tool anticipates those and fails operations that are expected
47 to fail without sending them to the kernel. For test purposes,
48 continue to attempt "expected to fail" operations to exercise the
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51 -s, --size
52 Specify the size of the allocation. This option supports the
53 suffixes "k" or "K" for KiB, "m" or "M" for MiB, "g" or "G" for GiB
54 and "t" or "T" for TiB. This defaults to "all available capacity of
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57 -v
58 Turn on verbose debug messages in the library (if libcxl was built
59 with logging and debug enabled).
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62 Copyright © 2016 - 2022, Intel Corporation. License GPLv2: GNU GPL
63 version 2 http://gnu.org/licenses/gpl.html. This is free software: you
64 are free to change and redistribute it. There is NO WARRANTY, to the
65 extent permitted by law.
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68 linkcxl:cxl-free-dpa[1]
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72 01/13/2023 CXL-RESERVE-DPA(1)