1Parser(3)             User Contributed Perl Documentation            Parser(3)
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NAME

6       Hardware::Vhdl::Parser - A complete grammar for parsing VHDL code using
7       perl
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SYNOPSIS

10         use Hardware::Vhdl::Parser;
11         $parser = new Hardware::Vhdl::Parser;
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13         $parser->Filename(@ARGV);
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DESCRIPTION

16       This module defines the complete grammar needed to parse any VHDL code.
17       By overloading this grammar, it is possible to easily create perl
18       scripts which run through VHDL code and perform specific functions.
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20       For example, a Hierarchy.pm uses Hardware::Vhdl::Parser to overload the
21       grammar rule for component instantiations. This single modification
22       will print out all instance names that occur in the file being parsed.
23       This might be useful for creating an automatic build script, or a
24       graphical hierarchical browser of a VHDL design.
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26       This module is currently in Beta release. All code is subject to
27       change.  Bug reports are welcome.
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29       DSLI information:
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31       D - Development Stage
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33               a - alpha testing
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35       S - Support Level
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37               d - developer
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39       L - Language used
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41               p - perl only, no compiler needed, should be platform independent
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43       I - Interface Style
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45               O - Object oriented using blessed references and / or inheritance
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AUTHOR

48       Copyright (C) 2000 Greg London   All Rights Reserved.
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50       This program is free software; you can redistribute it and/or modify it
51       under the same terms as Perl itself.
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53       email contact: greg42@bellatlantic.net
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SEE ALSO

56       Parse::RecDescent version 1.77
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58       perl(1).
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62perl v5.36.0                      2022-07-22                         Parser(3)