1OPENSSL_IA32CAP(3ossl)              OpenSSL             OPENSSL_IA32CAP(3ossl)
2
3
4

NAME

6       OPENSSL_ia32cap - the x86[_64] processor capabilities vector
7

SYNOPSIS

9        env OPENSSL_ia32cap=... <application>
10

DESCRIPTION

12       OpenSSL supports a range of x86[_64] instruction set extensions. These
13       extensions are denoted by individual bits in capability vector returned
14       by processor in EDX:ECX register pair after executing CPUID instruction
15       with EAX=1 input value (see Intel Application Note #241618). This
16       vector is copied to memory upon toolkit initialization and used to
17       choose between different code paths to provide optimal performance
18       across wide range of processors. For the moment of this writing
19       following bits are significant:
20
21       bit #4 denoting presence of Time-Stamp Counter.
22       bit #19 denoting availability of CLFLUSH instruction;
23       bit #20, reserved by Intel, is used to choose among RC4 code paths;
24       bit #23 denoting MMX support;
25       bit #24, FXSR bit, denoting availability of XMM registers;
26       bit #25 denoting SSE support;
27       bit #26 denoting SSE2 support;
28       bit #28 denoting Hyperthreading, which is used to distinguish cores
29       with shared cache;
30       bit #30, reserved by Intel, denotes specifically Intel CPUs;
31       bit #33 denoting availability of PCLMULQDQ instruction;
32       bit #41 denoting SSSE3, Supplemental SSE3, support;
33       bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
34       bit #54 denoting availability of MOVBE instruction;
35       bit #57 denoting AES-NI instruction set extension;
36       bit #58, XSAVE bit, lack of which in combination with MOVBE is used to
37       identify Atom Silvermont core;
38       bit #59, OSXSAVE bit, denoting availability of YMM registers;
39       bit #60 denoting AVX extension;
40       bit #62 denoting availability of RDRAND instruction;
41
42       For example, in 32-bit application context clearing bit #26 at run-time
43       disables high-performance SSE2 code present in the crypto library,
44       while clearing bit #24 disables SSE2 code operating on 128-bit XMM
45       register bank. You might have to do the latter if target OpenSSL
46       application is executed on SSE2 capable CPU, but under control of OS
47       that does not enable XMM registers. Historically address of the
48       capability vector copy was exposed to application through
49       OPENSSL_ia32cap_loc(), but not anymore. Now the only way to affect the
50       capability detection is to set OPENSSL_ia32cap environment variable
51       prior target application start. To give a specific example, on Intel P4
52       processor "env OPENSSL_ia32cap=0x16980010 apps/openssl", or better yet
53       "env OPENSSL_ia32cap=~0x1000000 apps/openssl" would achieve the desired
54       effect. Alternatively you can reconfigure the toolkit with no-sse2
55       option and recompile.
56
57       Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
58       variable" terms. The truth is that it's not copied from CPUID output
59       verbatim, but is adjusted to reflect whether or not the data cache is
60       actually shared between logical cores. This in turn affects the
61       decision on whether or not expensive countermeasures against cache-
62       timing attacks are applied, most notably in AES assembler module.
63
64       The capability vector is further extended with EBX value returned by
65       CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
66
67       bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
68       bit #64+5 denoting availability of AVX2 instructions;
69       bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and
70       RORX;
71       bit #64+16 denoting availability of AVX512F extension;
72       bit #64+17 denoting availability of AVX512DQ extension;
73       bit #64+18 denoting availability of RDSEED instruction;
74       bit #64+19 denoting availability of ADCX and ADOX instructions;
75       bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, aka
76       AVX512IFMA extension;
77       bit #64+29 denoting availability of SHA extension;
78       bit #64+30 denoting availability of AVX512BW extension;
79       bit #64+31 denoting availability of AVX512VL extension;
80       bit #64+41 denoting availability of VAES extension;
81       bit #64+42 denoting availability of VPCLMULQDQ extension;
82
83       To control this extended capability word use ":" as delimiter when
84       setting up OPENSSL_ia32cap environment variable. For example assigning
85       ":~0x20" would disable AVX2 code paths, and ":0" - all post-AVX
86       extensions.
87

RETURN VALUES

89       Not available.
90
92       Copyright 2004-2022 The OpenSSL Project Authors. All Rights Reserved.
93
94       Licensed under the Apache License 2.0 (the "License").  You may not use
95       this file except in compliance with the License.  You can obtain a copy
96       in the file LICENSE in the source distribution or at
97       <https://www.openssl.org/source/license.html>.
98
99
100
1013.1.1                             2023-08-31            OPENSSL_IA32CAP(3ossl)
Impressum