1ggGetSwarType(3)                      GGI                     ggGetSwarType(3)
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NAME

6       ggGetSwarType : Get CPU features
7

SYNOPSIS

9       #include <ggi/gg.h>
10
11       #if defined GG_HAVE_INT64
12       #endif
13
14       #if defined GG_LITTLE_ENDIAN
15       #endif
16
17       #if defined GG_BIG_ENDIAN
18       #endif
19
20       gg_swartype ggGetSwarType(void);
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22

DESCRIPTION

24       The GG_HAVE_INT64 macro is defined on 64-bit architectures where 64-bit
25       integer values function as normal integer  values  with  respect  to  C
26       operations.  Otherwise it is not defined.
27
28       The  GG_LITTLE_ENDIAN  or GG_BIG_ENDIAN are defined, respectively, when
29       the architecture stores values in little or big endian order.   One  of
30       the two will be defined, the other undefined, accordingly.
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32       SWAR stands for SIMD Within A Register.  The most well known example of
33       SWAR is Intel MMX technology.
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35       ggGetSwarType tells which specific SWAR instruction sets the CPU imple‐
36       ments.   This  is useful to choose at runtime a machine-specific imple‐
37       mentation of a very calculation-intensive routine.  SWAR  detection  is
38       done once during ggInit(3) and the value is cached for future use, thus
39       it should be fast enough to choose implementations on  the  fly.   How‐
40       ever, due to this, SMP machines must have identical feature sets in all
41       processors in order to ensure accurate results (see the GG_OPTS  option
42       description below.)
43

RETURN VALUE

45       ggGetSwarType  returns  an  integer  in which each bit set means that a
46       specific SWAR instruction set is available.  The integer value  may  be
47       32  bits  long or 64 bits long, depending on whether LibGG was compiled
48       for a 32-bit or 64-bit machine, as per the GG_HAVE_INT64 macro.
49

RECOGNIZED SWARS

51       The following flags are defined for all architectures.   All  of  these
52       flags  can be OR'ed and are exclusive even between architectures.  Note
53       at this stage of development some  of  these  SIMD  sets  are  not  yet
54       detected correctly.
55
56       GG_SWAR_NONE
57              The CPU can run a vanilla C program. (hopefully! :-)
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59
60       GG_SWAR_32BITC
61              The CPU can perform 32-bit math fast enough to give an advantage
62              over 16-bit math for software SWAR implementations.  Almost  all
63              computers will have this capability today.
64
65
66       GG_SWAR_ALTIVEC
67              The CPU has an AltiVec matrix coprocessor (Motorola G4.)
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69
70       GG_SWAR_SSE
71              The CPU supports Intel Streaming SIMD Extensions.
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74       GG_SWAR_SSE2
75              The CPU supports Intel Streaming SIMD Extensions Version 2.
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78       GG_SWAR_SSE3
79              The CPU supports Intel Streaming SIMD Extensions Version 3.
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81
82       GG_SWAR_MMX
83              The CPU supports Intel Multimedia Extensions.
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85
86       GG_SWAR_MMXPLUS
87              The  CPU  supports Cyrix enhancements to Intel Multimedia Exten‐
88              sions.
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90
91       GG_SWAR_3DNOW
92              The CPU supports AMD 3DNOW! instructions.
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95       GG_SWAR_ADV3DNOW
96              The CPU supports AMD Advanced 3DNOW! instructions.
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98
99       GG_SWAR_MAX
100              The CPU supports PA-RISC MAX Instructions.
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102
103       GG_SWAR_SIGD
104              The CPU supports Microunity Mediaprocessor SIGD instructions.
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106
107       Additionally, 64 bits architectures define the following flags:
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109       GG_SWAR_64BITC
110              The CPU can perform 64-bit math fast enough to give an advantage
111              over 32-bit and 16-bit math for software SWAR implementations.
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113
114       GG_SWAR_MVI
115              The CPU supports DEC (Compaq) Alpha Motion Video Instructions.
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117
118       GG_SWAR_MAX2
119              The CPU supports PA-RISC MAX2 Instructions.
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121
122       GG_SWAR_MDMX
123              The  CPU supports MIPS Digital Media Extension (MaDMaX) Instruc‐
124              tions.
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126
127       GG_SWAR_MAJC
128              The CPU supports SUN Microprocessor Architecture for  Java  Com‐
129              puting.
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131
132       GG_SWAR_VIS
133              The CPU supports the SUN Visual Instruction Set
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135

ENVIRONMENT VARIABLE

137       If the "-banswar=0xhexnumber" option is present in the GG_OPTS environ‐
138       ment variable when ggInit is first called, bits set in the  0xhexnumber
139       field  will  not be presented to the application in the return value of
140       ggGetSwarType.  This feature can be used for performance  benchmarking,
141       to  disable  the  use  of certain SWAR implementations.  It may also be
142       used if a multiproccesor machine mis-detects the usable  SWAR  instruc‐
143       tion set because the processors are not identical.
144

BUGS

146       No support is currently implemented for PDP endian machines.
147
148       SWAR  detection  code is incomplete for many architectures, and as such
149       LibGG may may fail to detect SWAR in the CPU.
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153libgg-1.0.x                       2005-08-26                  ggGetSwarType(3)
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