1EXT2SIM(1) General Commands Manual EXT2SIM(1)
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6 ext2sim - convert hierarchical ext(5) extracted-circuit files to flat
7 sim(5) files
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10 ext2sim [ -a aliasfile ] [ -l labelsfile ] [ -o simfile ] [ -A ] [ -B ]
11 [ -F ] [ -L ] [ -t ] [ extcheck-options ] [ -y num ] [ -f mit|lbl|su ]
12 [ -J hier|flat ] [ -j device:sdRclass[/subRclass]/defaultSubstrate ]
13 root
14
17 Ext2sim will convert an extracted circuit from the hierarchical ext(5)
18 representation produced by Magic to the flat sim(5) representation
19 required by many simulation tools. The root of the tree to be
20 extracted is the file root.ext; it and all the files it references are
21 recursively flattened. The result is a single, flat representation of
22 the circuit that is written to the file root.sim, a list of node
23 aliases written to the file root.al, and a list of the locations of all
24 nodenames in CIF format, suitable for plotting, to the file root.nodes.
25 The file root.sim is suitable for use with programs such as crystal(1),
26 esim(1), or sim2spice(1).
27 The following options are recognized:
29 -a aliasfile
31 Instead of leaving node aliases in the file root.al, leave it
32 in aliasfile.
33 -l labelfile
35 Instead of leaving a CIF file with the locations of all node
36 names in the file root.nodes, leave it in labelfile.
37 -o outfile
39 Instead of leaving output in the file root.sim, leave it in
40 outfile.
41 -A Don't produce the aliases file.
43 -B Don't output transistor or node attributes in the .sim file.
45 This option will also disable the output of information such
46 as the area and perimeter of source and drain diffusion and
47 the fet substrate. For compatibitlity reasons the latest ver‐
48 sion of ext2sim outputs this information as node attibutes.
49 This option is necessary when preparing input for programs
50 that don't know about attributes, such as sim2spice(1) (which
51 is actually made obsolete by ext2spice(1), anyway), or
52 rsim(1).
53 -F Don't output nodes that aren't connected to fets (floating
55 nodes).
56 -L Don't produce the label file.
58 -tchar Trim characters from node names when writing the output file.
60 Char should be either "#" or "!". The option may be used
61 twice if both characters are desired.
62 -f MIT|LBL|SU
64 Select the output format. MIT is the traditional sim(5) for‐
65 mat. LBL is a variant of it understood by gemini(1) which
66 includes the substrate connection as a fourth terminal before
67 length and width. SU is the internal Stanford format which
68 is described also in sim(5) and includes areas and perimeters
69 of fet sources, drains and substrates.
70 -y num Select the precision for outputing capacitors. The default is
72 1 which means that the capacitors will be printed to a preci‐
73 sion of .1 fF.
74 -J hier|flat
76 Select the source/drain area and perimeter extraction algo‐
77 rithm. If hier is selected then the areas and perimeters are
78 extracted only within each subcell. For each fet in a subcell
79 the area and perimeter of its source and drain within this
80 subcell are output. If two or more fets share a source/drain
81 node then the total area and perimeter will be output in only
82 one of them and the other will have 0. If flat is selected
83 the same rules apply only that the scope of search for area
84 and perimeter is the whole netlist. In general flat (which is
85 the default) will give accurate results (it will take into
86 account shared sources/drains) but hier is provided for back‐
87 wards compatibility with version 6.4.5. On top of this selec‐
88 tion you can individually control how a terminal of a spe‐
89 cific fet will be extracted if you put a source/drain
90 attribute. ext:aph makes the extraction for that specific
91 terminal hierarchical and ext:apf makes the extraction flat
92 (see the magic tutorial about attaching attribute labels).
93 Additionaly to ease extraction of bipolar transistors the
94 gate attribute ext:aps forces the output of the substrate
95 area and perimeter for a specific fet (in flat mode only).
96 -j device:sdRclass[/subRclass]/defaultSubstrate
98 Gives ext2sim information about the source/drain resistance
99 class of the fet type device. Makes device to have sdRclass
100 source drain resistance class, subRclass substrate (well)
101 resistance class and the node named defaultSubstrate as its
102 default substrate. The defaults are nfet:0/Gnd and
103 pfet:1/6/Vdd which correspond to the MOSIS technology file
104 but things might vary in your site. Ask your local cad admin‐
105 istrator.
106 The way the extraction of node area and perimeter works in magic the
109 total area and perimeter of the source/drain junction is summed up on a
110 single node. That is why all the junction areas and perimeters are
111 summed up on a single node (this should not affect simulation results
112 however).
113 Special care must be taken when the substrate of a fet is tied to a
115 node other than the default substrate (eg in a bootstraping charge
116 pump). To get the correct substrate info in these cases the fet(s)
117 with separate wells should be in their own separate subcell with
118 ext:aph attributes attached to their sensitive terminals (also all the
119 transistors which share sensistive terminals with these should be in
120 another subcell with the same attributes).
121 In addition, all of the options of extcheck(1) are accepted.
125
128 If all of the .ext files in the tree read by ext2sim have the same geo‐
129 metrical scale (specified in the scale line in each .ext file), this
130 scale is reflected through to the output, resulting in substantially
131 smaller .sim files. Otherwise, the geometrical unit in the output .sim
132 file is a centimicron.
133 Resistance and capacitance are always output in ohms and femptofarads,
135 respectively.
136
139 extcheck(1), ext2dlys(1), ext2spice(1), magic(1), rsim(1), ext(5),
140 sim(5)
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144 Walter Scott additions/fixes by Stefanos Sidiropoulos.
145
148 Transistor gate capacitance is typically not included in node capaci‐
149 tances, as most analysis tools compute the gate capacitance directly
150 from the gate area. The -c flag therefore provides a limit only on
151 non-gate capacitance. The areas and perimeters of fet sources and
152 drains work only with the simple extraction algorith and not with the
153 extresis flow. So you have to model them as linear capacitors (create a
154 special extraction style) if you want to extract parasitic resistances
155 with extresis.
1564th Berkeley Distribution EXT2SIM(1)