perf-list(1)

1PERF-LIST(1)                      perf Manual                     PERF-LIST(1)
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NAME

6       perf-list - List all symbolic event types
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SYNOPSIS

9       perf list [hw|sw|cache|tracepoint|pmu|event_glob]
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DESCRIPTION

12       This command displays the symbolic event types which can be selected in
13       the various perf commands with the -e option.
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EVENT MODIFIERS

16       Events can optionally have a modifier by appending a colon and one or
17       more modifiers. Modifiers allow the user to restrict the events to be
18       counted. The following modifiers exist:
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20           u - user-space counting
21           k - kernel counting
22           h - hypervisor counting
23           I - non idle counting
24           G - guest counting (in KVM guests)
25           H - host counting (not in KVM guests)
26           p - precise level
27           S - read sample value (PERF_SAMPLE_READ)
28           D - pin the event to the PMU
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30       The p modifier can be used for specifying how precise the instruction
31       address should be. The p modifier can be specified multiple times:
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33           0 - SAMPLE_IP can have arbitrary skid
34           1 - SAMPLE_IP must have constant skid
35           2 - SAMPLE_IP requested to have 0 skid
36           3 - SAMPLE_IP must have 0 skid
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38       For Intel systems precise event sampling is implemented with PEBS which
39       supports up to precise-level 2.
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41       On AMD systems it is implemented using IBS (up to precise-level 2). The
42       precise modifier works with event types 0x76 (cpu-cycles, CPU clocks
43       not halted) and 0xC1 (micro-ops retired). Both events map to IBS
44       execution sampling (IBS op) with the IBS Op Counter Control bit
45       (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
46       Manual Volume 2: System Programming, 13.3 Instruction-Based Sampling).
47       Examples to use IBS:
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49           perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
50           perf record -a -e r076:p ...          # same as -e cpu-cycles:p
51           perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR

54       Even when an event is not available in a symbolic form within perf
55       right now, it can be encoded in a per processor specific way.
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57       For instance For x86 CPUs NNN represents the raw register encoding with
58       the layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32
59       Architectures Software Developer’s Manual Volume 3B: System Programming
60       Guide] Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMD’s
61       PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2:
62       System Programming], Page 344, Figure 13-7 Performance Event-Select
63       Register (PerfEvtSeln)).
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65       Note: Only the following bit fields can be set in x86 counter
66       registers: event, umask, edge, inv, cmask. Esp. guest/host only and
67       OS/user mode flags must be setup using EVENT MODIFIERS.
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69       Example:
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71       If the Intel docs for a QM720 Core i7 describe an event as:
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73           Event  Umask  Event Mask
74           Num.   Value  Mnemonic    Description                        Comment
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76           A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
77                                     delivered by loop stream detector  invert to count
78                                                                        cycles
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80       raw encoding of 0x1A8 can be used:
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82           perf stat -e r1a8 -a sleep 1
83           perf record -e r1a8 ...
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85       You should refer to the processor specific documentation for getting
86       these details. Some of them are referenced in the SEE ALSO section
87       below.
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PARAMETERIZED EVENTS

90       Some pmu events listed by perf-list will be displayed with ? in them.
91       For example:
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93           hv_gpci/dtbp_ptitc,phys_processor_idx=?/
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95       This means that when provided as an event, a value for ? must also be
96       supplied. For example:
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98           perf stat -C 0 -e ´hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/´ ...
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OPTIONS

101       Without options all known events will be listed.
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103       To limit the list use:
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105        1.  hw or hardware to list hardware events such as cache-misses, etc.
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107        2.  sw or software to list software events such as context switches,
108           etc.
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110        3.  cache or hwcache to list hardware cache events such as
111           L1-dcache-loads, etc.
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113        4.  tracepoint to list all tracepoint events, alternatively use
114           subsys_glob:event_glob to filter by tracepoint subsystems such as
115           sched, block, etc.
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117        5.  pmu to print the kernel supplied PMU events.
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119        6. If none of the above is matched, it will apply the supplied glob to
120           all events, printing the ones that match.
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122       One or more types can be used at the same time, listing the events for
123       the types specified.
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125       Support raw format:
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127        1.  --raw-dump, shows the raw-dump of all the events.
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129        2.  --raw-dump [hw|sw|cache|tracepoint|pmu|event_glob], shows the
130           raw-dump of a certain kind of events.
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NOTES

139        1. Intel® 64 and IA-32 Architectures Software Developer’s Manual
140           Volume 3B: System Programming Guide
141           http://www.intel.com/Assets/PDF/manual/253669.pdf
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143        2. AMD64 Architecture Programmer’s Manual Volume 2: System Programming
144           http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf
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148perf                              06/18/2019                      PERF-LIST(1)