1PERF-LIST(1) perf Manual PERF-LIST(1)
2
6 perf-list - List all symbolic event types
7
9 perf list [--no-desc] [--long-desc]
10 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
11
13 This command displays the symbolic event types which can be selected in
14 the various perf commands with the -e option.
15
17 -d, --desc
18 Print extra event descriptions. (default)
19 --no-desc
21 Don’t print descriptions.
22 -v, --long-desc
24 Print longer event descriptions.
25 --debug
27 Enable debugging output.
28 --details
30 Print how named events are resolved internally into perf events,
31 and also any extra expressions computed by perf stat.
32
34 Events can optionally have a modifier by appending a colon and one or
35 more modifiers. Modifiers allow the user to restrict the events to be
36 counted. The following modifiers exist:
37 u - user-space counting
39 k - kernel counting
40 h - hypervisor counting
41 I - non idle counting
42 G - guest counting (in KVM guests)
43 H - host counting (not in KVM guests)
44 p - precise level
45 P - use maximum detected precise level
46 S - read sample value (PERF_SAMPLE_READ)
47 D - pin the event to the PMU
48 W - group is weak and will fallback to non-group if not schedulable,
49 The p modifier can be used for specifying how precise the instruction
51 address should be. The p modifier can be specified multiple times:
52 0 - SAMPLE_IP can have arbitrary skid
54 1 - SAMPLE_IP must have constant skid
55 2 - SAMPLE_IP requested to have 0 skid
56 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
57 sample shadowing effects.
58 For Intel systems precise event sampling is implemented with PEBS which
60 supports up to precise-level 2, and precise level 3 for some special
61 cases
62 On AMD systems it is implemented using IBS (up to precise-level 2). The
64 precise modifier works with event types 0x76 (cpu-cycles, CPU clocks
65 not halted) and 0xC1 (micro-ops retired). Both events map to IBS
66 execution sampling (IBS op) with the IBS Op Counter Control bit
67 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
68 Manual Volume 2: System Programming, 13.3 Instruction-Based Sampling).
69 Examples to use IBS:
70 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
72 perf record -a -e r076:p ... # same as -e cpu-cycles:p
73 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
74
76 Even when an event is not available in a symbolic form within perf
77 right now, it can be encoded in a per processor specific way.
78 For instance For x86 CPUs NNN represents the raw register encoding with
80 the layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32
81 Architectures Software Developer’s Manual Volume 3B: System Programming
82 Guide] Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMD’s
83 PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2:
84 System Programming], Page 344, Figure 13-7 Performance Event-Select
85 Register (PerfEvtSeln)).
86 Note: Only the following bit fields can be set in x86 counter
88 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
89 OS/user mode flags must be setup using EVENT MODIFIERS.
90 Example:
92 If the Intel docs for a QM720 Core i7 describe an event as:
94 Event Umask Event Mask
96 Num. Value Mnemonic Description Comment
97 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
99 delivered by loop stream detector invert to count
100 cycles
101 raw encoding of 0x1A8 can be used:
103 perf stat -e r1a8 -a sleep 1
105 perf record -e r1a8 ...
106 You should refer to the processor specific documentation for getting
108 these details. Some of them are referenced in the SEE ALSO section
109 below.
110
112 perf also supports an extended syntax for specifying raw parameters to
113 PMUs. Using this typically requires looking up the specific event in
114 the CPU vendor specific documentation.
115 The available PMUs and their raw parameters can be listed with
117 ls /sys/devices/*/format
119 For example the raw event "LSD.UOPS" core pmu event above could be
121 specified as
122 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
124 or using extended name syntax
126 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
128
130 Some PMUs are not associated with a core, but with a whole CPU socket.
131 Events on these PMUs generally cannot be sampled, but only counted
132 globally with perf stat -a. They can be bound to one logical CPU, but
133 will measure all the CPUs in the same socket.
134 This example measures memory bandwidth every second on the first memory
136 controller on socket 0 of a Intel Xeon system
137 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
139 Each memory controller has its own PMU. Measuring the complete system
141 bandwidth would require specifying all imc PMUs (see perf list output),
142 and adding the values together. To simplify creation of multiple
143 events, prefix and glob matching is supported in the PMU name, and the
144 prefix uncore_ is also ignored when performing the match. So the
145 command above can be expanded to all memory controllers by using the
146 syntaxes:
147 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
149 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
150 This example measures the combined core power every second
152 perf stat -I 1000 -e power/energy-cores/ -a
154
156 For non root users generally only context switched PMU events are
157 available. This is normally only the events in the cpu PMU, the
158 predefined events like cycles and instructions and some software
159 events.
160 Other PMUs and global measurements are normally root only. Some event
162 qualifiers, such as "any", are also root only.
163 This can be overridden by setting the kernel.perf_event_paranoid sysctl
165 to -1, which allows non root to use these events.
166 For accessing trace point events perf needs to have read access to
168 /sys/kernel/debug/tracing, even when perf_event_paranoid is in a
169 relaxed setting.
170
172 Some PMUs control advanced hardware tracing capabilities, such as Intel
173 PT, that allows low overhead execution tracing. These are described in
174 a separate intel-pt.txt document.
175
177 Some pmu events listed by perf-list will be displayed with ? in them.
178 For example:
179 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
181 This means that when provided as an event, a value for ? must also be
183 supplied. For example:
184 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
186
188 Perf supports time based multiplexing of events, when the number of
189 events active exceeds the number of hardware performance counters.
190 Multiplexing can cause measurement errors when the workload changes its
191 execution profile.
192 When metrics are computed using formulas from event counts, it is
194 useful to ensure some events are always measured together as a group to
195 minimize multiplexing errors. Event groups can be specified using { }.
196 perf stat -e '{instructions,cycles}' ...
198 The number of available performance counters depend on the CPU. A group
200 cannot contain more events than available counters. For example Intel
201 Core CPUs typically have four generic performance counters for the
202 core, plus three fixed counters for instructions, cycles and
203 ref-cycles. Some special events have restrictions on which counter they
204 can schedule, and may not support multiple instances in a single group.
205 When too many events are specified in the group some of them will not
206 be measured.
207 Globally pinned events can limit the number of counters available for
209 other groups. On x86 systems, the NMI watchdog pins a counter by
210 default. The nmi watchdog can be disabled as root with
211 echo 0 > /proc/sys/kernel/nmi_watchdog
213 Events from multiple different PMUs cannot be mixed in a group, with
215 some exceptions for software events.
216
218 perf also supports group leader sampling using the :S specifier.
219 perf record -e '{cycles,instructions}:S' ...
221 perf report --group
222 Normally all events in an event group sample, but with :S only the
224 first event (the leader) samples, and it only reads the values of the
225 other events in the group.
226
228 Without options all known events will be listed.
229 To limit the list use:
231 1. hw or hardware to list hardware events such as cache-misses, etc.
233 2. sw or software to list software events such as context switches,
235 etc.
236 3. cache or hwcache to list hardware cache events such as
238 L1-dcache-loads, etc.
239 4. tracepoint to list all tracepoint events, alternatively use
241 subsys_glob:event_glob to filter by tracepoint subsystems such as
242 sched, block, etc.
243 5. pmu to print the kernel supplied PMU events.
245 6. sdt to list all Statically Defined Tracepoint events.
247 7. metric to list metrics
249 8. metricgroup to list metricgroups with metrics.
251 9. If none of the above is matched, it will apply the supplied glob to
253 all events, printing the ones that match.
254 10. As a last resort, it will do a substring search in all event names.
256 One or more types can be used at the same time, listing the events for
258 the types specified.
259 Support raw format:
261 1. --raw-dump, shows the raw-dump of all the events.
263 2. --raw-dump [hw|sw|cache|tracepoint|pmu|event_glob], shows the
265 raw-dump of a certain kind of events.
266
268 perf-stat(1), perf-top(1), perf-record(1), Intel® 64 and IA-32
269 Architectures Software Developer’s Manual Volume 3B: System Programming
270 Guide[1], AMD64 Architecture Programmer’s Manual Volume 2: System
271 Programming[2]
272
274 1. Intel® 64 and IA-32 Architectures Software Developer’s Manual
275 Volume 3B: System Programming Guide
276 http://www.intel.com/sdm/
277 2. AMD64 Architecture Programmer’s Manual Volume 2: System Programming
279 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf
280perf 06/03/2019 PERF-LIST(1)