1STRUCT SPI_MASTER(9)    Serial Peripheral Interface (S    STRUCT SPI_MASTER(9)
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NAME

6       struct_spi_master - interface to SPI master controller
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SYNOPSIS

9       struct spi_master {
10         struct device dev;
11         s16 bus_num;
12         u16 num_chipselect;
13         u16 dma_alignment;
14         u16 mode_bits;
15         u16 flags;
16       #define SPI_MASTER_HALF_DUPLEX     BIT(0)
17       #define SPI_MASTER_NO_RX BIT(1)
18       #define SPI_MASTER_NO_TX BIT(2)
19         int (* setup) (struct spi_device *spi);
20         int (* transfer) (struct spi_device *spi,struct spi_message *mesg);
21         void (* cleanup) (struct spi_device *spi);
22       };
23

MEMBERS

25       dev
26           device interface to this driver
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28       bus_num
29           board-specific (and often SOC-specific) identifier for a given SPI
30           controller.
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32       num_chipselect
33           chipselects are used to distinguish individual SPI slaves, and are
34           numbered from zero to num_chipselects. each slave has a chipselect
35           signal, but it´s common that not every chipselect is connected to a
36           slave.
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38       dma_alignment
39           SPI controller constraint on DMA buffers alignment.
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41       mode_bits
42           flags understood by this controller driver
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44       flags
45           other constraints relevant to this driver
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47       setup
48           updates the device mode and clocking records used by a device´s SPI
49           controller; protocol code may call this. This must fail if an
50           unrecognized or unsupported mode is requested. It´s always safe to
51           call this unless transfers are pending on the device whose settings
52           are being modified.
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54       transfer
55           adds a message to the controller´s transfer queue.
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57       cleanup
58           frees controller-specific state
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DESCRIPTION

61       Each SPI master controller can communicate with one or more spi_device
62       children. These make a small bus, sharing MOSI, MISO and SCK signals
63       but not chip select signals. Each device may be configured to use a
64       different clock rate, since those shared signals are ignored unless the
65       chip is selected.
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67       The driver for an SPI controller manages access to those devices
68       through a queue of spi_message transactions, copying data between CPU
69       memory and an SPI slave device. For each such message it queues, it
70       calls the message´s completion function when the transaction completes.
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73Kernel Hackers Manual 2.6.         June 2019              STRUCT SPI_MASTER(9)
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