1VERILATOR(1) User Contributed Perl Documentation VERILATOR(1)
2
6 Verilator - Convert Verilog code to C++/SystemC
7
9 verilator --help
10 verilator --version
11 verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
12 verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
13 verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
14 verilator --lint-only [top_level.v]...
15
17 Verilator converts synthesizable (not behavioral) Verilog code, plus
18 some Synthesis, SystemVerilog and Sugar/PSL assertions, into C++,
19 SystemC or SystemPerl code. It is not a complete simulator, just a
20 compiler.
21 Verilator is invoked with parameters similar to GCC, Cadence
23 Verilog-XL/NC-Verilog, or Synopsys's VCS. It reads the specified
24 Verilog code, lints it, and optionally adds coverage and waveform
25 tracing code. For C++ and SystemC formats, it outputs .cpp and .h
26 files. For SystemPerl format, it outputs .sp files for the SystemPerl
27 preprocessor, which greatly simplifies writing SystemC code and is
28 available at <http://www.veripool.org>.
29 The files created by Verilator are then compiled with C++. The user
31 writes a little C++ wrapper file, which instantiates the top level
32 module, and passes this filename on the command line. These C files
33 are compiled in C++, and linked with the Verilated files.
34 The resulting executable will perform the actual simulation.
36 To get started, jump down to "EXAMPLE C++ EXECUTION".
38
40 This is a short summary of the arguments to Verilator. See the
41 detailed descriptions in the next sections for more information.
42 {file.v} Verilog top level filenames
44 {file.c/cc/cpp} Optional C++ files to compile in
45 {file.a/o/so} Optional C++ files to link in
46 --assert Enable all assertions
48 --autoflush Flush streams after all $displays
49 --bbox-sys Blackbox unknown $system calls
50 --bbox-unsup Blackbox unsupported language features
51 --bin <filename> Override Verilator binary
52 -CFLAGS <flags> C++ Compiler flags for makefile
53 --cc Create C++ output
54 --cdc Clock domain crossing analysis
55 --compiler <compiler-name> Tune for specified C++ compiler
56 --coverage Enable all coverage
57 --coverage-line Enable line coverage
58 --coverage-toggle Enable toggle coverage
59 --coverage-user Enable PSL/SVL user coverage
60 --coverage-underscore Enable covarge of _signals
61 -D<var>[=<value>] Set preprocessor define
62 --debug Enable debugging
63 --debug-check Enable debugging assertions
64 --debugi <level> Enable debugging at a specified level
65 --debugi-<srcfile> <level> Enable debugging a source file at a level
66 +define+<var>+<value> Set preprocessor define
67 --dump-tree Enable dumping .tree files
68 -E Preprocess, but do not compile
69 --error-limit <value> Abort after this number of errors
70 --exe Link to create executable
71 -f <file> Parse options from a file
72 --help Display this help.
73 -I<dir> Directory to search for includes
74 +incdir+<dir> Directory to search for includes
75 --inhibit-sim Create function to turn off sim
76 --inline-mult <value> Tune module inlining
77 -LDFLAGS <flags> Linker pre-object flags for makefile
78 -LDLIBS <flags> Linker library flags for makefile
79 --language <lang> Language standard to parse
80 +libext+<ext>+[ext]... Extensions for finding modules
81 --lint-only Lint, but do not make output
82 --MMD Create .d dependency files
83 --MP Create phony dependency targets
84 --Mdir <directory> Name of output object directory
85 --mod-prefix <topname> Name to prepend to lower classes
86 --no-pins64 Don't use uint64_t's for 33-64 bit sigs
87 --no-skip-identical Disable skipping identical output
88 +notimingchecks Ignored
89 -O0 Disable optimizations
90 -O3 High performance optimizations
91 -O<optimization-letter> Selectable optimizations
92 -o <executable> Name of final executable
93 --output-split <bytes> Split .cpp files into pieces
94 --output-split-cfuncs <statements> Split .ccp functions
95 --pins-bv <bits> Specify types for top level ports
96 --pins-uint8 Specify types for top level ports
97 --pipe-filter <command> Filter all input through a script
98 --prefix <topname> Name of top level class
99 --profile-cfuncs Name functions for profiling
100 --private Debugging; see docs
101 --psl Enable PSL parsing
102 --public Debugging; see docs
103 --sc Create SystemC output
104 --sp Create SystemPerl output
105 --stats Create statistics file
106 -sv Enable SystemVerilog parsing
107 --top-module <topname> Name of top level input module
108 --trace Enable waveform creation
109 --trace-depth <levels> Depth of tracing
110 --trace-underscore Enable tracing of _signals
111 -U<var> Undefine preprocessor define
112 --unroll-count <loops> Tune maximum loop iterations
113 --unroll-stmts <stmts> Tune maximum loop body size
114 -V Verbose version and config
115 -v <filename> Verilog library
116 -Werror-<message> Convert warning to error
117 -Wfuture-<message> Disable unknown message warnings
118 -Wno-<message> Disable warning
119 -Wno-lint Disable all lint warnings
120 -x-assign <mode> Initially assign Xs to this value
121 -y <dir> Directory to search for modules
122
124 {file.v}
125 Specifies the Verilog file containing the top module to be
126 Verilated.
127 {file.c/.cc/.cpp/.cxx}
129 Specifies optional C++ files to be linked in with the Verilog code.
130 If any C++ files are specified in this way, Verilator will include
131 a make rule that generates a module executable. Without any C++
132 files, Verilator will stop at the module__ALL.a library, and
133 presume you'll continue linking with make rules you write yourself.
134 See also the -CFLAGS option.
135 {file.a/.o/.so}
137 Specifies optional object or library files to be linked in with the
138 Verilog code, as a shorthand for -LDFLAGS "<file>". If any files
139 are specified in this way, Verilator will include a make rule that
140 uses these files when linking the module executable. This
141 generally is only useful when used with the --exe option.
142 --assert
144 Enable all assertions, includes enabling the --psl flag. (If psl
145 is not desired, but other assertions are, use --assert --nopsl.)
146 See also --x-assign; setting "--x-assign unique" may be desirable.
148 --autoflush
150 After every $display or $fdisplay, flush the output stream. This
151 insures that messages will appear immediately but may reduce
152 performance. Defaults off, which will buffer output as provided by
153 the normal C stdio calls.
154 --bbox-sys
156 Black box any unknown $system task or function calls. System tasks
157 will be simply NOPed, and system functions will be replaced by
158 unsized zero. Arguments to such functions will be parsed, but not
159 otherwise checked. This prevents errors when linting in the
160 presence of company specific PLI calls.
161 --bbox-unsup
163 Black box some unsupported language features, currently UDP tables
164 and the cmos and tran gate primitives. This may enable linting the
165 rest of the design even when unsupported constructs are present.
166 --bin filename
168 Rarely needed. Override the default filename for Verilator itself.
169 When a dependency (.d) file is created, this filename will become a
170 source dependency, such that a change in this binary will have make
171 rebuild the output files.
172 -CFLAGS flags
174 Add specified C compiler flags to the generated makefiles. When
175 make is run on the generated makefile these will be passed to the
176 C++ compiler (gcc/g++/msvc++).
177 --cc
179 Specifies C++ without SystemC output mode; see also --sc and --sp.
180 --cdc
182 Experimental. Perform some clock domain crossing checks and issue
183 related warnings (CDCRSTLOGIC) and then exit; if warnings other
184 than CDC warnings are needed make a second run with --lint-only.
185 Additional warning information is also written to the file
186 {prefix}__cdc.txt.
187 Currently only checks some items that other CDC tools missed; if
189 you have interest in adding more traditional CDC checks, please
190 contact the authors.
191 --compiler compiler-name
193 Enables tunings and work-arounds for the specified C++ compiler.
194 gcc Tune for Gnu C++, although generated code should work on almost
196 any compliant C++ compiler. Currently the default.
197 msvc
199 Tune for Microsoft Visual C++. This may reduce execution speed
200 as it enables several workarounds to avoid silly hardcoded
201 limits in MSVC++. This includes breaking deeply nested
202 parenthesized expressions into sub-expressions to avoid error
203 C1009, and breaking deep blocks into functions to avoid error
204 C1061.
205 --coverage
207 Enables all forms of coverage, alias for "--coverage-line
208 --coverage-toggle --coverage-user".
209 --coverage-line
211 Specifies basic block line coverage analysis code should be
212 inserted.
213 Coverage analysis adds statements at each code flow change point,
215 which are the branches of IF and CASE statements, a super-set of
216 normal Verilog Line Coverage. At each such branch a unique counter
217 is incremented. At the end of a test, the counters along with the
218 filename and line number corresponding to each counter are written
219 into logs/coverage.pl.
220 Verilator automatically disables coverage of branches that have a
222 $stop in them, as it is assumed $stop branches contain an error
223 check that should not occur. A /*verilator coverage_block_off*/
224 comment will perform a similar function on any code in that block
225 or below, or /*verilator coverage_on/coverage_off*/ will disable
226 coverage around lines of code.
227 Note Verilator may over-count combinatorial (non-clocked) blocks
229 when those blocks receive signals which have had the UNOPTFLAT
230 warning disabled; for most accurate results do not disable this
231 warning when using coverage.
232 --coverage-toggle
234 Specifies signal toggle coverage analysis code should be inserted.
235 Every bit of every signal in a module has a counter inserted. The
237 counter will increment on every edge change of the corresponding
238 bit.
239 Signals that are part of tasks or begin/end blocks are considered
241 local variables and are not covered. Signals that begin with
242 underscores, are integers, or are very wide (>256 bits total
243 storage across all dimensions) are also not covered.
244 Hierarchy is compressed, such that if a module is instantiated
246 multiple times, coverage will be summed for that bit across ALL
247 instantiations of that module with the same parameter set. A
248 module instantiated with different parameter values is considered a
249 different module, and will get counted separately.
250 Verilator makes a minimally-intelligent decision about what clock
252 domain the signal goes to, and only looks for edges in that clock
253 domain. This means that edges may be ignored if it is known that
254 the edge could never be seen by the receiving logic. This
255 algorithm may improve in the future. The net result is coverage
256 may be lower than what would be seen by looking at traces, but the
257 coverage is a more accurate representation of the quality of
258 stimulus into the design.
259 There may be edges counted near time zero while the model
261 stabilizes. It's a good practice to zero all coverage just before
262 releasing reset to prevent counting such behavior.
263 A /*verilator coverage_off/on */ comment pair can be used around
265 signals that do not need toggle analysis, such as RAMs and register
266 files.
267 --coverage-underscore
269 Enable coverage of signals that start with an underscore. Normally,
270 these signals are not covered. See also --trace-underscore.
271 --coverage-user
273 Enables user inserted functional coverage. Currently, all
274 functional coverage points are specified using PSL which must be
275 separately enabled with --psl.
276 For example, the following PSL statement will add a coverage point,
278 with the comment "DefaultClock":
279 // psl default clock = posedge clk;
281 // psl cover {cyc==9} report "DefaultClock,expect=1";
282 -Dvar=value
284 Defines the given preprocessor symbol. Same as +define; +define is
285 fairly standard across Verilog tools while -D is an alias for GCC
286 compatibility.
287 --debug
289 Select the debug built image of Verilator (if available), and
290 enable more internal assertions, debugging messages, and
291 intermediate form dump files.
292 --debug-check
294 Rarely needed. Enable internal debugging assertion checks, without
295 changing debug verbosity. Enabled automatically when --debug
296 specified.
297 --debugi <level> =item --debugi-<srcfile> <level>
299 Rarely needed - for developer use. Set internal debugging level
300 globally or on the specified source file to the specified level.
301 +define+var+value
303 Defines the given preprocessor symbol. Same as -D; +define is
304 fairly standard across Verilog tools while -D is an alias for GCC
305 compatibility.
306 --dump-tree
308 Rarely needed. Enable writing .tree debug files. This is enabled
309 with --debug, so "--debug --no-dump-tree" may be useful if the dump
310 files are large and not desired.
311 -E Preprocess the source code, but do not compile, as with 'gcc -E'.
313 Output is written to standard out. Beware of enabling debugging
314 messages, as they will also go to standard out.
315 --error-limit <value>
317 After this number of errors or warnings are encountered, exit.
318 Defaults to 50.
319 --exe
321 Generate a executable. You will also need to pass additional .cpp
322 files on the command line that implement the main loop for your
323 simulation.
324 -f file
326 Read the specified file, and act as if all text inside it was
327 specified as command line parameters. Note -f is fairly standard
328 across Verilog tools.
329 --help
331 Displays this message and program version and exits.
332 -Idir
334 Add the directory to the list of directories that should be
335 searched for include directories or libraries. Same as +incdir and
336 -y; +incdir and -y are fairly standard across Verilog tools while
337 -I is an alias for GCC compatibility.
338 +incdir+dir
340 Add the directory to the list of directories that should be
341 searched for include directories or libraries. Same as -I and -y;
342 +incdir and -y are fairly standard across Verilog tools while -I is
343 an alias for GCC compatibility.
344 --inhibit-sim
346 Rarely needed. Create a "inhibitSim(bool)" function to enable and
347 disable evaluation. This allows a upper level testbench to disable
348 modules that are not important in a given simulation, without
349 needing to recompile or change the SystemC modules instantiated.
350 --inline-mult value
352 Tune the inlining of modules. The default value of 2000 specifies
353 that up to 2000 new operations may be added to the model by
354 inlining, if more than this number of operations would result, the
355 module is not inlined. Larger values, or a value <= 1 will inline
356 everything, will lead to longer compile times, but potentially
357 faster runtimes. This setting is ignored for very small modules;
358 they will always be inlined, if allowed.
359 -LDFLAGS flags
361 Add specified C linker flags to the generated makefiles. When make
362 is run on the generated makefile these will be passed to the C++
363 linker (ld) *after* the primary file being linked. This flag is
364 called -LDFLAGS as that's the traditional name in simulators; it's
365 would have been better called LDLIBS as that's the Makefile
366 variable it controls. (In Make, LDFLAGS is before the first
367 object, LDLIBS after. -L libraries need to be in the Make variable
368 LDLIBS, not LDFLAGS.)
369 --language value
371 Select the language to be used when first processing each Verilog
372 file. The language value must be "1364-1995", "1364-2001",
373 "1364-2001", "1364-2005", or "1800-2005". This should only be used
374 for legacy code, as the preferable option is to edit the code to
375 repair new keywords, or add appropriate `begin_keywords.
376 +libext+ext+ext...
378 Specify the extensions that should be used for finding modules. If
379 for example module x is referenced, look in x.ext. Note +libext+
380 is fairly standard across Verilog tools.
381 --lint-only
383 Check the files for lint violations only, do not create any other
384 output.
385 If the design is not to be completely Verilated see also the
387 --bbox-sys and --bbox-unsup options.
388 --MMD
390 Enable creation of .d dependency files, used for make dependency
391 detection, similar to gcc -MMD option. On by default, use --no-MMD
392 to disable.
393 --MP
395 When creating .d dependency files with --MMD, make phony targets.
396 Similar to gcc -MP option.
397 --Mdir directory
399 Specifies the name of the Make object directory. All generated
400 files will be placed in this directory. If not specified,
401 "obj_dir" is used.
402 --mod-prefix topname
404 Specifies the name to prepend to all lower level classes. Defaults
405 to the same as --prefix.
406 --no-pins64
408 Backward compatible alias for "--pins-bv 33".
409 --no-skip-identical
411 Rarely needed. Disables skipping execution of Verilator if all
412 source files are identical, and all output files exist with newer
413 dates.
414 +notimingchecks
416 Ignored for compatibility with other simulators.
417 -O0 Disables optimization of the model.
419 -O3 Enables slow optimizations. This may reduce simulation runtimes at
421 the cost of compile time. This currently sets --inline-mult -1.
422 -Ooptimization-letter
424 Rarely needed. Enables or disables a specific optimizations, with
425 the optimization selected based on the letter passed. A lowercase
426 letter disables an optimization, an upper case letter enables it.
427 This is intended for debugging use only; see the source code for
428 version-dependent mappings of optimizations to -O letters.
429 -o <executable>
431 Specify the name for the final executable built if using --exe.
432 Defaults to the --prefix if not specified.
433 --output-split bytes
435 Enables splitting the output .cpp/.sp files into multiple outputs.
436 When a C++ file exceeds the specified number of operations, a new
437 file will be created at the next function boundary. In addition,
438 any slow routines will be placed into __Slow files. This
439 accelerates compilation by as optimization can be disabled on the
440 slow routines, and the remaining files can be compiled on parallel
441 machines. Using --output-split should have only a trivial impact
442 on performance. With GCC 3.3 on a 2GHz Opteron, --output-split
443 20000 will result in splitting into approximately one-minute-
444 compile chunks.
445 --output-split-cfuncs statements
447 Enables splitting functions in the output .cpp/.sp files into
448 multiple functions. When a generated function exceeds the
449 specified number of operations, a new function will be created.
450 With --output-split, this will enable GCC to compile faster, at a
451 small loss in performance that gets worse with decreasing split
452 values. Note that this option is stronger than --output-split in
453 the sense that --output-split will not split inside a function.
454 --pins64
456 Backward compatible alias for "--pins-bv 65". Note that's a 65,
457 not a 64.
458 --pins-bv width
460 Specifies SystemC inputs/outputs of greater than or equal to width
461 bits wide should use sc_bv's instead of uint32/uint64_t's. The
462 default is "--pins-bv 65". Versions before Verilator 3.671
463 defaulted to "--pins-bv 33". The more sc_bv is used, the worse for
464 performance.
465 --pins-uint8
467 Specifies SystemC inputs/outputs that are smaller than the
468 --pins-bv setting and 8 bits or less should use uint8_t instead of
469 uint32_t. Likewise pins of width 9-16 will use uint16_t instead of
470 uint32_t.
471 --pipe-filter command
473 Rarely needed and experimental. Verilator will spawn the specified
474 command as a subprocess pipe, to allow the command to perform
475 custom edits on the Verilog code before it reaches Verilator.
476 Before reading each Verilog file, Verilator will pass the file name
478 to the subprocess' stdin with 'read_verilog "<filename>"'. The
479 filter may then read the file and perform any filtering it desires,
480 and feeds the new file contents back to Verilator on stdout with
481 'Content-Length'. Output to stderr from the filter feeds through
482 to Verilator's stdout and if the filter exits with non-zero status
483 Verilator terminates. See the t/t_pipe_filter test for an example.
484 To debug the output of the filter, try using the -E option to see
486 preprocessed output.
487 --prefix topname
489 Specifies the name of the top level class and makefile. Defaults
490 to V prepended to the name of the --top-module switch, or V
491 prepended to the first Verilog filename passed on the command line.
492 --profile-cfuncs
494 Modify the created C++ functions to support profiling. The
495 functions will be minimized to contain one "basic" statement,
496 generally a single always block or wire statement. (Note this will
497 slow down the executable by ~5%.) Furthermore, the function name
498 will be suffixed with the basename of the Verilog module and line
499 number the statement came from. This allows gprof or oprofile
500 reports to be correlated with the original Verilog source
501 statements.
502 --private
504 Opposite of --public. Is the default; this option exists for
505 backwards compatibility.
506 --psl
508 Enable PSL parsing. Without this switch, PSL meta-comments are
509 ignored. See the --assert flag to enable all assertions, and
510 --coverage-user to enable functional coverage.
511 --public
513 This is only for historical debug use. Using it may result in mis-
514 simulation of generated clocks.
515 Declares all signals and modules public. This will turn off signal
517 optimizations as if all signals had a /*verilator public*/ comments
518 and inlining. This will also turn off inlining as if all modules
519 had a /*verilator public_module*/, unless the module specifically
520 enabled it with /*verilator inline_module*/.
521 --sc
523 Specifies SystemC output mode; see also --cc and -sp.
524 --sp
526 Specifies SystemPerl output mode; see also --cc and -sc.
527 --stats
529 Creates a dump file with statistics on the design in
530 {prefix}__stats.txt.
531 -sv Specifies SystemVerilog language features should be enabled;
533 equivalent to "--language 1800-2005". This option is selected by
534 default, it exists for compatibility with other simulators.
535 --top-module topname
537 When the input Verilog contains more than one top level module,
538 specifies the name of the top level Verilog module to become the
539 top, and sets the default for if --prefix is not used. This is not
540 needed with standard designs with only one top.
541 --trace
543 Adds waveform tracing code to the model. Verilator will generate
544 additional {prefix}__Trace*.cpp files that will need to be
545 compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) or
546 verilated_vcd_c.cpp (for both) must be compiled and linked in. If
547 using the Verilator generated Makefiles, these will be added as
548 source targets for you. If you're not using the Verilator
549 makefiles, you will need to add these to your Makefile manually.
550 Having tracing compiled in may result in some small performance
552 losses, even when waveforms are not turned on during model
553 execution.
554 --trace-depth levels
556 Specify the number of levels deep to enable tracing, for example
557 --trace-level 1 to only see the top level's signals. Defaults to
558 the entire model. Using a small number will decrease visibility,
559 but greatly improve runtime and trace file size.
560 --trace-underscore
562 Enable tracing of signals that start with an underscore. Normally,
563 these signals are not output during tracing. See also
564 --coverage-underscore.
565 -Uvar
567 Undefines the given preprocessor symbol.
568 --unroll-count loops
570 Rarely needed. Specifies the maximum number of loop iterations
571 that may be unrolled. See also BLKLOOPINIT warning.
572 --unroll-stmts statements
574 Rarely needed. Specifies the maximum number of statements in a
575 loop for that loop to be unrolled. See also BLKLOOPINIT warning.
576 -V Shows the verbose version, including configuration information
578 compiled into Verilator. (Similar to perl -V.)
579 -v filename
581 Read the filename as a Verilog library. Any modules in the file
582 may be used to resolve cell instantiations in the top level module,
583 else ignored. Note -v is fairly standard across Verilog tools.
584 -Werror-message
586 Convert the specified warning message into a error message. This
587 is generally to discourage users from violating important site-wide
588 rules, for example "-Werror-NOUNOPTFLAT".
589 -Wfuture-message
591 Suppress unknown Verilator comments or warning messages with the
592 given message code. This is used to allow code written with
593 pragmas for a later version of Verilator to run under a older
594 version; add -Wfuture- arguments for each message code or comment
595 that the new version supports which the older version does not
596 support.
597 -Wno-message
599 Disable the specified warning message.
600 -Wno-lint
602 Disable all lint related warning messages. This is equivalent to
603 "-Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX
604 -Wno-CMPCONST -Wno-IMPLICIT -Wno-LITENDIAN -Wno-UNDRIVEN
605 -Wno-UNSIGNED -Wno-UNUSED -Wno-VARHIDDEN -Wno-WIDTH".
606 It is strongly recommended you cleanup your code rather than using
608 this option, it is only intended to be use when running test-cases
609 of code received from third parties.
610 -Wwarn-message
612 Enables the specified warning message.
613 -x-assign 0
615 -x-assign 1
616 -x-assign fast (default)
617 -x-assign unique
618 Controls the two-state value that is replaced when an assignment to
619 X is encountered. -x-assign=fast, the default, converts all Xs to
620 whatever is best for performance. -x-assign=0 converts all Xs to
621 0s, and is also fast. -x-assign=1 converts all Xs to 1s, this is
622 nearly as fast as 0, but more likely to find reset bugs as active
623 high logic will fire. -x-assign=unique will call a function to
624 determine the value, this allows randomization of all Xs to find
625 reset bugs and is the slowest, but safest for finding reset bugs in
626 code.
627 If using -x-assign unique, you may want to seed your random number
629 generator such that each regression run gets a different
630 randomization sequence. Use the system's srand48() or for Windows
631 srand() function to do this. You'll probably also want to print
632 any seeds selected, and code to enable rerunning with that same
633 seed so you can reproduce bugs.
634 -y dir
636 Add the directory to the list of directories that should be
637 searched for include directories or libraries. Same as +incdir and
638 -I; +incdir and +y are fairly standard across Verilog tools while
639 -I is an alias for GCC compatibility.
640
642 We'll compile this example into C++.
643 mkdir test_our
645 cd test_our
646 cat <<EOF >our.v
648 module our;
649 initial begin \$display("Hello World"); \$finish; end
650 endmodule
651 EOF
652 cat <<EOF >sim_main.cpp
654 #include "Vour.h"
655 #include "verilated.h"
656 int main(int argc, char **argv, char **env) {
657 Verilated::commandArgs(argc, argv);
658 Vour* top = new Vour;
659 while (!Verilated::gotFinish()) { top->eval(); }
660 exit(0);
661 }
662 EOF
663 Now we run Verilator on our little example.
665 export VERILATOR_ROOT=/path/to/where/verilator/was/installed
667 $VERILATOR_ROOT/bin/verilator --cc our.v --exe sim_main.cpp
668 We can see the source code under the "obj_dir" directory. See the
670 FILES section below for descriptions of some of the files that were
671 created.
672 ls -l obj_dir
674 We then can compile it
676 cd obj_dir
678 make -j -f Vour.mk Vour
679 (Verilator included a default compile rule and link rule, since we used
681 --exe and passed a .cpp file on the Verilator command line. You can
682 also write your own compile rules, as we'll show in the SYSTEMC
683 section.)
684 And now we run it
686 cd ..
688 obj_dir/Vour
689 And we get as output
691 Hello World
693 - our.v:2: Verilog $finish
694 Really, you're better off writing a Makefile to do all this for you.
696 Then, when your source changes it will automatically run all of these
697 steps. See the test_c directory in the distribution for an example.
698
700 This is an example similar to the above, but using SystemPerl.
701 mkdir test_our_sc
703 cd test_our_sc
704 cat <<EOF >our.v
706 module our (clk);
707 input clk; // Clock is required to get initial activation
708 always @ (posedge clk)
709 begin \$display("Hello World"); \$finish; end
710 endmodule
711 EOF
712 cat <<EOF >sc_main.cpp
714 #include "Vour.h"
715 int sc_main(int argc, char **argv) {
716 Verilated::commandArgs(argc, argv);
717 sc_clock clk ("clk",10, 0.5, 3, true);
718 Vour* top;
719 top = new Vour("top"); // SP_CELL (top, Vour);
720 top->clk(clk); // SP_PIN (top, clk, clk);
721 while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
722 exit(0);
723 }
724 EOF
725 Now we run Verilator on our little example.
727 export VERILATOR_ROOT=/path/to/where/verilator/was/installed
729 $VERILATOR_ROOT/bin/verilator --sp our.v
730 Then we convert the SystemPerl output to SystemC.
732 cd obj_dir
734 export SYSTEMPERL=/path/to/where/systemperl/kit/came/from
735 $SYSTEMPERL/sp_preproc --preproc *.sp
736 (You can also skip the above sp_preproc by getting pure SystemC from
738 Verilator by replacing the verilator --sp flag in the previous step
739 with -sc.)
740 We then can compile it
742 make -j -f Vour.mk Vour__ALL.a
744 make -j -f Vour.mk ../sc_main.o verilated.o
745 And link with SystemC. Note your path to the libraries may vary,
747 depending on the operating system.
748 export SYSTEMC=/path/to/where/systemc/was/built/or/installed
750 g++ -L$SYSTEMC/lib-linux ../sc_main.o Vour__ALL*.o verilated.o \
751 -o Vour -lsystemc
752 And now we run it
754 cd ..
756 obj_dir/Vour
757 And we get the same output as the C++ example:
759 Hello World
761 - our.v:2: Verilog $finish
762 Really, you're better off using a Makefile to do all this for you.
764 Then, when your source changes it will automatically run all of these
765 steps. See the test_sp directory in the distribution for an example.
766
768 For best performance, run Verilator with the "-O3 -x-assign=fast
769 --noassert" flags. The -O3 flag will require longer compile times, and
770 -x-assign=fast may increase the risk of reset bugs in trade for
771 performance; see the above documentation for these flags.
772 Minor Verilog code changes can also give big wins. You should not have
774 any UNOPTFLAT warnings from Verilator. Fixing these warnings can
775 result in huge improvements; one user fixed their one UNOPTFLAT warning
776 by making a simple change to a clock latch used to gate clocks and
777 gained a 60% performance improvement.
778 Beyond that, the performance of a Verilated model depends mostly on
780 your C++ compiler and size of your CPU's caches.
781 By default, the lib/verilated.mk file has optimization turned off.
783 This is for the benefit of new users, as it improves compile times at
784 the cost of runtimes. To add optimization as the default, set one of
785 three variables, OPT, OPT_FAST, or OPT_SLOW in lib/verilated.mk. Or,
786 just for one run, pass them on the command line to make:
787 make OPT_FAST="-O2" -f Vour.mk Vour__ALL.a
789 OPT_FAST specifies optimizations for those programs that are part of
791 the fast path, mostly code that is executed every cycle. OPT_SLOW
792 specifies optimizations for slow-path files (plus tracing), which
793 execute only rarely, yet take a long time to compile with optimization
794 on. OPT specifies overall optimization and affects all compiles,
795 including those OPT_FAST and OPT_SLOW affect. For best results, use
796 OPT="-O2", and link with "-static". Nearly the same results can be had
797 with much better compile times with OPT_FAST="-O1 -fstrict-aliasing".
798 Unfortunately, using the optimizer with SystemC files can result in
800 compiles taking several minutes. (The SystemC libraries have many
801 little inlined functions that drive the compiler nuts.)
802 For best results, use GCC 3.3 or newer. GCC 3.2 and earlier have
804 optimization bugs around pointer aliasing detection, which can result
805 in 2x performance losses.
806 If you will be running many simulations on a single compile,
808 investigate feedback driven compilation. With GCC, using
809 -fprofile-arcs, then -fbranch-probabilities will yield another 15% or
810 so.
811 You may uncover further tuning possibilities by profiling the Verilog
813 code. Use Verilator's --profile-cfuncs, then GCC's -g -pg. You can
814 then run either oprofile or gprof to see where in the C++ code the time
815 is spent. Run the gprof output through verilator_profcfunc and it will
816 tell you what Verilog line numbers on which most of the time is being
817 spent.
818 When done, please let the author know the results. I like to keep tabs
820 on how Verilator compares, and may be able to suggest additional
821 improvements.
822
824 All output files are placed in the output directory name specified with
825 the -Mdir option, or "obj_dir" if not specified.
826 Verilator creates the following files in the output directory:
828 {prefix}.mk // Make include file for compiling
830 {prefix}_classes.mk // Make include file with class names
831 For -cc and -sc mode, it also creates:
833 {prefix}.cpp // Top level C++ file
835 {prefix}.h // Top level header
836 {prefix}{each_verilog_module}.cpp // Lower level internal C++ files
837 {prefix}{each_verilog_module}.h // Lower level internal header files
838 For -sp mode, instead of .cpp and .h it creates:
840 {prefix}.sp // Top level SystemC file
842 {prefix}{each_verilog_module}.sp // Lower level internal SC files
843 In certain optimization modes, it also creates:
845 {prefix}__Dpi.h // DPI import and export declarations
847 {prefix}__Inlines.h // Inline support functions
848 {prefix}__Slow.cpp // Constructors and infrequent routines
849 {prefix}__Syms.cpp // Global symbol table C++
850 {prefix}__Syms.h // Global symbol table header
851 {prefix}__Trace.cpp // Wave file generation code (--trace)
852 {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc)
853 {prefix}__stats.txt // Statistics (--stats)
854 It also creates internal files that can be mostly ignored:
856 {each_verilog_module}.vpp // Post-processed verilog (--debug)
858 {prefix}.flags_vbin // Verilator dependencies
859 {prefix}.flags_vpp // Pre-processor dependencies
860 {prefix}__verFiles.dat // Timestamps for skip-identical
861 {prefix}{misc}.d // Make dependencies (-MMD)
862 {prefix}{misc}.dot // Debugging graph files (--debug)
863 {prefix}{misc}.tree // Debugging files (--debug)
864 After running Make, the C++ compiler should produce the following:
866 {prefix} // Final executable (w/--exe argument)
868 {prefix}__ALL.a // Library of all Verilated objects
869 {prefix}{misc}.o // Intermediate objects
870
872 OBJCACHE
873 Optionally specifies a caching or distribution program to place in
874 front of all runs of the C++ Compiler. For example, "objcache
875 --read --write", or "ccache". If using distcc, it would generally
876 be run under either objcache or ccache; see the documentation for
877 those programs.
878 OBJCACHE_JOBS
880 Optionally lists Make flags that specifies parallel make jobs. For
881 example a 4 CPU system may use "-j 6" to request 6 parallel
882 compiles when making.
883 SYSTEMC
885 Required for SystemC output mode. If set, specifies the directory
886 containing the SystemC distribution. This is used to find the
887 SystemC include files. If not specified, it will come from a
888 default optionally specified at configure time (before Verilator
889 was compiled).
890 SYSTEMC_ARCH
892 Specifies the architecture name used by the SystemC kit. This is
893 the part after the dash in the lib-{...} directory name created by
894 a 'make' in the SystemC distribution. If not set, Verilator will
895 try to intuit the proper setting, or use the default optionally
896 specified at configure time (before Verilator was compiled). .
897 SYSTEMC_CXX_FLAGS
899 Specifies additional flags that are required to be passed to GCC
900 when building the SystemC model.
901 SYSTEMPERL
903 Specifies the directory containing the SystemPerl distribution kit.
904 This is used to find the SystemPerl library and include files. If
905 not specified, it will come from a default optionally specified at
906 configure time (before Verilator was compiled). See also
907 SYSTEMPERL_INCLUDE.
908 SYSTEMPERL_INCLUDE
910 Specifies the directory containing the Verilog-Perl include .cpp
911 files, from the src/ directory of the SystemPerl kit. If not
912 specified, it will be computed from the SYSTEMPERL environment
913 variable if it is set, and if SYSTEMPERL is not set
914 SYSTEMPERL_INCLUDE will come from a default optionally specified at
915 configure time (before Verilator was compiled).
916 VCS_HOME
918 If set, specifies the directory containing the Synopsys VCS
919 distribution. When set, a 'make test' in the Verilator
920 distribution will also run VCS baseline regression tests.
921 VERILATOR_BIN
923 If set, specifies an alternative name of the Verilator binary. May
924 be used for debugging and selecting between multiple operating
925 system builds.
926 VERILATOR_ROOT
928 Specifies the directory containing the distribution kit. This is
929 used to find the executable, Perl library, and include files. If
930 not specified, it will come from a default optionally specified at
931 configure time (before Verilator was compiled).
932
934 Verilator creates a .h and .cpp file for the top level module and all
935 modules under it. See the test_c directory in the kit for an example.
936 After the modules are completed, there will be a module.mk file that
938 may be used with Make to produce a module__ALL.a file with all required
939 objects in it. This is then linked with the user's top level to create
940 the simulation executable.
941 The user must write the top level of the simulation. Here's a simple
943 example:
944 #include <verilated.h> // Defines common routines
946 #include "Vtop.h" // From Verilating "top.v"
947 Vtop *top; // Instantiation of module
949 unsigned int main_time = 0; // Current simulation time
951 double sc_time_stamp () { // Called by $time in Verilog
953 return main_time;
954 }
955 int main(int argc, char** argv) {
957 Verilated::commandArgs(argc, argv); // Remember args
958 top = new Vtop; // Create instance
960 top->reset_l = 0; // Set some inputs
962 while (!Verilated::gotFinish()) {
964 if (main_time > 10) {
965 top->reset_l = 1; // Deassert reset
966 }
967 if ((main_time % 10) == 1) {
968 top->clk = 1; // Toggle clock
969 }
970 if ((main_time % 10) == 6) {
971 top->clk = 0;
972 }
973 top->eval(); // Evaluate model
974 cout << top->out << endl; // Read a output
975 main_time++; // Time passes...
976 }
977 top->final(); // Done simulating
979 // // (Though this example doesn't get here)
980 }
981 Note signals are read and written as member variables of the lower
983 module. You call the eval() method to evaluate the model. When the
984 simulation is complete call the final() method to wrap up any
985 SystemVerilog final blocks, and complete any assertions.
986
988 Verilator will convert the top level module to a SC_MODULE. This
989 module will plug directly into a SystemC netlist.
990 The SC_MODULE gets the same pinout as the Verilog module, with the
992 following type conversions: Pins of a single bit become bool. Pins
993 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's
994 or uint64_t's depending on the --no-pins64 switch. Wider pins become
995 sc_bv's. (Uints simulate the fastest so are used where possible.)
996 Lower modules are not pure SystemC code. This is a feature, as using
998 the SystemC pin interconnect scheme everywhere would reduce performance
999 by an order of magnitude.
1000
1002 Verilator supports SystemVerilog Direct Programming Interface import
1003 and export statements. Only the SystemVerilog form ("DPI-C") is
1004 supported, not the original Synopsys-only DPI.
1005 DPI Example
1007 In the SYSTEMC example above, if you wanted to import C++ functions
1009 into Verilog, put in our.v:
1010 import "DPI-C" function integer add (input integer a, input integer b);
1012 initial begin
1014 $display("%x + %x = %x", 1, 2, add(1,2));
1015 endtask
1016 Then after Verilating, Verilator will create a file Vour__Dpi.h with
1018 the prototype to call this function:
1019 extern int add (int a, int b);
1021 From the sc_main.cpp file (or another .cpp file passed to the Verilator
1023 command line, or the link), you'd then:
1024 #include "svdpi.h"
1026 #include "Vour__Dpi.h"
1027 int add (int a, int b) { return a+b; }
1028 DPI System Task/Functions
1030 Verilator extends the DPI format to allow using the same scheme to
1032 efficiently add system functions. Simply use a dollar-sign prefixed
1033 system function name for the import, but note it must be escaped.
1034 export "DPI-C" function integer \$myRand;
1036 initial $display("myRand=%d", $myRand());
1038 Going the other direction, you can export Verilog tasks so they can be
1040 called from C++:
1041 export "DPI-C" task publicSetBool;
1043 task publicSetBool;
1045 input bit in_bool;
1046 var_bool = in_bool;
1047 endtask
1048 Then after Verilating, Verilator will create a file Vour__Dpi.h with
1050 the prototype to call this function:
1051 extern bool publicSetBool(bool in_bool);
1053 From the sc_main.cpp file, you'd then:
1055 #include "Vour__Dpi.h"
1057 publicSetBool(value);
1058 Or, alternatively, call the function under the design class. This
1060 isn't DPI compatible but is easier to read and better supports multiple
1061 designs.
1062 #include "Vour__Dpi.h"
1064 Vour::publicSetBool(value);
1065 // or top->publicSetBool(value);
1066 DPI Display Functions
1068 Verilator allows writing $display like functions using this syntax:
1070 import "DPI-C" function void
1072 \$my_display (input string formatted /*verilator sformat*/ );
1073 The /*verilator sformat*/ indicates that this function accepts a
1075 $display like format specifier followed by any number of arguments to
1076 satisfy the format.
1077 DPI Header Isolation
1079 Verilator places the IEEE standard header files such as svdpi.h into a
1081 separate include directory, vltstd (VeriLaTor STandarD). When
1082 compiling most applications $VERILATOR_ROOT/include/vltstd would be in
1083 the include path along with the normal $VERILATOR_ROOT/include.
1084 However, when compiling Verilated models into other simulators which
1085 have their own svdpi.h and similar standard files with different
1086 contents, the vltstd directory should not be included to prevent
1087 picking up incompatible definitions.
1088 Public Functions
1090 Instead of DPI exporting, there's also Verilator public functions,
1092 which are slightly faster, but less compatible.
1093
1095 Verilator supports cross-compiling Verilated code. This is generally
1096 used to run Verilator on a Linux system and produce C++ code that is
1097 then compiled on Windows.
1098 Cross compilation involves up to three different OSes. The build
1100 system is where you configured and compiled Verilator, the host system
1101 where you run Verilator, and the target system where you compile the
1102 Verilated code and run the simulation.
1103 Currently, Verilator requires the build and host system type to be the
1105 same, though the target system type may be different. To support this,
1106 ./configure and make Verilator on the build system. Then, run
1107 Verilator on the host system. Finally, the output of Verilator may be
1108 compiled on the different target system.
1109 To support this, none of the files that Verilator produces will
1111 reference any configure generated build-system specific files, such as
1112 config.h (which is renamed in Verilator to config_build.h to reduce
1113 confusion.) The disadvantage of this approach is that
1114 include/verilatedos.h must self-detect the requirements of the target
1115 system, rather than using configure.
1116 The target system may also require edits to the Makefiles, the simple
1118 Makefiles produced by Verilator presume the target system is the same
1119 type as the build system.
1120 Cadence NC-SystemC Models
1122 Similar to compiling Verilated designs with gcc, Verilated designs may
1124 be compiled inside other simulators that support C++ or SystemC models.
1125 One such simulator is Cadence's NC-SystemC, part of their Incisive
1126 Verification Suite. (Highly recommended.)
1127 Using the example files above, the following command will build the
1129 model underneath NC:
1130 cd obj_dir
1132 ncsc_run \
1133 sc_main.cpp \
1134 Vour__ALLcls.cpp \
1135 Vour__ALLsup.cpp \
1136 verilated.cpp
1137 For larger designs you'll want to automate this using makefiles, which
1139 pull the names of the .cpp files to compile in from the make variables
1140 generated in obj_dir/Vour_classes.mk.
1141
1143 In addition to the command line, warnings and other features may be
1144 controlled by configuration files, typically named with the .vlt
1145 extension. An example:
1146 `verilator_config
1148 lint_off -msg WIDTH
1149 lint_off -msg CASEX -file "silly_vendor_code.v"
1150 This disables WIDTH warnings globally, and CASEX for a specific file.
1152 Configuration files are parsed after the normal Verilog preprocessing,
1154 so `ifdefs, `defines, and comments may be used as if it were normal
1155 Verilog code.
1156 The grammar of configuration commands is as follows:
1158 `verilator_config
1160 Take remaining text up the the next `verilog mode switch and treat
1161 it as Verilator configuration commands.
1162 coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]]
1164 Disable coverage for the specified filename (or all files if
1165 omitted) and range of line numbers (or all lines if omitted).
1166 Often used to ignore an entire module for coverage analysis
1167 purposes.
1168 lint_off -msg <message> [-file "<filename>" [-lines <line> [ -
1170 <line>]]]
1171 Disables the specified lint warning in the specified filename (or
1172 all files if omitted) and range of line numbers (or all lines if
1173 omitted).
1174 tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]
1176 Disable waveform tracing for all future signals declared in the
1177 specified filename (or all files if omitted) and range of line
1178 numbers (or all lines if omitted).
1179
1181 Verilog 2001 (IEEE 1364-2001) Support
1182 Verilator supports most Verilog 2001 language features. This includes
1184 signed numbers, "always @*", generate statements, multidimensional
1185 arrays, localparam, and C-style declarations inside port lists.
1186 Verilog 2005 (IEEE 1364-2005) Support
1188 Verilator supports most Verilog 2005 language features. This includes
1190 the `begin_keywords and `end_keywords compiler directives, $clog2, and
1191 the uwire keyword.
1192 SystemVerilog 2005 (IEEE 1800-2005) Support
1194 Verilator currently has some support for SystemVerilog synthesis
1196 constructs. As SystemVerilog features enter common usage they are
1197 added; please file a bug if a feature you need is missing.
1198 Verilator supports ==? and !=? operators, ++ and -- in some contexts,
1200 $bits, $countones, $error, $fatal, $info, $isunknown, $onehot,
1201 $onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit,
1202 byte, chandle, do-while, enum, export, final, import, int, logic,
1203 longint, package, program, shortint, time, typedef, var, void, priority
1204 case/if, and unique case/if.
1205 It also supports .name and .* interconnection.
1207 Verilator partially supports concurrent assert and cover statements;
1209 see the enclosed coverage tests for the syntax which is allowed.
1210 SystemVerilog 2009 (IEEE 1800-2009) Support
1212 Verilator implements a full SystemVerilog 2009 preprocessor, including
1214 function call-like preprocessor defines, default define arguments,
1215 `__FILE__, `__LINE__ and `undefineall.
1216 Verilator currently has some support for SystemVerilog 2009 synthesis
1218 constructs. As SystemVerilog features enter common usage they are
1219 added; please file a bug if a feature you need is missing.
1220 Sugar/PSL Support
1222 Most future work is being directed towards improving SystemVerilog
1224 assertions instead of PSL. If you are using these PSL features, please
1225 contact the author as they may be depreciated in future versions.
1226 With the --assert switch, Verilator enables support of the Property
1228 Specification Language (PSL), specifically the simple PSL subset
1229 without time-branching primitives. Verilator currently only converts
1230 PSL assertions to simple "if (...) error" statements, and coverage
1231 statements to increment the line counters described in the coverage
1232 section.
1233 Verilator implements these keywords: assert, assume (same as assert),
1235 default (for clocking), countones, cover, isunknown, onehot, onehot0,
1236 report, and true.
1237 Verilator implements these operators: -> (logical if).
1239 Verilator does not support SEREs yet. All assertion and coverage
1241 statements must be simple expressions that complete in one cycle. PSL
1242 vmode/vprop/vunits are not supported. PSL statements must be in the
1243 module they reference, at the module level where you would put an
1244 initial... statement.
1245 Verilator only supports (posedge CLK) or (negedge CLK), where CLK is
1247 the name of a one bit signal. You may not use arbitrary expressions as
1248 assertion clocks.
1249 Synthesis Directive Assertion Support
1251 With the --assert switch, Verilator reads any "//synopsys full_case" or
1253 "// synopsys parallel_case" directives. The same applies to any
1254 "//cadence" or "// ambit synthesis" directives of the same form.
1255 When these synthesis directives are discovered, Verilator will either
1257 formally prove the directive to be true, or failing that, will insert
1258 the appropriate code to detect failing cases at runtime and print an
1259 "Assertion failed" error message.
1260 Verilator likewise also asserts any "unique" or "priority"
1262 SystemVerilog keywords on case statements. However, "unique if" and
1263 "priority if" are currently simply ignored.
1264
1266 The following additional constructs are the extensions Verilator
1267 supports on top of standard Verilog code. Using these features outside
1268 of comments or `ifdef's may break other tools.
1269 `__FILE__
1271 The __FILE__ define expands to the current filename as a string,
1272 like C++'s __FILE__. This was incorporated into to the 1800-2009
1273 standard (but supported by Verilator since 2006!)
1274 `__LINE__
1276 The __LINE__ define expands to the current filename as a string,
1277 like C++'s __LINE__. This was incorporated into to the 1800-2009
1278 standard (but supported by Verilator since 2006!)
1279 `error string
1281 This will report an error when encountered, like C++'s #error.
1282 _(expr)
1284 A underline followed by an expression in parenthesis returns a
1285 Verilog expression. This is different from normal parenthesis in
1286 special contexts, such as PSL expressions, and can be used to embed
1287 bit concatenation ({}) inside of PSL statements.
1288 $c(string, ...);
1290 The string will be embedded directly in the output C++ code at the
1291 point where the surrounding Verilog code is compiled. It may
1292 either be a standalone statement (with a trailing ; in the string),
1293 or a function that returns up to a 32-bit number (without a
1294 trailing ;). This can be used to call C++ functions from your
1295 Verilog code.
1296 String arguments will be put directly into the output C++ code.
1298 Expression arguments will have the code to evaluate the expression
1299 inserted. Thus to call a C++ function, $c("func(",a,")") will
1300 result in 'func(a)' in the output C++ code. For input arguments,
1301 rather than hard-coding variable names in the string $c("func(a)"),
1302 instead pass the variable as an expression $c("func(",a,")"). This
1303 will allow the call to work inside Verilog functions where the
1304 variable is flattened out, and also enable other optimizations.
1305 If you will be reading or writing any Verilog variables inside the
1307 C++ functions, the Verilog signals must be declared with
1308 /*verilator public*/.
1309 You may also append a arbitrary number to $c, generally the width
1311 of the output. [signal_32_bits = $c32("...");] This allows for
1312 compatibility with other simulators which require a differently
1313 named PLI function name for each different output width.
1314 $display, $write, $fdisplay, $fwrite, $sformat, $swrite
1316 Format arguments may use C fprintf sizes after the % escape. Per
1317 the Verilog standard, %x prints a number with the natural width,
1318 and %0x prints a number with minimum width. Verilator extends this
1319 so %5x prints 5 digits per the C standard (it's unspecified in
1320 Verilog).
1321 `coverage_block_off
1323 Specifies the entire begin/end block should be ignored for coverage
1324 analysis. Same as /* verilator coverage_block_off */.
1325 `systemc_header
1327 Take remaining text up to the next `verilog or `systemc_... mode
1328 switch and place it verbatim into the output .h file's header.
1329 Despite the name of this macro, this also works in pure C++ code.
1330 `systemc_ctor
1332 Take remaining text up to the next `verilog or `systemc_... mode
1333 switch and place it verbatim into the C++ class constructor.
1334 Despite the name of this macro, this also works in pure C++ code.
1335 `systemc_dtor
1337 Take remaining text up to the next `verilog or `systemc_... mode
1338 switch and place it verbatim into the C++ class destructor.
1339 Despite the name of this macro, this also works in pure C++ code.
1340 `systemc_interface
1342 Take remaining text up to the next `verilog or `systemc_... mode
1343 switch and place it verbatim into the C++ class interface. Despite
1344 the name of this macro, this also works in pure C++ code.
1345 `systemc_imp_header
1347 Take remaining text up to the next `verilog or `systemc_... mode
1348 switch and place it verbatim into the header of all files for this
1349 C++ class implementation. Despite the name of this macro, this
1350 also works in pure C++ code.
1351 `systemc_implementation
1353 Take remaining text up to the next `verilog or `systemc_... mode
1354 switch and place it verbatim into a single file of the C++ class
1355 implementation. Despite the name of this macro, this also works in
1356 pure C++ code.
1357 If you will be reading or writing any Verilog variables in the C++
1359 functions, the Verilog signals must be declared with /*verilator
1360 public*/. See also the public task feature; writing a accessor may
1361 result in cleaner code.
1362 `VERILATOR
1364 `verilator
1365 `verilator3
1366 The VERILATOR, verilator and verilator3 defines are set by default
1367 so you may `ifdef around compiler specific constructs.
1368 `verilator_config
1370 Take remaining text up the the next `verilog mode switch and treat
1371 it as Verilator configuration commands.
1372 `verilog
1374 Switch back to processing Verilog code after a `systemc_... mode
1375 switch. The Verilog code returns to the last language mode
1376 specified with `begin_keywords, or SystemVerilog if none were
1377 specified.
1378 /*verilator clock_enable*/
1380 Used after a signal declaration to indicate the signal is used to
1381 gate a clock, and the user takes responsibility for insuring there
1382 are no races related to it. (Typically by adding a latch, and
1383 running static timing analysis.) This will cause the clock gate to
1384 be ignored in the scheduling algorithm, improving performance.
1385 It's also a good idea to enable the IMPERFECTSCH warning, to insure
1386 all clock enables are properly recognized.
1387 /*verilator coverage_block_off*/
1389 Specifies the entire begin/end block should be ignored for coverage
1390 analysis purposes.
1391 /*verilator coverage_off*/
1393 Specifies that following lines of code should have coverage
1394 disabled. Often used to ignore an entire module for coverage
1395 analysis purposes.
1396 /*verilator coverage_on*/
1398 Specifies that following lines of code should have coverage re-
1399 enabled (if appropriate --coverage flags are passed) after being
1400 disabled earlier with /*verilator coverage_off*/.
1401 /*verilator inline_module*/
1403 Specifies the module the comment appears in may be inlined into any
1404 modules that use this module. This is useful to speed up
1405 simulation time with some small loss of trace visibility and
1406 modularity. Note signals under inlined submodules will be named
1407 submodule__DOT__subsignal as C++ does not allow "." in signal
1408 names. SystemPerl when tracing such signals will replace the
1409 __DOT__ with the period.
1410 /*verilator isolate_assignments*/
1412 Used after a signal declaration to indicate the assignments to this
1413 signal in any blocks should be isolated into new blocks. When
1414 there is a large combinatorial block that is resulting in a
1415 UNOPTFLAT warning, attaching this to the signal causing a false
1416 loop may clear up the problem.
1417 IE, with the following
1419 reg splitme /* verilator isolate_assignments*/;
1421 // Note the placement of the semicolon above
1422 always @* begin
1423 if (....) begin
1424 splitme = ....;
1425 other assignments
1426 end
1427 end
1428 Verilator will internally split the block that assigns to "splitme"
1430 into two blocks:
1431 It would then internally break it into (sort of):
1433 // All assignments excluding those to splitme
1435 always @* begin
1436 if (....) begin
1437 other assignments
1438 end
1439 end
1440 // All assignments to splitme
1441 always @* begin
1442 if (....) begin
1443 splitme = ....;
1444 end
1445 end
1446 /*verilator lint_off msg*/
1448 Disable the specified warning message for any warnings following
1449 the comment.
1450 /*verilator lint_on msg*/
1452 Re-enable the specified warning message for any warnings following
1453 the comment.
1454 /*verilator lint_restore*/
1456 After a /*verilator lint_save*/, pop the stack containing lint
1457 message state. Often this is useful at the bottom of include
1458 files.
1459 /*verilator lint_save*/
1461 Push the current state of what lint messages are turned on or
1462 turned off to a stack. Later meta-comments may then lint_on or
1463 lint_off specific messages, then return to the earlier message
1464 state by using /*verilator lint_restore*/. For example:
1465 // verilator lint_save
1467 // verilator lint_off SOME_WARNING
1468 ... // code needing SOME_WARNING turned off
1469 // verilator lint_restore
1470 If SOME_WARNING was on before the lint_off, it will now be restored
1472 to on, and if it was off before the lint_off it will remain off.
1473 /*verilator no_inline_task*/
1475 Used in a function or task variable definition section to specify
1476 the function or task should not be inlined into where it is used.
1477 This may reduce the size of the final executable when a task is
1478 used a very large number of times. For this flag to work, the task
1479 and tasks below it must be pure; they cannot reference any
1480 variables outside the task itself.
1481 /*verilator public*/ (variable)
1483 Used after a input, output, register, or wire declaration to
1484 indicate the signal should be declared so that C code may read or
1485 write the value of the signal. This will also declare this module
1486 public, otherwise use /*verilator public_flat*/.
1487 Instead of using public variables, consider instead making a DPI or
1489 public function that accesses the variable. This is nicer as it
1490 provides an obvious entry point that is also compatible across
1491 simulators.
1492 /*verilator public*/ (task/function)
1494 Used inside the declaration section of a function or task
1495 declaration to indicate the function or task should be made into a
1496 C++ function, public to outside callers. Public tasks will be
1497 declared as a void C++ function, public functions will get the
1498 appropriate non-void (bool, uint32_t, etc) return type. Any input
1499 arguments will become C++ arguments to the function. Any output
1500 arguments will become C++ reference arguments. Any local
1501 registers/integers will become function automatic variables on the
1502 stack.
1503 Wide variables over 64 bits cannot be function returns, to avoid
1505 exposing complexities. However, wide variables can be
1506 input/outputs; they will be passed as references to an array of 32
1507 bit numbers.
1508 Generally, only the values of stored state (flops) should be
1510 written, as the model will NOT notice changes made to variables in
1511 these functions. (Same as when a signal is declared public.)
1512 You may want to use DPI exports instead, as it's compatible with
1514 other simulators.
1515 /*verilator public_flat*/ (variable)
1517 Used after a input, output, register, or wire declaration to
1518 indicate the signal should be declared so that C code may read or
1519 write the value of the signal. This will not declare this module
1520 public, which means the name of the signal or path to it may change
1521 based upon the module inlining which takes place.
1522 /*verilator public_flat_rd*/ (variable)
1524 Used after a input, output, register, or wire declaration to
1525 indicate the signal should be declared public_flat (see above), but
1526 read-only.
1527 /*verilator public_flat_rw @(<edge_list>) */ (variable)
1529 Used after a input, output, register, or wire declaration to
1530 indicate the signal should be declared public_flat_rd (see above),
1531 and also writable, where writes should be considered to have the
1532 timing specified by the given sensitivity edge list.
1533 /*verilator public_module*/
1535 Used after a module statement to indicate the module should not be
1536 inlined (unless specifically requested) so that C code may access
1537 the module. Verilator automatically sets this attribute when the
1538 module contains any public signals or `systemc_ directives. Also
1539 set for all modules when using the --public switch.
1540 /*verilator sc_clock*/
1542 Rarely needed. Used after a input declaration to indicate the
1543 signal should be declared in SystemC as a sc_clock instead of a
1544 bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0
1545 and later do not require clock pins to be sc_clocks and this is no
1546 longer needed.
1547 /*verilator sformat*/
1549 Attached to the final input of a function or task "input string" to
1550 indicate the function or task should pass all remaining arguments
1551 through $sformatf. This allows creation of DPI functions with
1552 $display like behavior. See the test_regress/t/t_dpi_display.v
1553 file for an example.
1554 /*verilator tracing_off*/
1556 Disable waveform tracing for all future signals that are declared
1557 in this module. Often this is placed just after a primitive's
1558 module statement, so that the entire module is not traced.
1559 /*verilator tracing_on*/
1561 Re-enable waveform tracing for all future signals that are
1562 declared.
1563
1565 There are some limitations and lack of features relative to a
1566 commercial simulator, by intent. User beware.
1567 It is strongly recommended you use a lint tool before running this
1569 program. Verilator isn't designed to easily uncover common mistakes
1570 that a lint program will find for you.
1571 Synthesis Subset
1573 Verilator supports only the Synthesis subset with a few minor additions
1575 such as $stop, $finish and $display. That is, you cannot use
1576 hierarchical references, events or similar features of the Verilog
1577 language. It also simulates as Synopsys's Design Compiler would;
1578 namely a block of the form:
1579 always @ (x) y = x & z;
1581 This will recompute y when there is even a potential for change in x or
1583 a change in z, that is when the flops computing x or z evaluate (which
1584 is what Design Compiler will synthesize.) A compliant simulator would
1585 only calculate y if x changes. Use verilog-mode's /*AS*/ or Verilog
1586 2001's always @* to reduce missing activity items. Avoid putting
1587 $displays in combo blocks, as they may print multiple times when not
1588 desired, even on compliant simulators as event ordering is not
1589 specified.
1590 Dotted cross-hierarchy references
1592 Verilator supports dotted references to variables, functions and tasks
1594 in different modules. However, references into named blocks and
1595 function-local variables are not supported. The portion before the dot
1596 must have a constant value; for example a[2].b is acceptable, while
1597 a[x].b is not.
1598 References into generated and arrayed instances use the instance names
1600 specified in the Verilog standard; arrayed instances are named
1601 {cellName}[{instanceNumber}] in Verilog, which becomes
1602 {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code.
1603 Verilator creates numbered "genblk" when a begin: name is not specified
1605 around a block inside a generate statement. These numbers may differ
1606 between other simulators, but the Verilog specification does not allow
1607 users to use these names, so it should not matter.
1608 If you are having trouble determining where a dotted path goes wrong,
1610 note that Verilator will print a list of known scopes to help your
1611 debugging.
1612 Floating Point
1614 Floating Point numbers are not synthesizable, and so not supported.
1616 Latches
1618 Verilator is optimized for edge sensitive (flop based) designs. It
1620 will attempt to do the correct thing for latches, but most performance
1621 optimizations will be disabled around the latch.
1622 Time
1624 All delays (#) are ignored, as they are in synthesis.
1626 Two State
1628 Verilator is a two state simulator, not a four state simulator.
1630 However, it has two features which uncover most initialization bugs
1631 (including many that a four state simulator will miss.)
1632 First, assigning a variable to a X will actually assign the variable to
1634 a random value (see the -x-assign switch.) Thus if the value is
1635 actually used, the random value should cause downstream errors.
1636 Integers also randomize, even though the Verilog 2001 specification
1637 says they initialize to zero.
1638 Identity comparisons (=== or !==) are converted to standard ==/!== when
1640 neither side is a constant. This may make the expression result differ
1641 from a four state simulator.
1642 All variables are initialized using a function. By running several
1644 random simulation runs you can determine that reset is working
1645 correctly. On the first run, the function initializes variables to
1646 zero. On the second, have it initialize variables to one. On the
1647 third and following runs have it initialize them randomly. If the
1648 results match, reset works. (Note this is what the hardware will
1649 really do.) In practice, just setting all variables to one at startup
1650 finds most problems.
1651 Tri/Inout
1653 Verilator converts some simple tristate structures into two state. An
1655 assignment of the form:
1656 inout driver;
1658 wire driver = (enable) ? output_value : 1'bz;
1659 Will be converted to
1661 input driver__in; // Value being driven in from "external" drivers
1663 output driver__en; // True if driven from this module
1664 output driver__enout; // Value being driven from this module
1665 Pullup, pulldown, bufif0, bufif1, notif0, notif1 are also supported.
1667 External logic will be needed to combine these signals with any
1668 external drivers.
1669 Tristate drivers are not supported inside functions and tasks; a inout
1671 there will be considered a two state variable that is read and written
1672 instead of a four state variable.
1673 Functions & Tasks
1675 All functions and tasks will be inlined (will not become functions in
1677 C.) The only support provided is for simple statements in tasks (which
1678 may affect global variables).
1679 Recursive functions and tasks are not supported. All inputs and
1681 outputs are automatic, as if they had the Verilog 2001 "automatic"
1682 keyword prepended. (If you don't know what this means, Verilator will
1683 do what you probably expect -- what C does. The default behavior of
1684 Verilog is different.)
1685 Generated Clocks
1687 Verilator attempts to deal with generated clocks correctly, however new
1689 cases may turn up bugs in the scheduling algorithm. The safest option
1690 is to have all clocks as primary inputs to the model, or wires directly
1691 attached to primary inputs.
1692 Ranges must be big-bit-endian
1694 Bit ranges must be numbered with the MSB being numbered greater or the
1696 same as the LSB. Little-bit-endian busses [0:15] are not supported as
1697 they aren't easily made compatible with C++.
1698 Gate Primitives
1700 The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor)
1702 are directly converted to behavioral equivalents. The 3-state and MOS
1703 gate primitives are not supported. Tables are not supported.
1704 Specify blocks
1706 All specify blocks and timing checks are ignored.
1708 Array Initialization
1710 When initializing a large array, you need to use non-delayed
1712 assignments. Verilator will tell you when this needs to be fixed; see
1713 the BLKLOOPINIT error for more information.
1714 Array Out of Bounds
1716 Writing a memory element that is outside the bounds specified for the
1718 array may cause a different memory element inside the array to be
1719 written instead. For power-of-2 sized arrays, Verilator will give a
1720 width warning and the address. For non-power-of-2-sizes arrays, index
1721 0 will be written.
1722 Reading a memory element that is outside the bounds specified for the
1724 array will give a width warning and wrap around the power-of-2 size.
1725 For non-power-of-2 sizes, it will return a unspecified constant of the
1726 appropriate width.
1727 Assertions
1729 Verilator is beginning to add support for assertions. Verilator
1731 currently only converts assertions to simple "if (...) error"
1732 statements, and coverage statements to increment the line counters
1733 described in the coverage section.
1734 Verilator does not support SEREs yet. All assertion and coverage
1736 statements must be simple expressions that complete in one cycle.
1737 (Arguably SEREs are much of the point, but one must start somewhere.)
1738 Language Keyword Limitations
1740 This section describes specific limitations for each language keyword.
1742 `__FILE__, `__LINE__, `begin_keywords, `begin_keywords,
1744 `begin_keywords, `begin_keywords, `begin_keywords, `define, `else,
1745 `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include,
1746 `line, `systemc_ctor, `systemc_dtor, `systemc_header,
1747 `systemc_imp_header, `systemc_implementation, `systemc_interface,
1748 `timescale, `undef, `verilog
1749 Fully supported.
1750 always, always_comb, always_ff, always_latch, and, assign, begin, buf,
1752 byte, case, casex, casez, default, defparam, do-while, else, end,
1753 endcase, endfunction, endgenerate, endmodule, endspecify, endtask,
1754 final, for, function, generate, genvar, if, initial, inout, input, int,
1755 integer, localparam, logic, longint, macromodule, module, nand,
1756 negedge, nor, not, or, output, parameter, posedge, reg, scalared,
1757 shortint, signed, supply0, supply1, task, time, tri, typedef, var,
1758 vectored, while, wire, xnor, xor
1759 Generally supported.
1760 chandle
1762 Treated as a "longint"; does not yet warn about operations that are
1763 specified as illegal on chandles.
1764 priority if, unique if
1766 Priority and unique if's are treated as normal ifs and not asserted
1767 to be full nor unique.
1768 specify specparam
1770 All specify blocks and timing checks are ignored.
1771 string
1773 String is supported only to the point that they can be passed to
1774 DPI imports.
1775 timeunit, timeprecision
1777 All timing control statements are ignored.
1778 uwire
1780 Verilator does not perform warning checking on uwires, it treats
1781 the uwire keyword as if it were the normal wire keyword.
1782 $bits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot,
1784 $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time,
1785 $unsigned, $warning.
1786 Generally supported.
1787 $display, $write, $fdisplay, $fwrite, $swrite
1789 $display and friends must have a constant format string as the
1790 first argument (as with C's printf). The rare usage which lists
1791 variables standalone without a format is not supported.
1792 $displayb, $displayh, $displayo, $writeb, $writeh, $writeo, etc
1794 The sized display functions are rarely used and so not supported.
1795 Replace them with a $write with the appropriate format specifier.
1796 $finish, $stop
1798 The rarely used optional parameter to $finish and $stop is ignored.
1799 $fopen, $fclose, $fdisplay, $feof, $fflush, $fgetc, $fgets, $fscanf,
1801 $fwrite
1802 File descriptors passed to the file PLI calls must be file
1803 descriptors, not MCDs, which includes the mode parameter to $fopen
1804 being mandatory. Verilator will convert the integer used to hold
1805 the file descriptor into a internal FILE*. To prevent core dumps
1806 due to mis-use, and because integers are 32 bits while FILE*s may
1807 be 64 bits, the descriptor must be stored in a reg [63:0] rather
1808 than an integer. The define `verilator_file_descriptor in
1809 verilated.v can be used to hide this difference.
1810 $fscanf, $sscanf
1812 Only integer formats are supported; %e, %f, %m, %r, %v, and %z are
1813 not supported.
1814 $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
1816 $setup, $setuphold, $skew, $timeskew, $width
1817 All specify blocks and timing checks are ignored.
1818 $random
1820 $random does not support the optional argument to set the seed.
1821 Use the srand function in C to accomplish this, and note there is
1822 only one random number generator (not one per module).
1823 $readmemb, $readmemh
1825 Read memory commands should work properly. Note Verilator and the
1826 Verilog specification does not include support for readmem to
1827 multi-dimensional arrays.
1828 $realtime
1830 Treated as $time.
1831 $test$plusargs, $value$plusargs
1833 Supported, but the instantiating C++/SystemC testbench must call
1834 Verilated::commandArgs(argc, argv);
1836 to register the command line before calling $test$plusargs or
1838 $value$plusargs.
1839 $timeformat
1841 Not supported as Verilator needs to determine all formatting at
1842 compile time. Generally you can just ifdef them out for no ill
1843 effect. Note also VL_TIME_MULTIPLER can be defined at compile time
1844 to move the decimal point when displaying all times, model wide.
1845
1847 Warnings may be disabled in two ways. First, when the warning is
1848 printed it will include a warning code. Simply surround the offending
1849 line with a warn_off/warn_on pair:
1850 // verilator lint_off UNSIGNED
1852 if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
1853 // verilator lint_on UNSIGNED
1854 Warnings may also be globally disabled by invoking Verilator with the
1856 "-Wno-warning" switch. This should be avoided, as it removes all
1857 checking across the designs, and prevents other users from compiling
1858 your code without knowing the magic set of disables needed to
1859 successfully compile your design.
1860 List of all warnings:
1862 BLKANDNBLK
1864 BLKANDNBLK is an error that a variable comes from a mix of blocked
1865 and non-blocking assignments. Generally, this is caused by a
1866 register driven by both combo logic and a flop:
1867 always @ (posedge clk) foo[0] <= ...
1869 always @* foo[1] = ...
1870 Simply use a different register for the flop:
1872 always @ (posedge clk) foo_flopped[0] <= ...
1874 always @* foo[0] = foo_flopped[0];
1875 always @* foo[1] = ...
1876 This is good coding practice anyways.
1878 It is also possible to disable this error when one of the
1880 assignments is inside a public task.
1881 Ignoring this warning may make Verilator simulations differ from
1883 other simulators.
1884 BLKLOOPINIT
1886 This indicates that the initialization of an array needs to use
1887 non-delayed assignments. This is done in the interest of speed; if
1888 delayed assignments were used, the simulator would have to copy
1889 large arrays every cycle. (In smaller loops, loop unrolling allows
1890 the delayed assignment to work, though it's a bit slower than a
1891 non-delayed assignment.) Here's an example
1892 always @ (posedge clk)
1894 if (~reset_l) begin
1895 for (i=0; i<`ARRAY_SIZE; i++) begin
1896 array[i] = 0; // Non-delayed for verilator
1897 end
1898 This message is only seen on large or complicated loops because
1900 Verilator generally unrolls small loops. You may want to try
1901 increasing --unroll-count (and occasionally --unroll-stmts) which
1902 will raise the small loop bar to avoid this error.
1903 CASEINCOMPLETE
1905 Warns that inside a case statement there is a stimulus pattern for
1906 which there is no case item specified. This is bad style, if a
1907 case is impossible, it's better to have a "default: $stop;" or just
1908 "default: ;" so that any design assumption violations will be
1909 discovered in simulation.
1910 Ignoring this warning will only suppress the lint check, it will
1912 simulate correctly.
1913 CASEOVERLAP
1915 Warns that inside a case statement you have case values which are
1916 detected to be overlapping. This is bad style, as moving the order
1917 of case values will cause different behavior. Generally the values
1918 can be respecified to not overlap.
1919 Ignoring this warning will only suppress the lint check, it will
1921 simulate correctly.
1922 CASEX
1924 Warns that it is simply better style to use casez, and "?" in place
1925 of "x"'s. See
1926 <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>
1927 Ignoring this warning will only suppress the lint check, it will
1929 simulate correctly.
1930 CASEWITHX
1932 Warns that a case statement contains a constant with a "x".
1933 Verilator is two-state so interpret such items as always false.
1934 Note a common error is to use a "X" in a case or casez statement
1935 item; often what the user instead intended is to use a casez with
1936 "?".
1937 Ignoring this warning will only suppress the lint check, it will
1939 simulate correctly.
1940 CDCRSTLOGIC
1942 With --cdc only, warns that asynchronous flop reset terms come from
1943 other than primary inputs or flopped outputs, creating the
1944 potential for reset glitches.
1945 CMPCONST
1947 Warns that you are comparing a value in a way that will always be
1948 constant. For example "X > 1" will always be true when X is a
1949 single bit wide.
1950 Ignoring this warning will only suppress the lint check, it will
1952 simulate correctly.
1953 COMBDLY
1955 Warns that you have a delayed assignment inside of a combinatorial
1956 block. Using delayed assignments in this way is considered bad
1957 form, and may lead to the simulator not matching synthesis. If
1958 this message is suppressed, Verilator, like synthesis, will convert
1959 this to a non-delayed assignment, which may result in logic races
1960 or other nasties. See
1961 <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>
1962 Ignoring this warning may make Verilator simulations differ from
1964 other simulators.
1965 GENCLK
1967 Warns that the specified signal is generated, but is also being
1968 used as a clock. Verilator needs to evaluate sequential logic
1969 multiple times in this situation. In somewhat contrived cases
1970 having any generated clock can reduce performance by almost a
1971 factor of two. For fastest results, generate ALL clocks outside in
1972 C++/SystemC and make them primary inputs to your Verilog model.
1973 (However once need to you have even one, don't sweat additional
1974 ones.)
1975 Ignoring this warning may make Verilator simulations differ from
1977 other simulators.
1978 IMPERFECTSCH
1980 Warns that the scheduling of the model is not absolutely perfect,
1981 and some manual code edits may result in faster performance. This
1982 warning defaults to off, and must be turned on explicitly before
1983 the top module statement is processed.
1984 IMPLICIT
1986 Warns that a wire is being implicitly declared (it is a single bit
1987 wide output from a sub-module.) While legal in Verilog, implicit
1988 declarations only work for single bit wide signals (not buses), do
1989 not allow using a signal before it is implicitly declared by a
1990 cell, and can lead to dangling nets. A better option is the
1991 /*AUTOWIRE*/ feature of Verilog-Mode for Emacs, available from
1992 <http://www.veripool.org/>
1993 Ignoring this warning will only suppress the lint check, it will
1995 simulate correctly.
1996 IMPURE
1998 Warns that a task or function that has been marked with /*verilator
1999 no_inline_task*/ references variables that are not local to the
2000 task. Verilator cannot schedule these variables correctly.
2001 Ignoring this warning may make Verilator simulations differ from
2003 other simulators.
2004 LITENDIAN
2006 Warns that a vector is declared with little endian bit numbering
2007 (i.e. [0:7]). Big endian bit numbering is now the overwhelming
2008 standard, and little numbering is now thus often due to simple
2009 oversight instead of intent.
2010 Ignoring this warning will only suppress the lint check, it will
2012 simulate correctly.
2013 MODDUP
2015 Error that a module has multiple definitions. Generally this
2016 indicates a coding error, or a mistake in a library file and it's
2017 good practice to have one module per file to avoid these issues.
2018 For some gate level netlists duplicates are unavoidable, and this
2019 error may be disabled.
2020 MULTIDRIVEN
2022 Warns that the specified signal comes from multiple always blocks.
2023 This is often unsupported by synthesis tools, and is considered bad
2024 style. It will also cause longer runtimes due to reduced
2025 optimizations.
2026 Ignoring this warning will only slow simulations, it will simulate
2028 correctly.
2029 MULTITOP
2031 Error that there are multiple top level modules, that is modules
2032 not instantiated by any other module. Verilator only supports a
2033 single top level, if you need more, create a module that wraps all
2034 of the top modules.
2035 Often this error is because some low level cell is being read in,
2037 but is not really needed. The best solution is to insure that each
2038 module is in a unique file by the same name. Otherwise, make sure
2039 all library files are read in as libraries with -v, instead of
2040 automatically with -y.
2041 REDEFMACRO
2043 Warns that you have redefined the same macro with a different
2044 value, for example:
2045 `define MACRO def1
2047 //...
2048 `define MACRO otherdef
2049 The best solution is to use a different name for the second macro.
2051 If this is not possible, add a undef to indicate the code is
2052 overriding the value:
2053 `define MACRO def1
2055 //...
2056 `undef MACRO
2057 `define MACRO otherdef
2058 STMTDLY
2060 Warns that you have a statement with a delayed time in front of it,
2061 for example:
2062 #100 $finish;
2064 Ignoring this warning may make Verilator simulations differ from
2066 other simulators.
2067 SYMRSVDWORD
2069 Error that a symbol matches a C++ reserved word and using this as a
2070 symbol name would result in odd C compiler errors. You may disable
2071 this error message as you would disable warnings, but the symbol
2072 will be renamed by Verilator to avoid the conflict.
2073 TASKNSVAR
2075 Error when a call to a task or function has a output from that task
2076 tied to a non-simple signal. Instead connect the task output to a
2077 temporary signal of the appropriate width, and use that signal to
2078 set the appropriate expression as the next statement. For example:
2079 task foo; output sig; ... endtask
2081 always @* begin
2082 foo(bus_we_select_from[2]); // Will get TASKNSVAR error
2083 end
2084 Change this to:
2086 reg foo_temp_out;
2088 always @* begin
2089 foo(foo_temp_out);
2090 bus_we_select_from[2] = foo_temp_out;
2091 end
2092 Verilator doesn't do this conversion for you, as some more
2094 complicated cases would result in simulator mismatches.
2095 UNDRIVEN
2097 Warns that the specified signal is never sourced.
2098 Ignoring this warning will only suppress the lint check, it will
2100 simulate correctly.
2101 UNOPT
2103 Warns that due to some construct, optimization of the specified
2104 signal or block is disabled. The construct should be cleaned up to
2105 improve runtime.
2106 A less obvious case of this is when a module instantiates two
2108 submodules. Inside submodule A, signal I is input and signal O is
2109 output. Likewise in submodule B, signal O is an input and I is an
2110 output. A loop exists and a UNOPT warning will result if AI & AO
2111 both come from and go to combinatorial blocks in both submodules,
2112 even if they are unrelated always blocks. This affects performance
2113 because Verilator would have to evaluate each submodule multiple
2114 times to stabilize the signals crossing between the modules.
2115 Ignoring this warning will only slow simulations, it will simulate
2117 correctly.
2118 UNOPTFLAT
2120 Warns that due to some construct, optimization of the specified
2121 signal is disabled. The signal specified includes a complete scope
2122 to the signal; it may be only one particular usage of a multiply
2123 instantiated block. The construct should be cleaned up to improve
2124 runtime; two times better performance may be possible by fixing
2125 these warnings.
2126 Unlike the UNOPT warning, this occurs after netlist flattening, and
2128 indicates a more basic problem, as the less obvious case described
2129 under UNOPT does not apply.
2130 Often UNOPTFLAT is caused by logic that isn't truly circular as
2132 viewed by synthesis which analyzes interconnection per-bit, but is
2133 circular to simulation which analyzes per-bus:
2134 wire [2:0] x = {x[1:0],shift_in};
2136 This statement needs to be evaluated multiple times, as a change in
2138 "shift_in" requires "x" to be computed 3 times before it becomes
2139 stable. This is because a change in "x" requires "x" itself to
2140 change value, which causes the warning.
2141 For significantly better performance, split this into 2 separate
2143 signals:
2144 wire [2:0] xout = {x[1:0],shift_in};
2146 and change all receiving logic to instead receive "xout".
2148 Alternatively, change it to
2149 wire [2:0] x = {xin[1:0],shift_in};
2151 and change all driving logic to instead drive "xin".
2153 With this change this assignment needs to be evaluated only once.
2155 These sort of changes may also speed up your traditional event
2156 driven simulator, as it will result in fewer events per cycle.
2157 The most complicated UNOPTFLAT path we've seen was due to low bits
2159 of a bus being generated from an always statement that consumed
2160 high bits of the same bus processed by another series of always
2161 blocks. The fix is the same; split it into two separate signals
2162 generated from each block.
2163 The UNOPTFLAT warning may also be due to clock enables, identified
2165 from the reported path going through a clock gating cell. To fix
2166 these, use the clock_enable meta comment described above.
2167 The UNOPTFLAT warning may also occur where outputs from a block of
2169 logic are independent, but occur in the same always block. To fix
2170 this, use the isolate_assignments meta comment described above.
2171 Ignoring this warning will only slow simulations, it will simulate
2173 correctly.
2174 UNSIGNED
2176 Warns that you are comparing a unsigned value in a way that implies
2177 it is signed, for example "X < 0" will always be true when X is
2178 unsigned.
2179 Ignoring this warning will only suppress the lint check, it will
2181 simulate correctly.
2182 UNUSED
2184 Warns that the specified signal is never sinked. This is a future
2185 message, currently Verilator will not produce this warning.
2186 Ignoring this warning will only suppress the lint check, it will
2188 simulate correctly.
2189 VARHIDDEN
2191 Warns that a task, function, or begin/end block is declaring a
2192 variable by the same name as a variable in the upper level module
2193 or begin/end block (thus hiding the upper variable from being able
2194 to be used.) Rename the variable to avoid confusion when reading
2195 the code.
2196 Ignoring this warning will only suppress the lint check, it will
2198 simulate correctly.
2199 WIDTH
2201 Warns that based on width rules of Verilog, two operands have
2202 different widths. Verilator generally can intuit the common usages
2203 of widths, and you shouldn't need to disable this message like you
2204 do with most lint programs. Generally other than simple mistakes,
2205 you have two solutions:
2206 If it's a constant 0 that's 32 bits or less, simply leave it
2208 unwidthed. Verilator considers zero to be any width needed.
2209 Concatenate leading zeros when doing arithmetic. In the statement
2211 wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0];
2213 The best fix, which clarifies intent and will also make all tools
2215 happy is:
2216 wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
2218 Ignoring this warning will only suppress the lint check, it will
2220 simulate correctly.
2221 WIDTHCONCAT
2223 Warns that based on width rules of Verilog, a concatenate or
2224 replication has a indeterminate width. In most cases this violates
2225 the Verilog rule that widths inside concatenates and replicates
2226 must be sized, and should be fixed in the code.
2227 wire [63:0] concat = {1,2};
2229 An example where this is technically legal (though still bad form)
2231 is:
2232 parameter PAR = 1;
2234 wire [63:0] concat = {PAR,PAR};
2235 The correct fix is to either size the 1 ("32'h1"), or add the width
2237 to the parameter definition ("parameter [31:0]"), or add the width
2238 to the parameter usage ("{PAR[31:0],PAR[31:0]}".
2239 The following describes the less obvious errors:
2241 Internal Error
2243 This error should never occur first, though may occur if earlier
2244 warnings or error messages have corrupted the program. If there
2245 are no other warnings or errors, submit a bug report.
2246 Unsupported: ....
2248 This error indicates that you are using a Verilog language
2249 construct that is not yet supported in Verilator. See the
2250 Limitations chapter.
2251 Verilated model didn't converge
2253 Verilator sometimes has to evaluate combinatorial logic multiple
2254 times, usually around code where a UNOPTFLAT warning was issued,
2255 but disabled. For example:
2256 always @ (a) b=~a;
2258 always @ (b) a=b
2259 will toggle forever and thus the executable will give the didn't
2261 converge error to prevent an infinite loop.
2262 To debug this, run Verilator with --profile-cfuncs. Run make on
2264 the generated files with "OPT=-DVL_DEBUG". Then call
2265 Verilated::debug(1) in your main.cpp.
2266 This will cause each change in a variable to print a message. Near
2268 the bottom you'll see the code and variable that causes the
2269 problem. For the program above:
2270 CHANGE: filename.v:1: b
2272 CHANGE: filename.v:2: a
2273
2275 Does it run under Windows?
2276 Yes, using Cygwin. Verilated output should also compile under
2277 Microsoft Visual C++ Version 7 or newer, but this is not tested by
2278 the author.
2279 Can you provide binaries?
2281 Verilator is available as a RPM for SuSE, Fedora, and perhaps other
2282 systems; this is done by porters and may slightly lag the primary
2283 distribution. If there isn't a binary build for your distribution,
2284 how about you set one up? Please contact the authors for
2285 assistance.
2286 Note people sometimes request binaries when they are having
2288 problems with their C++ compiler. Alas, binaries won't help this,
2289 as in the end a fully working C++ compiler is required to compile
2290 the output of Verilator.
2291 How can it be faster than (name-the-simulator)?
2293 Generally, the implied part of the question is "... with all of
2294 their manpower they can put into it."
2295 Most commercial simulators have to be Verilog compliant, meaning
2297 event driven. This prevents them from being able to reorder blocks
2298 and make netlist-style optimizations, which are where most of the
2299 gains come from.
2300 Non-compliance shouldn't be scary. Your synthesis program isn't
2302 compliant, so your simulator shouldn't have to be -- and Verilator
2303 is closer to the synthesis interpretation, so this is a good thing
2304 for getting working silicon.
2305 Will Verilator output remain under my own copyright?
2307 Yes, it's just like using GCC on your programs; this is why
2308 Verilator uses the "GNU *Lesser* Public License Version 3" instead
2309 of the more typical "GNU Public License". See the licenses for
2310 details, but in brief, if you change Verilator itself or the header
2311 files Verilator includes, you must make the source code available
2312 under the GNU Lesser Public License. However, Verilator output
2313 (the Verilated code) only "include"s the licensed files, and so you
2314 are NOT required to release any output from Verilator.
2315 You also have the option of using the Perl Artistic License, which
2317 again does not require you release your Verilog or generated code,
2318 and also allows you to modify Verilator for internal use without
2319 distributing the modified version. But please contribute back to
2320 the community!
2321 One limit is that you cannot under either license release a
2323 commercial Verilog simulation product incorporating Verilator
2324 without making the source code available.
2325 Why is Verilation so slow?
2327 Verilator needs more memory than the resulting simulator will
2328 require, as Verilator creates internally all of the state of the
2329 resulting simulator in order to optimize it. If it takes more than
2330 a minute or so (and you're not using --debug since debug is disk
2331 bound), see if your machine is paging; most likely you need to run
2332 it on a machine with more memory. Verilator is a full 64 bit
2333 application and may use more than 4GB, but about 1GB is the maximum
2334 typically needed.
2335 How do I generate waveforms (traces) in C++?
2337 See the next question for tracing in SystemC mode.
2338 Add the --trace switch to Verilator, and in your top level C code,
2340 call Verilated::traceEverOn(true). Then create a VerilatedVcdC
2341 object, and in your main loop call "trace_object->dump(time)" every
2342 time step, and finally call "trace_object->close()". For an
2343 example, see below and the test_c/sim_main.cpp file of the
2344 distribution.
2345 You also need to compile verilated_vcd_c.cpp and add it to your
2347 link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to
2348 your Makefile's link rule. This is done for you if using the
2349 Verilator --exe flag.
2350 Note you can also call ->trace on multiple Verilated objects with
2352 the same trace file if you want all data to land in the same output
2353 file.
2354 Note also older versions of Verilator used the SystemPerl package
2356 and SpTraceVcdC class. This still works, but is depreciated as it
2357 requires strong coupling between the Verilator and SystemPerl
2358 versions.
2359 #include "verilated_vcd_c.h"
2361 ...
2362 int main(int argc, char **argv, char **env) {
2363 ...
2364 Verilated::traceEverOn(true);
2365 VerilatedVcdC* tfp = new VerilatedVcdC;
2366 topp->trace (tfp, 99);
2367 tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
2368 ...
2369 while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
2370 main_time += #;
2371 tfp->dump (main_time);
2372 }
2373 tfp->close();
2374 }
2375 How do I generate waveforms (traces) in SystemC?
2377 Add the --trace switch to Verilator, and in your top level C
2378 sc_main code, include verilated_vcd_sc.h. Then call
2379 Verilated::traceEverOn(true). Then create a VerilatedVcdSc object
2380 as you would create a normal SystemC trace file. For an example,
2381 see the call to VerilatedVcdSc in the test_sp/sc_main.cpp file of
2382 the distribution, and below.
2383 Alternatively you may use the C++ trace mechanism described in the
2385 previous question, however the timescale and timeprecision will not
2386 inherited from your SystemC settings.
2387 You also need to compile verilated_vcd_sc.cpp and
2389 verilated_vcd_c.cpp and add them to your link, preferably by adding
2390 the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule.
2391 This is done for you if using the Verilator --exe flag.
2392 Note you can also call ->trace on multiple Verilated objects with
2394 the same trace file if you want all data to land in the same output
2395 file.
2396 #include "verilated_vcd_sc.h"
2398 ...
2399 int main(int argc, char **argv, char **env) {
2400 ...
2401 Verilated::traceEverOn(true);
2402 VerilatedVcdSc* tfp = new VerilatedVcdSc;
2403 topp->trace (tfp, 99);
2404 tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
2405 ...
2406 sc_start(1);
2407 ...
2408 tfp->close();
2409 }
2410 How do I view waveforms (traces)?
2412 Verilator makes standard VCD (Value Change Dump) files. They are
2413 viewable with the public domain Dinotrace or GtkWave programs, or
2414 any of the many commercial offerings.
2415 How do I reduce the size of large waveform (trace) files?
2417 First, instead of calling VerilatedVcdC->open at the beginning of
2418 time, delay calling it until the time stamp where you want to
2419 tracing to begin. Likewise you can also call VerilatedVcdC->open
2420 before the end of time (perhaps a short period after you detect a
2421 verification error.)
2422 Next, add /*verilator tracing_off*/ to any very low level modules
2424 you never want to trace (such as perhaps library cells). Finally,
2425 use the --trace-depth option to limit the depth of tracing, for
2426 example --trace-depth 1 to see only the top level signals.
2427 Also be sure you write your trace files to a local disk, instead of
2429 to a network disk. Network disks are generally far slower.
2430 How do I do coverage analysis?
2432 Verilator supports both block (line) coverage and user inserted
2433 functional coverage. Both currently require SystemPerl output mode
2434 and the SystemPerl package.
2435 First, run verilator with the --coverage option. If you're using
2437 your own makefile, compile the model with the GCC flag
2438 -DSP_COVERAGE_ENABLE (if using Verilator's, it will do this for
2439 you.)
2440 Run your tests in different directories. Each test will create a
2442 logs/coverage.pl file.
2443 After running all of your tests, the vcoverage utility (from the
2445 SystemPerl package) is executed. Vcoverage reads the
2446 logs/coverage.pl file(s), and creates an annotated source code
2447 listing showing code coverage details.
2448 For an example, after running 'make test' in the Verilator
2450 distribution, see the test_sp/logs/coverage_source directory. Grep
2451 for lines starting with '%' to see what lines Verilator believes
2452 need more coverage.
2453 Where is the translate_off command? (How do I ignore a construct?)
2455 Translate on/off pragmas are generally a bad idea, as it's easy to
2456 have mismatched pairs, and you can't see what another tool sees by
2457 just preprocessing the code. Instead, use the preprocessor;
2458 Verilator defines the "VERILATOR" define for you, so just wrap the
2459 code in a ifndef region:
2460 `ifndef VERILATOR
2462 Something_Verilator_Dislikes;
2463 `endif
2464 Why do I get "unexpected `do'" or "unexpected `bit'" errors?
2466 Do, bit, ref, return, and other words are now SystemVerilog
2467 keywords. You should change your code to not use them to insure it
2468 works with newer tools. Alternatively, surround them by the
2469 Verilog 2005/SystemVerilog begin_keywords pragma to indicate
2470 Verilog 2001 code.
2471 `begin_keywords "1364-2001"
2473 integer bit; initial bit = 1;
2474 `end_keywords
2475 If you want the whole file to be parsed as Verilog 2001, just
2477 create a file with
2478 `begin_keywords "1364-2001"
2480 and add it before other Verilog files on the command line. (Note
2482 this will also change the default for --prefix, so if you're not
2483 using --prefix, you will now need to.)
2484 How do I prevent my assertions from firing during reset?
2486 Call Verilated::assertOn(false) before you first call the model,
2487 then turn it back on after reset. It defaults to true. When
2488 false, all assertions controlled by --assert are disabled.
2489 Why do I get "undefined reference to `sc_time_stamp()'"?
2491 In C++ (non SystemC) code you need to define this function so that
2492 the simulator knows the current time. See the "CONNECTING TO C++"
2493 examples.
2494 Why do I get "undefined reference to `VL_RAND_RESET_I' or
2496 `Verilated::...'"?
2497 You need to link your compiled Verilated code against the
2498 verilated.cpp file found in the include directory of the Verilator
2499 kit. This is one target in the $(VK_GLOBAL_OBJS) make variable,
2500 which should be part of your Makefile's link rule.
2501 Is the PLI supported?
2503 No, but the DPI is.
2504 More specifically, the common PLI-ish calls $display, $finish,
2506 $stop, $time, $write are converted to C++ equivalents. You can
2507 also use the "import DPI" SystemVerilog feature to call C code (see
2508 the chapter above). If you want something more complex, since
2509 Verilator emits standard C++ code, you can simply write your own
2510 C++ routines that can access and modify signal values without
2511 needing any PLI interface code, and call it with
2512 $c("{any_c++_statement}").
2513 How do I make a Verilog module that contain a C++ object?
2515 You need to add the object to the structure that Verilator creates,
2516 then use $c to call a method inside your object. The
2517 test_regress/t/t_extend_class files show an example of how to do
2518 this.
2519 How do I get faster build times?
2521 Between GCC 3.0 to 3.3, each compiled progressively slower, thus if
2522 you can use GCC 2.95, or GCC 3.4 you'll have faster builds. Two
2523 ways to cheat are to compile on parallel machines and avoid
2524 compilations altogether. See the --output-split option, and the
2525 web for the ccache, distcc and icecream packages, and the
2526 Make::Cache package available from <http://www.veripool.org/>.
2527 Make::Cache will skip GCC runs between identical source builds,
2528 even across different users. You can use the OBJCACHE environment
2529 variable to use these CC wrappers.
2530 Why do so many files need to recompile when I add a signal?
2532 Adding a new signal requires the symbol table to be recompiled.
2533 Verilator uses one large symbol table, as that results in 2-3 less
2534 assembly instructions for each signal access. This makes the
2535 execution time 10-15% faster, but can result in more compilations
2536 when something changes.
2537 How do I access functions/tasks in C?
2539 Use the SystemVerilog Direct Programming Interface. You write a
2540 Verilog function or task with input/outputs that match what you
2541 want to call in with C. Then mark that function as an external
2542 function. See the DPI chapter in the manual.
2543 How do I access signals in C?
2545 The best thing is to make a SystemVerilog "export DPI task" or
2546 function that accesses that signal, as described in the DPI chapter
2547 in the manual and DPI tutorials on the web. This will allow
2548 Verilator to better optimize the model and should be portable
2549 across simulators.
2550 If you really want raw access to the signals, declare the signals
2552 you will be accessing with a /*verilator public*/ comment before
2553 the closing semicolon. Then scope into the C++ class to read the
2554 value of the signal, as you would any other member variable.
2555 Signals are the smallest of 8 bit chars, 16 bit shorts, 32 bit
2557 longs, or 64 bit long longs that fits the width of the signal.
2558 Generally, you can use just uint32_t's for 1 to 32 bits, or
2559 uint64_t for 1 to 64 bits, and the compiler will properly up-
2560 convert smaller entities.
2561 Signals wider than 64 bits are stored as an array of 32-bit
2563 uint32_t's. Thus to read bits 31:0, access signal[0], and for bits
2564 63:32, access signal[1]. Unused bits (for example bit numbers
2565 65-96 of a 65 bit vector) will always be zero. if you change the
2566 value you must make sure to pack zeros in the unused bits or core-
2567 dumps may result. (Because Verilator strips array bound checks
2568 where it believes them to be unnecessary.)
2569 In the SYSTEMC example above, if you had in our.v:
2571 input clk /*verilator public*/;
2573 // Note the placement of the semicolon above
2574 From the sc_main.cpp file, you'd then:
2576 #include "Vour.h"
2578 #include "Vour_our.h"
2579 cout << "clock is " << top->v->clk << endl;
2580 In this example, clk is a bool you can read or set as any other
2582 variable. The value of normal signals may be set, though clocks
2583 shouldn't be changed by your code or you'll get strange results.
2584 Should a module be in Verilog or SystemC?
2586 Sometimes there is a block that just interconnects cells, and have
2587 a choice as to if you write it in Verilog or SystemC. Everything
2588 else being equal, best performance is when Verilator sees all of
2589 the design. So, look at the hierarchy of your design, labeling
2590 cells as to if they are SystemC or Verilog. Then:
2591 A module with only SystemC cells below must be SystemC.
2593 A module with a mix of Verilog and SystemC cells below must be
2595 SystemC. (As Verilator cannot connect to lower-level SystemC
2596 cells.)
2597 A module with only Verilog cells below can be either, but for best
2599 performance should be Verilog. (The exception is if you have a
2600 design that is instantiated many times; in this case Verilating one
2601 of the lower modules and instantiating that Verilated cells
2602 multiple times into a SystemC module *may* be faster.)
2603
2605 First, check the the coding limitations section.
2606 Next, try the --debug switch. This will enable additional internal
2608 assertions, and may help identify the problem.
2609 Finally, reduce your code to the smallest possible routine that
2611 exhibits the bug. Even better, create a test in the test_regress/t
2612 directory, as follows:
2613 cd test_regress
2615 cp -p t/t_EXAMPLE.pl t/t_BUG.pl
2616 cp -p t/t_EXAMPLE.v t/t_BUG.v
2617 Edit t/t_BUG.pl to suit your example; you can do anything you want in
2619 the Verilog code there; just make sure it retains the single clk input
2620 and no outputs. Now, the following should fail:
2621 cd test_regress
2623 t/t_BUG.pl
2624 Finally, report the bug using the bug tracker at
2626 <http://www.veripool.org/verilator>. The bug will become publicly
2627 visible; if this is unacceptable, mail the bug report to
2628 "wsnyder@wsnyder.org".
2629
2631 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group
2632 at Digital Equipment Corporation. The Verilog code that was converted
2633 to C was then merged with a C based CPU model of the Alpha processor
2634 and simulated in a C based environment called CCLI.
2635 In 1995 Verilator started being used also for Multimedia and Network
2637 Processor development inside Digital. Duane Galbi took over active
2638 development of Verilator, and added several performance enhancements.
2639 CCLI was still being used as the shell.
2640 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
2642 Digital graciously agreed to release the source code. (Subject to the
2643 code not being resold, which is compatible with the GNU Public
2644 License.)
2645 In 2001, Wilson Snyder took the kit, and added a SystemC mode, and
2647 called it Verilator2. This was the first packaged public release.
2648 In 2002, Wilson Snyder created Verilator3 by rewriting Verilator from
2650 scratch in C++. This added many optimizations, yielding about a 2-5x
2651 performance gain.
2652 In 2009, major SystemVerilog and DPI language support was added.
2654 Currently, various language features and performance enhancements are
2656 added as the need arises. Verilator is now about 3x faster than in
2657 2002, and is faster than many popular commercial simulators.
2658
2660 Many people have provided ideas and other assistance with Verilator.
2661 The major corporate sponsors of Verilator, by providing significant
2663 contributions of time or funds include include Compaq Corporation,
2664 Digital Equipment Corporation, Intel Corporation, Mindspeed
2665 Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun
2666 Microsystems, Nauticus Networks, and SiCortex Inc.
2667 The people who have contributed major functionality are Byron Bradley,
2669 Lane Brooks, Duane Galbi, Paul Wasson, and Wilson Snyder. Major
2670 testers include Jeff Dutton, Ralf Karge, David Hewson, Wim Michiels,
2671 and Gene Weber.
2672 Some of the people who have provided ideas and feedback for Verilator
2674 include David Addison, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm,
2675 J Baxter, Jeremy Bennett, David Black, Gregg Bouchard, Christopher
2676 Boumenot, Byron Bradley, Bryan Brady, Lane Brooks, John Brownlee,
2677 Lawrence Butcher, Chris Candler, Lauren Carlson, Donal Casey, Robert A.
2678 Clark, Allan Cochrane, Gunter Dannoritzer, Bernard Deadman, John Deroo,
2679 John Dickol, Danny Ding, Alex Duller, Jeff Dutton, Robert Farrell,
2680 Eugen Fekete, Andrea Foletto, Bob Fredieu, Shankar Giri, Sam Gladstone,
2681 Chitlesh Goorah, Thomas Hawkins, David Hewson, Jae Hossell, Ben
2682 Jackson, Mike Kagen, Guy-Armand Kamendje, Vasu Kandadi, Patricio
2683 Kaplan, Ralf Karge, Dan Katz, Sol Katzman, Jonathan Kimmitt, Gernot
2684 Koch, Soon Koh, Steve Kolecki, Steve Lang, Stephane Laurent, Charlie
2685 Lind, Dan Lussier, Fred Ma, Duraid Madina, Mark Marshall, Wim Michiels,
2686 Dennis Muhlestein, John Murphy, Richard Myers, Dimitris Nalbantis, Paul
2687 Nitza, Pete Nixon, Lisa Noack, Mark Nodine, Andreas Olofsson, Niranjan
2688 Prabhu, Oleg Rodionov, John Sanguinetti, Mike Shinkarovsky, Rafael
2689 Shirakawa, Rodney Sinclair, Brian Small, Art Stamness, John Stroebel,
2690 Emerson Suguimoto, Renga Sundararajan, Stefan Thiede, Gary Thomas,
2691 Steve Tong, Holger Waechtler, Shawn Wang, Greg Waters, Eugene Weber,
2692 Leon Wildman, Gerald Williams, Jeff Winston, Johan Wouters, and Ding
2693 Xiaoliang.
2694 Thanks all.
2696
2698 The latest version is available from <http://www.veripool.org/>.
2699 Copyright 2003-2010 by Wilson Snyder. Verilator is free software; you
2701 can redistribute it and/or modify the Verilator internals under the
2702 terms of either the GNU Lesser General Public License Version 3 or the
2703 Perl Artistic License Version 2.0.
2704
2706 When possible, please instead report bugs to
2707 <http://www.veripool.org/>.
2708 Wilson Snyder <wsnyder@wsnyder.org>
2710 Major concepts by Paul Wasson and Duane Galbi.
2712
2714 verilator_profcfunc, systemperl, vcoverage, make
2715 And internals.txt in the distribution.
2717perl v5.10.0 2010-09-20 VERILATOR(1)