1VERILATOR(1) User Contributed Perl Documentation VERILATOR(1)
2
6 Verilator - Convert Verilog code to C++/SystemC
7
9 verilator --help
10 verilator --version
11 verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
12 verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
13 verilator --lint-only [source_files.v]...
14
16 Verilator converts synthesizable (not behavioral) Verilog code, plus
17 some Synthesis, SystemVerilog and a small subset of Verilog AMS
18 assertions, into C++ or SystemC code. It is not a complete simulator,
19 but a compiler.
20 Verilator is invoked with parameters similar to GCC, Cadence
22 Verilog-XL/NC-Verilog, or Synopsys's VCS. It reads the specified
23 Verilog code, lints it, and optionally adds coverage and waveform
24 tracing code. For C++ and SystemC formats, it outputs .cpp and .h
25 files.
26 The files created by Verilator are then compiled with C++. The user
28 writes a little C++ wrapper file, which instantiates the top level
29 module, and passes this filename on the command line. These C files
30 are compiled in C++, and linked with the Verilated files.
31 The resulting executable will perform the actual simulation.
33 To get started, jump down to "EXAMPLE C++ EXECUTION".
35
37 This is a short summary of the arguments to Verilator. See the
38 detailed descriptions in the next sections for more information.
39 {file.v} Verilog package, module and top module filenames
41 {file.c/cc/cpp} Optional C++ files to compile in
42 {file.a/o/so} Optional C++ files to link in
43 +1364-1995ext+<ext> Use Verilog 1995 with file extension <ext>
45 +1364-2001ext+<ext> Use Verilog 2001 with file extension <ext>
46 +1364-2005ext+<ext> Use Verilog 2005 with file extension <ext>
47 +1800-2005ext+<ext> Use SystemVerilog 2005 with file extension <ext>
48 +1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
49 +1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
50 +1800-2017ext+<ext> Use SystemVerilog 2017 with file extension <ext>
51 --assert Enable all assertions
52 --autoflush Flush streams after all $displays
53 --bbox-sys Blackbox unknown $system calls
54 --bbox-unsup Blackbox unsupported language features
55 --bin <filename> Override Verilator binary
56 -CFLAGS <flags> C++ Compiler flags for makefile
57 --cc Create C++ output
58 --cdc Clock domain crossing analysis
59 --clk <signal-name> Mark specified signal as clock
60 --compiler <compiler-name> Tune for specified C++ compiler
61 --converge-limit <loops> Tune convergence settle time
62 --coverage Enable all coverage
63 --coverage-line Enable line coverage
64 --coverage-toggle Enable toggle coverage
65 --coverage-user Enable SVL user coverage
66 --coverage-underscore Enable coverage of _signals
67 -D<var>[=<value>] Set preprocessor define
68 --debug Enable debugging
69 --debug-check Enable debugging assertions
70 --no-debug-leak Disable leaking memory in --debug mode
71 --debugi <level> Enable debugging at a specified level
72 --debugi-<srcfile> <level> Enable debugging a source file at a level
73 --default-language <lang> Default language to parse
74 +define+<var>=<value> Set preprocessor define
75 --dump-tree Enable dumping .tree files
76 --dump-treei <level> Enable dumping .tree files at a level
77 --dump-treei-<srcfile> <level> Enable dumping .tree file at a source file at a level
78 -E Preprocess, but do not compile
79 --error-limit <value> Abort after this number of errors
80 --exe Link to create executable
81 -F <file> Parse options from a file, relatively
82 -f <file> Parse options from a file
83 -FI <file> Force include of a file
84 -G<name>=<value> Overwrite toplevel parameter
85 --gdb Run Verilator under GDB interactively
86 --gdbbt Run Verilator under GDB for backtrace
87 --getenv <var> Get environment variable with defaults
88 --help Display this help
89 -I<dir> Directory to search for includes
90 --gate-stmts <value> Tune gate optimizer depth
91 --if-depth <value> Tune IFDEPTH warning
92 +incdir+<dir> Directory to search for includes
93 --inhibit-sim Create function to turn off sim
94 --inline-mult <value> Tune module inlining
95 -LDFLAGS <flags> Linker pre-object flags for makefile
96 -LDLIBS <flags> Linker library flags for makefile
97 --l2-name <value> Verilog scope name of the top module
98 --language <lang> Default language standard to parse
99 +libext+<ext>+[ext]... Extensions for finding modules
100 --lint-only Lint, but do not make output
101 --MMD Create .d dependency files
102 --MP Create phony dependency targets
103 --Mdir <directory> Name of output object directory
104 --mod-prefix <topname> Name to prepend to lower classes
105 --no-clk <signal-name> Prevent marking specified signal as clock
106 --no-decoration Disable comments and symbol decorations
107 --no-pins64 Don't use vluint64_t's for 33-64 bit sigs
108 --no-skip-identical Disable skipping identical output
109 +notimingchecks Ignored
110 -O0 Disable optimizations
111 -O3 High performance optimizations
112 -O<optimization-letter> Selectable optimizations
113 -o <executable> Name of final executable
114 --no-order-clock-delay Disable ordering clock enable assignments
115 --output-split <bytes> Split .cpp files into pieces
116 --output-split-cfuncs <statements> Split .cpp functions
117 --output-split-ctrace <statements> Split tracing functions
118 -P Disable line numbers and blanks with -E
119 --pins-bv <bits> Specify types for top level ports
120 --pins-sc-uint Specify types for top level ports
121 --pins-sc-biguint Specify types for top level ports
122 --pins-uint8 Specify types for top level ports
123 --pipe-filter <command> Filter all input through a script
124 --prefix <topname> Name of top level class
125 --profile-cfuncs Name functions for profiling
126 --private Debugging; see docs
127 --public Debugging; see docs
128 -pvalue+<name>=<value> Overwrite toplevel parameter
129 --relative-includes Resolve includes relative to current file
130 --no-relative-cfuncs Disallow 'this->' in generated functions
131 --report-unoptflat Extra diagnostics for UNOPTFLAT
132 --savable Enable model save-restore
133 --sc Create SystemC output
134 --stats Create statistics file
135 --stats-vars Provide statistics on variables
136 -sv Enable SystemVerilog parsing
137 +systemverilogext+<ext> Synonym for +1800-2017ext+<ext>
138 --top-module <topname> Name of top level input module
139 --trace Enable waveform creation
140 --trace-depth <levels> Depth of tracing
141 --trace-max-array <depth> Maximum bit width for tracing
142 --trace-max-width <width> Maximum array depth for tracing
143 --trace-params Enable tracing parameters
144 --trace-structs Enable tracing structure names
145 --trace-underscore Enable tracing of _signals
146 -U<var> Undefine preprocessor define
147 --unroll-count <loops> Tune maximum loop iterations
148 --unroll-stmts <stmts> Tune maximum loop body size
149 --unused-regexp <regexp> Tune UNUSED lint signals
150 -V Verbose version and config
151 -v <filename> Verilog library
152 +verilog1995ext+<ext> Synonym for +1364-1995ext+<ext>
153 +verilog2001ext+<ext> Synonym for +1364-2001ext+<ext>
154 --vpi Enable VPI compiles
155 -Wall Enable all style warnings
156 -Werror-<message> Convert warnings to errors
157 -Wfuture-<message> Disable unknown message warnings
158 -Wno-<message> Disable warning
159 -Wno-lint Disable all lint warnings
160 -Wno-style Disable all style warnings
161 -Wno-fatal Disable fatal exit on warnings
162 --x-assign <mode> Assign non-initial Xs to this value
163 --x-initial <mode> Assign initial Xs to this value
164 --x-initial-edge Enable initial X->0 and X->1 edge triggers
165 -y <dir> Directory to search for modules
166
168 {file.v}
169 Specifies the Verilog file containing the top module to be
170 Verilated.
171 {file.c/.cc/.cpp/.cxx}
173 Specifies optional C++ files to be linked in with the Verilog code.
174 If any C++ files are specified in this way, Verilator will include
175 a make rule that generates a module executable. Without any C++
176 files, Verilator will stop at the module__ALL.a library, and
177 presume you'll continue linking with make rules you write yourself.
178 See also the -CFLAGS option.
179 {file.a/.o/.so}
181 Specifies optional object or library files to be linked in with the
182 Verilog code, as a shorthand for -LDFLAGS "<file>". If any files
183 are specified in this way, Verilator will include a make rule that
184 uses these files when linking the module executable. This
185 generally is only useful when used with the --exe option.
186 +1364-1995ext+ext
188 +1364-2001ext+ext
189 +1364-2005ext+ext
190 +1800-2005ext+ext
191 +1800-2009ext+ext
192 +1800-2012ext+ext
193 +1800-2017ext+ext
194 Specifies the language standard to be used with a specific filename
195 extension, ext.
196 For compatibility with other simulators, see also the synonyms
198 "+verilog1995ext+"ext, "+verilog2001ext+"ext, and
199 "+systemverilogext+"ext.
200 For any source file, the language specified by these options takes
202 precedence over any language specified by the "--default-language"
203 or "--language" options.
204 These options take effect in the order they are encountered. Thus
206 the following would use Verilog 1995 for "a.v" and Verilog 2001 for
207 "b.v".
208 verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v
210 These flags are only recommended for legacy mixed language designs,
212 as the preferable option is to edit the code to repair new
213 keywords, or add appropriate "`begin_keywords".
214 Note "`begin_keywords" is a SystemVerilog construct, which
216 specifies only which the set of keywords is to be recognized.
217 Whatever set is chosen, the semantics will be those of
218 SystemVerilog. By contrast "+1364-1995ext+" etc. specify both the
219 syntax and semantics to be used.
220 --assert
222 Enable all assertions.
223 --autoflush
225 After every $display or $fdisplay, flush the output stream. This
226 ensures that messages will appear immediately but may reduce
227 performance; for best performance call "fflush(stdout)"
228 occasionally in the main C loop. Defaults off, which will buffer
229 output as provided by the normal C stdio calls.
230 --bbox-sys
232 Black box any unknown $system task or function calls. System tasks
233 will be simply NOPed, and system functions will be replaced by
234 unsized zero. Arguments to such functions will be parsed, but not
235 otherwise checked. This prevents errors when linting in the
236 presence of company specific PLI calls.
237 --bbox-unsup
239 Black box some unsupported language features, currently UDP tables,
240 the cmos and tran gate primitives, deassign statements, and mixed
241 edge errors. This may enable linting the rest of the design even
242 when unsupported constructs are present.
243 --bin filename
245 Rarely needed. Override the default filename for Verilator itself.
246 When a dependency (.d) file is created, this filename will become a
247 source dependency, such that a change in this binary will have make
248 rebuild the output files.
249 -CFLAGS flags
251 Add specified C compiler flags to the generated makefiles. When
252 make is run on the generated makefile these will be passed to the
253 C++ compiler (gcc/g++/msvc++).
254 --cc
256 Specifies C++ without SystemC output mode; see also --sc.
257 --cdc
259 Experimental. Perform some clock domain crossing checks and issue
260 related warnings (CDCRSTLOGIC) and then exit; if warnings other
261 than CDC warnings are needed make a second run with --lint-only.
262 Additional warning information is also written to the file
263 {prefix}__cdc.txt.
264 Currently only checks some items that other CDC tools missed; if
266 you have interest in adding more traditional CDC checks, please
267 contact the authors.
268 --clk signal-name
270 Sometimes it is quite difficult for Verilator to distinguish clock
271 signals from other data signals. Occasionally the clock signals can
272 end up in the checking list of signals which determines if further
273 evaluation is needed. This will heavily degrade the performance of
274 a Verilated model.
275 With --clk <signal-name>, user can specified root clock into the
277 model, then Verilator will mark the signal as clocker and propagate
278 the clocker attribute automatically to other signals derived from
279 that. In this way, Verilator will try to avoid taking the clocker
280 signal into checking list.
281 Note signal-name is specified by the RTL hierarchy path. For
283 example, v.foo.bar. If the signal is the input to top-module, the
284 directly the signal name. If you find it difficult to find the
285 exact name, try to use "/*verilator clocker*/" in RTL file to mark
286 the signal directly.
287 If clock signals are assigned to vectors and then later used
289 individually, Verilator will attempt to decompose the vector and
290 connect the single-bit clock signals directly. This should be
291 transparent to the user.
292 --compiler compiler-name
294 Enables tunings and workarounds for the specified C++ compiler.
295 clang
297 Tune for clang. This may reduce execution speed as it enables
298 several workarounds to avoid silly hardcoded limits in clang.
299 This includes breaking deep structures as for msvc as described
300 below.
301 gcc Tune for GNU C++, although generated code should work on almost
303 any compliant C++ compiler. Currently the default.
304 msvc
306 Tune for Microsoft Visual C++. This may reduce execution speed
307 as it enables several workarounds to avoid silly hardcoded
308 limits in MSVC++. This includes breaking deeply nested
309 parenthesized expressions into sub-expressions to avoid error
310 C1009, and breaking deep blocks into functions to avoid error
311 C1061.
312 --converge-limit <loops>
314 Rarely needed. Specifies the maximum number of runtime iterations
315 before creating a model failed to converge error. Defaults to 100.
316 --coverage
318 Enables all forms of coverage, alias for "--coverage-line
319 --coverage-toggle --coverage-user".
320 --coverage-line
322 Specifies basic block line coverage analysis code should be
323 inserted.
324 Coverage analysis adds statements at each code flow change point,
326 which are the branches of IF and CASE statements, a super-set of
327 normal Verilog Line Coverage. At each such branch a unique counter
328 is incremented. At the end of a test, the counters along with the
329 filename and line number corresponding to each counter are written
330 into logs/coverage.dat.
331 Verilator automatically disables coverage of branches that have a
333 $stop in them, as it is assumed $stop branches contain an error
334 check that should not occur. A /*verilator coverage_block_off*/
335 comment will perform a similar function on any code in that block
336 or below, or /*verilator coverage_on/coverage_off*/ will disable
337 coverage around lines of code.
338 Note Verilator may over-count combinatorial (non-clocked) blocks
340 when those blocks receive signals which have had the UNOPTFLAT
341 warning disabled; for most accurate results do not disable this
342 warning when using coverage.
343 --coverage-toggle
345 Specifies signal toggle coverage analysis code should be inserted.
346 Every bit of every signal in a module has a counter inserted. The
348 counter will increment on every edge change of the corresponding
349 bit.
350 Signals that are part of tasks or begin/end blocks are considered
352 local variables and are not covered. Signals that begin with
353 underscores, are integers, or are very wide (>256 bits total
354 storage across all dimensions) are also not covered.
355 Hierarchy is compressed, such that if a module is instantiated
357 multiple times, coverage will be summed for that bit across ALL
358 instantiations of that module with the same parameter set. A
359 module instantiated with different parameter values is considered a
360 different module, and will get counted separately.
361 Verilator makes a minimally-intelligent decision about what clock
363 domain the signal goes to, and only looks for edges in that clock
364 domain. This means that edges may be ignored if it is known that
365 the edge could never be seen by the receiving logic. This
366 algorithm may improve in the future. The net result is coverage
367 may be lower than what would be seen by looking at traces, but the
368 coverage is a more accurate representation of the quality of
369 stimulus into the design.
370 There may be edges counted near time zero while the model
372 stabilizes. It's a good practice to zero all coverage just before
373 releasing reset to prevent counting such behavior.
374 A /*verilator coverage_off/on */ comment pair can be used around
376 signals that do not need toggle analysis, such as RAMs and register
377 files.
378 --coverage-underscore
380 Enable coverage of signals that start with an underscore. Normally,
381 these signals are not covered. See also --trace-underscore.
382 --coverage-user
384 Enables user inserted functional coverage. Currently, all
385 functional coverage points are specified using SVA which must be
386 separately enabled with --assert.
387 For example, the following statement will add a coverage point,
389 with the comment "DefaultClock":
390 DefaultClock: cover property (@(posedge clk) cyc==3);
392 -Dvar=value
394 Defines the given preprocessor symbol, without allowing. Similar
395 to +define; +define is fairly standard across Verilog tools while
396 -D is an alias for GCC compatibility.
397 --debug
399 Select the debug built image of Verilator (if available), and
400 enable more internal assertions (equivalent to "--debug-check"),
401 debugging messages (equivalent to "--debugi 4"), and intermediate
402 form dump files (equivalent to "--dump-treei 3").
403 --debug-check
405 Rarely needed. Enable internal debugging assertion checks, without
406 changing debug verbosity. Enabled automatically when --debug
407 specified.
408 --no-debug-leak
410 In --debug mode, by default Verilator intentionally leaks AstNode's
411 instead of freeing them, so that each node pointer is unique in the
412 resulting tree files and dot files.
413 This option disables the leak. This may avoid out-of-memory errors
415 when Verilating large models in --debug mode.
416 Outside of --debug mode, AstNode's should never be leaked and this
418 option has no effect.
419 --debugi <level>
421 --debugi-<srcfile> <level>
422 Rarely needed - for developer use. Set internal debugging level
423 globally to the specified debug level (1-10) or set the specified
424 Verilator source file to the specified level (e.g.
425 "--debugi-V3Width 9"). Higher levels produce more detailed
426 messages.
427 --default-language value
429 Select the language to be used by default when first processing
430 each Verilog file. The language value must be "1364-1995",
431 "1364-2001", "1364-2005", "1800-2005", "1800-2009", "1800-2012" or
432 "1800-2017".
433 Any language associated with a particular file extension (see the
435 various +langext+ options) will be used in preference to the
436 language specified by --default-language.
437 The --default-language flag is only recommended for legacy code
439 using the same language in all source files, as the preferable
440 option is to edit the code to repair new keywords, or add
441 appropriate "`begin_keywords". For legacy mixed language designs,
442 the various +langext+ options should be used.
443 If no language is specified, either by this flag or +langext+
445 options, then the latest SystemVerilog language (IEEE 1800-2017) is
446 used.
447 +define+var=value
449 +define+var=value+var2=value2...
450 Defines the given preprocessor symbol, or multiple symbols if
451 separated by plusses. Similar to -D; +define is fairly standard
452 across Verilog tools while -D is an alias for GCC compatibility.
453 --dump-tree
455 Rarely needed. Enable writing .tree debug files with dumping level
456 3, which dumps the standard critical stages. For details on the
457 format see the Verilator Internals manual. --dump-tree is enabled
458 automatically with --debug, so "--debug --no-dump-tree" may be
459 useful if the dump files are large and not desired.
460 --dump-treei <level>
462 --dump-treei-<srcfile> <level>
463 Rarely needed - for developer use. Set internal tree dumping level
464 globally to a specific dumping level or set the specified Verilator
465 source file to the specified tree dumping level (e.g.
466 "--dump-treei-V3Order 9"). Level 0 disbles dumps and is equivalent
467 to "--no-dump-tree". Level 9 enables dumping of every stage.
468 -E Preprocess the source code, but do not compile, as with 'gcc -E'.
470 Output is written to standard out. Beware of enabling debugging
471 messages, as they will also go to standard out.
472 --error-limit <value>
474 After this number of errors or warnings are encountered, exit.
475 Defaults to 50.
476 --exe
478 Generate an executable. You will also need to pass additional .cpp
479 files on the command line that implement the main loop for your
480 simulation.
481 -F file
483 Read the specified file, and act as if all text inside it was
484 specified as command line parameters. Any relative paths are
485 relative to the directory containing the specified file. See also
486 -f. Note -F is fairly standard across Verilog tools.
487 -f file
489 Read the specified file, and act as if all text inside it was
490 specified as command line parameters. Any relative paths are
491 relative to the current directory. See also -F. Note -f is fairly
492 standard across Verilog tools.
493 The file may contain // comments which are ignored to the end of
495 the line. Any $VAR, $(VAR), or ${VAR} will be replaced with the
496 specified environment variable.
497 -FI <file>
499 Force include of the specified C++ header file. All generated C++
500 files will insert a #include of the specified file before any other
501 includes. The specified file might be used to contain define
502 prototypes of custom VL_VPRINTF functions, and may need to include
503 verilatedos.h as this file is included before any other standard
504 includes.
505 -Gname=value
507 Overwrites the given parameter of the toplevel module. The value is
508 limited to basic data literals:
509 Verilog integer literals
511 The standard verilog integer literals are supported, so values
512 like 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that
513 the single quote (I') is properly escaped in an interactive
514 shell, e.g., as -GWIDTH=8\'hx.
515 C integer literals
517 It is also possible to use C integer notation, including
518 hexadecimal (0x..), octal (0..) or binary (0b..) notation.
519 Double literals
521 Double literals must contain a dot (.) and/or an exponent (e).
522 Strings
524 String must in double quotes ("). On the command line it is
525 required to escape them properly, e.g. as -GSTR="\"My String\""
526 or -GSTR='"My String"'.
527 --gate-stmts value
529 Rarely needed. Set the maximum number of statements that may be
530 present in an equation for the gate substitution optimization to
531 inline that equation.
532 --gdb
534 Run Verilator underneath an interactive GDB (or VERILATOR_GDB
535 environment variable value) session. See also --gdbbt.
536 --gdbbt
538 If --debug is specified, run Verilator underneath a GDB process and
539 print a backtrace on exit, then exit GDB immediately. Without
540 --debug or if GDB doesn't seem to work, this flag is ignored.
541 Intended for easy creation of backtraces by users; otherwise see
542 the --gdb flag.
543 --getenv variable
545 If the variable is declared in the environment, print it and exit
546 immediately. Otherwise, if it's built into Verilator (e.g.
547 VERILATOR_ROOT), print that and exit immediately. Otherwise, print
548 a newline and exit immediately. This can be useful in makefiles.
549 See also -V, and the various *.mk files.
550 --help
552 Displays this message and program version and exits.
553 -Idir
555 See -y.
556 --if-depth value
558 Rarely needed. Set the depth at which the IFDEPTH warning will
559 fire, defaults to 0 which disables this warning.
560 +incdir+dir
562 See -y.
563 --inhibit-sim
565 Rarely needed. Create a "inhibitSim(bool)" function to enable and
566 disable evaluation. This allows an upper level testbench to
567 disable modules that are not important in a given simulation,
568 without needing to recompile or change the SystemC modules
569 instantiated.
570 --inline-mult value
572 Tune the inlining of modules. The default value of 2000 specifies
573 that up to 2000 new operations may be added to the model by
574 inlining, if more than this number of operations would result, the
575 module is not inlined. Larger values, or a value <= 1 will inline
576 everything, will lead to longer compile times, but potentially
577 faster runtimes. This setting is ignored for very small modules;
578 they will always be inlined, if allowed.
579 -LDFLAGS flags
581 Add specified C linker flags to the generated makefiles. When make
582 is run on the generated makefile these will be passed to the C++
583 linker (ld) *after* the primary file being linked. This flag is
584 called -LDFLAGS as that's the traditional name in simulators; it's
585 would have been better called LDLIBS as that's the Makefile
586 variable it controls. (In Make, LDFLAGS is before the first
587 object, LDLIBS after. -L libraries need to be in the Make variable
588 LDLIBS, not LDFLAGS.)
589 --l2-name value
591 Instead of using the module name when showing Verilog scope, use
592 the name provided. This allows simplifying some Verilator-embedded
593 modeling methodologies. Default is an l2-name matching the top
594 module. The default before 3.884 was "--l2-name v"
595 For example, the program "module t; initial $display("%m");
597 endmodule" will show by default "t". With "--l2-name v" it will
598 print "v".
599 --language value
601 A synonym for "--default-language", for compatibility with other
602 tools and earlier versions of Verilator.
603 +libext+ext+ext...
605 Specify the extensions that should be used for finding modules. If
606 for example module x is referenced, look in x.ext. Note +libext+
607 is fairly standard across Verilog tools. Defaults to .v and .sv.
608 --lint-only
610 Check the files for lint violations only, do not create any other
611 output.
612 You may also want the -Wall option to enable messages that are
614 considered stylistic and not enabled by default.
615 If the design is not to be completely Verilated see also the
617 --bbox-sys and --bbox-unsup options.
618 --MMD
620 Enable creation of .d dependency files, used for make dependency
621 detection, similar to gcc -MMD option. On by default, use --no-MMD
622 to disable.
623 --MP
625 When creating .d dependency files with --MMD, make phony targets.
626 Similar to gcc -MP option.
627 --Mdir directory
629 Specifies the name of the Make object directory. All generated
630 files will be placed in this directory. If not specified,
631 "obj_dir" is used. The directory is created if it does not exist
632 and the parent directories exist; otherwise manually create the
633 Mdir before calling Verilator.
634 --mod-prefix topname
636 Specifies the name to prepend to all lower level classes. Defaults
637 to the same as --prefix.
638 --no-clk <signal-name>
640 Prevent the specified signal from being marked as clock. See
641 "--clk".
642 --no-decoration
644 When creating output Verilated code, minimize comments, whitespace,
645 symbol names and other decorative items, at the cost of greatly
646 reduced readability. This may assist C++ compile times. This will
647 not typically change the ultimate model's performance, but may in
648 some cases.
649 --no-pins64
651 Backward compatible alias for "--pins-bv 33".
652 --no-relative-cfuncs
654 Disable 'this->' references in generated functions, and instead
655 Verilator will generate absolute references starting from
656 'vlTOPp->'. This prevents V3Combine from merging functions from
657 multiple instances of the same module, so it can grow the
658 instruction stream.
659 This is a work around for old compilers. Don't set this if your C++
661 compiler supports __restrict__ properly, as GCC 4.5.x and newer do.
662 For older compilers, test if this switch gives you better
663 performance or not.
664 Compilers which don't honor __restrict__ will suspect that 'this->'
666 references and 'vlTOPp->' references may alias, and may write slow
667 code with extra loads and stores to handle the (imaginary)
668 aliasing. Using only 'vlTOPp->' references allows these old
669 compilers to produce tight code.
670 --no-skip-identical
672 Rarely needed. Disables skipping execution of Verilator if all
673 source files are identical, and all output files exist with newer
674 dates.
675 +notimingchecks
677 Ignored for compatibility with other simulators.
678 -O0 Disables optimization of the model.
680 -O3 Enables slow optimizations for the code Verilator itself generates
682 (as opposed to "-CFLAGS -O3" which effects the C compiler's
683 optimization. -O3 may reduce simulation runtimes at the cost of
684 compile time. This currently sets --inline-mult -1.
685 -Ooptimization-letter
687 Rarely needed. Enables or disables a specific optimizations, with
688 the optimization selected based on the letter passed. A lowercase
689 letter disables an optimization, an upper case letter enables it.
690 This is intended for debugging use only; see the source code for
691 version-dependent mappings of optimizations to -O letters.
692 -o <executable>
694 Specify the name for the final executable built if using --exe.
695 Defaults to the --prefix if not specified.
696 --no-order-clock-delay
698 Rarely needed. Disables a bug fix for ordering of clock enables
699 with delayed assignments. This flag should only be used when
700 suggested by the developers.
701 --output-split bytes
703 Enables splitting the output .cpp files into multiple outputs.
704 When a C++ file exceeds the specified number of operations, a new
705 file will be created at the next function boundary. In addition,
706 any slow routines will be placed into __Slow files. This
707 accelerates compilation by as optimization can be disabled on the
708 slow routines, and the remaining files can be compiled on parallel
709 machines. Using --output-split should have only a trivial impact
710 on performance. With GCC 3.3 on a 2GHz Opteron, --output-split
711 20000 will result in splitting into approximately one-minute-
712 compile chunks.
713 --output-split-cfuncs statements
715 Enables splitting functions in the output .cpp files into multiple
716 functions. When a generated function exceeds the specified number
717 of operations, a new function will be created. With
718 --output-split, this will enable GCC to compile faster, at a small
719 loss in performance that gets worse with decreasing split values.
720 Note that this option is stronger than --output-split in the sense
721 that --output-split will not split inside a function.
722 --output-split-ctrace statements
724 Enables splitting trace functions in the output .cpp files into
725 multiple functions. Defaults to same setting as
726 --output-split-cfuncs.
727 -P With -E, disable generation of `line markers and blank lines,
729 similar to GCC -P flag.
730 --pins64
732 Backward compatible alias for "--pins-bv 65". Note that's a 65,
733 not a 64.
734 --pins-bv width
736 Specifies SystemC inputs/outputs of greater than or equal to width
737 bits wide should use sc_bv's instead of uint32/vluint64_t's. The
738 default is "--pins-bv 65", and the value must be less than or equal
739 to 65. Versions before Verilator 3.671 defaulted to "--pins-bv
740 33". The more sc_bv is used, the worse for performance. Use the
741 "/*verilator sc_bv*/" attribute to select specific ports to be
742 sc_bv.
743 --pins-sc-uint
745 Specifies SystemC inputs/outputs of greater than 2 bits wide should
746 use sc_uint between 2 and 64. When combined with the
747 "--pins-sc-biguint" combination, it results in sc_uint being used
748 between 2 and 64 and sc_biguint being used between 65 and 512.
749 --pins-sc-biguint
751 Specifies SystemC inputs/outputs of greater than 65 bits wide
752 should use sc_biguint between 65 and 512, and sc_bv from 513
753 upwards. When combined with the "--pins-sc-uint" combination, it
754 results in sc_uint being used between 2 and 64 and sc_biguint being
755 used between 65 and 512.
756 --pins-uint8
758 Specifies SystemC inputs/outputs that are smaller than the
759 --pins-bv setting and 8 bits or less should use uint8_t instead of
760 uint32_t. Likewise pins of width 9-16 will use uint16_t instead of
761 uint32_t.
762 --pipe-filter command
764 Rarely needed and experimental. Verilator will spawn the specified
765 command as a subprocess pipe, to allow the command to perform
766 custom edits on the Verilog code before it reaches Verilator.
767 Before reading each Verilog file, Verilator will pass the file name
769 to the subprocess' stdin with 'read_verilog "<filename>"'. The
770 filter may then read the file and perform any filtering it desires,
771 and feeds the new file contents back to Verilator on stdout with
772 'Content-Length'. Output to stderr from the filter feeds through
773 to Verilator's stdout and if the filter exits with non-zero status
774 Verilator terminates. See the t/t_pipe_filter test for an example.
775 To debug the output of the filter, try using the -E option to see
777 preprocessed output.
778 --prefix topname
780 Specifies the name of the top level class and makefile. Defaults
781 to V prepended to the name of the --top-module switch, or V
782 prepended to the first Verilog filename passed on the command line.
783 --profile-cfuncs
785 Modify the created C++ functions to support profiling. The
786 functions will be minimized to contain one "basic" statement,
787 generally a single always block or wire statement. (Note this will
788 slow down the executable by ~5%.) Furthermore, the function name
789 will be suffixed with the basename of the Verilog module and line
790 number the statement came from. This allows gprof or oprofile
791 reports to be correlated with the original Verilog source
792 statements.
793 --private
795 Opposite of --public. Is the default; this option exists for
796 backwards compatibility.
797 --public
799 This is only for historical debug use. Using it may result in mis-
800 simulation of generated clocks.
801 Declares all signals and modules public. This will turn off signal
803 optimizations as if all signals had a /*verilator public*/ comments
804 and inlining. This will also turn off inlining as if all modules
805 had a /*verilator public_module*/, unless the module specifically
806 enabled it with /*verilator inline_module*/.
807 -pvalue+name=value
809 Overwrites the given parameter(s) of the toplevel module. See -G
810 for a detailed description.
811 --relative-includes
813 When a file references an include file, resolve the filename
814 relative to the path of the referencing file, instead of relative
815 to the current directory.
816 --report-unoptflat
818 Extra diagnostics for UNOPTFLAT warnings. This includes for each
819 loop, the 10 widest variables in the loop, and the 10 most fanned
820 out variables in the loop. These are candidates for splitting into
821 multiple variables to break the loop.
822 In addition produces a GraphViz DOT file of the entire strongly
824 connected components within the source associated with each loop.
825 This is produced irrespective of whether --dump-tree is set. Such
826 graphs may help in analyzing the problem, but can be very large
827 indeed.
828 Various commands exist for viewing and manipulating DOT files. For
830 example the dot command can be used to convert a DOT file to a PDF
831 for printing. For example:
832 dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot
834 will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from
836 the DOT file.
837 --savable
839 Enable including save and restore functions in the generated model.
840 The user code must create a VerilatedSerialize or
842 VerilatedDeserialze object then calling the << or >> operators on
843 the generated model and any other data the process needs
844 saved/restored. For example:
845 void save_model(const char* filenamep) {
847 VerilatedSave os;
848 os.open(filenamep);
849 os << main_time; // user code must save the timestamp, etc
850 os << *topp;
851 }
852 void restore_model(const char* filenamep) {
853 VerilatedRestore os;
854 os.open(filenamep);
855 os >> main_time;
856 os >> *topp;
857 }
858 --sc
860 Specifies SystemC output mode; see also --cc.
861 --stats
863 Creates a dump file with statistics on the design in
864 {prefix}__stats.txt.
865 --stats-vars
867 Creates more detailed statistics, including a list of all the
868 variables by size (plain --stats just gives a count). See --stats,
869 which is implied by this.
870 -sv Specifies SystemVerilog language features should be enabled;
872 equivalent to "--language 1800-2005". This option is selected by
873 default, it exists for compatibility with other simulators.
874 +systemverilogext+ext
876 A synonym for "+1800-2017ext+"ext.
877 --top-module topname
879 When the input Verilog contains more than one top level module,
880 specifies the name of the top level Verilog module to become the
881 top, and sets the default for if --prefix is not used. This is not
882 needed with standard designs with only one top.
883 --trace
885 Adds waveform tracing code to the model. Verilator will generate
886 additional {prefix}__Trace*.cpp files that will need to be
887 compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) or
888 verilated_vcd_c.cpp (for both) must be compiled and linked in. If
889 using the Verilator generated Makefiles, these files will be added
890 as source targets for you. If you're not using the Verilator
891 makefiles, you will need to add these to your Makefile manually.
892 Having tracing compiled in may result in some small performance
894 losses, even when waveforms are not turned on during model
895 execution.
896 --trace-depth levels
898 Specify the number of levels deep to enable tracing, for example
899 --trace-level 1 to only see the top level's signals. Defaults to
900 the entire model. Using a small number will decrease visibility,
901 but greatly improve runtime and trace file size.
902 --trace-max-array depth
904 Rarely needed. Specify the maximum array depth of a signal that
905 may be traced. Defaults to 32, as tracing large arrays may greatly
906 slow traced simulations.
907 --trace-max-width width
909 Rarely needed. Specify the maximum bit width of a signal that may
910 be traced. Defaults to 256, as tracing large vectors may greatly
911 slow traced simulations.
912 --no-trace-params
914 Disable tracing of parameters.
915 --trace-structs
917 Enable tracing to show the name of packed structure, union, and
918 packed array fields, rather than a simgle combined packed bus. Due
919 to VCD file format constraints this may result in significantly
920 slower trace times and larger trace files.
921 --trace-underscore
923 Enable tracing of signals that start with an underscore. Normally,
924 these signals are not output during tracing. See also
925 --coverage-underscore.
926 -Uvar
928 Undefines the given preprocessor symbol.
929 --unroll-count loops
931 Rarely needed. Specifies the maximum number of loop iterations
932 that may be unrolled. See also BLKLOOPINIT warning.
933 --unroll-stmts statements
935 Rarely needed. Specifies the maximum number of statements in a
936 loop for that loop to be unrolled. See also BLKLOOPINIT warning.
937 --unused-regexp regexp
939 Rarely needed. Specifies a simple regexp with * and ? that if a
940 signal name matches will suppress the UNUSED warning. Defaults to
941 "*unused*". Setting it to "" disables matching.
942 -V Shows the verbose version, including configuration information
944 compiled into Verilator. (Similar to perl -V.) See also --getenv.
945 -v filename
947 Read the filename as a Verilog library. Any modules in the file
948 may be used to resolve cell instantiations in the top level module,
949 else ignored. Note -v is fairly standard across Verilog tools.
950 +verilog1995ext+ext
952 +verilog2001ext+ext
953 Synonyms for "+1364-1995ext+"ext and "+1364-2001ext+"ext
954 respectively
955 --vpi
957 Enable use of VPI and linking against the verilated_vpi.cpp files.
958 -Wall
960 Enable all code style warnings, including code style warnings that
961 are normally disabled by default. Equivelent to "-Wwarn-lint
962 -Wwarn-style". Excludes some specialty warnings, i.e.
963 IMPERFECTSCH.
964 -Werror-message
966 Convert the specified warning message into an error message. This
967 is generally to discourage users from violating important site-wide
968 rules, for example "-Werror-NOUNOPTFLAT".
969 -Wfuture-message
971 Rarely needed. Suppress unknown Verilator comments or warning
972 messages with the given message code. This is used to allow code
973 written with pragmas for a later version of Verilator to run under
974 a older version; add -Wfuture- arguments for each message code or
975 comment that the new version supports which the older version does
976 not support.
977 -Wno-message
979 Disable the specified warning message, or in some cases where noted
980 here disable an error. This will override any lint_on directives
981 in the source, i.e. the warning will still not be printed.
982 -Wno-lint
984 Disable all lint related warning messages, and all style warnings.
985 This is equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE
986 -Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEWITHX
987 -Wno-CMPCONST -Wno-COLONPLUS -Wno-ENDLABEL -Wno-IMPLICIT
988 -Wno-LITENDIAN -Wno-PINCONNECTEMPTY -Wno-PINMISSING
989 -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED
990 -Wno-WIDTH" plus the list shown for Wno-style.
991 It is strongly recommended you cleanup your code rather than using
993 this option, it is only intended to be use when running test-cases
994 of code received from third parties.
995 -Wno-style
997 Disable all code style related warning messages (note by default
998 they are already disabled). This is equivalent to
999 "-Wno-DECLFILENAME -Wno-DEFPARAM -Wno-INCABSPATH
1000 -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT -Wno-SYNCASYNCNET
1001 -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN".
1002 -Wno-fatal
1004 When warnings are detected, print them, but do not exit the
1005 simulator.
1006 Having warning messages in builds is sloppy. It is strongly
1008 recommended you cleanup your code, use inline lint_off, or use
1009 -Wno-... flags rather than using this option.
1010 -Wwarn-message
1012 Enables the specified warning message.
1013 -Wwarn-lint
1015 Enable all lint related warning messages (note by default they are
1016 already enabled), but do not affect style messages. This is
1017 equivalent to "-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE
1018 -Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX
1019 -Wwarn-CASEWITHX -Wwarn-CMPCONST -Wwarn-COLONPLUS -Wwarn-ENDLABEL
1020 -Wwarn-IMPLICIT -Wwarn-LITENDIAN -Wwarn-PINMISSING -Wwarn-REALCVT
1021 -Wwarn-UNSIGNED -Wwarn-WIDTH".
1022 -Wwarn-style
1024 Enable all code style related warning messages. This is equivalent
1025 to "-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM
1026 -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET
1027 -Wwarn-UNDRIVEN -Wwarn-UNUSED -Wwarn-VARHIDDEN".
1028 --x-assign 0
1030 --x-assign 1
1031 --x-assign fast (default)
1032 --x-assign unique
1033 Controls the two-state value that is replaced when an assignment to
1034 X is encountered. --x-assign=fast, the default, converts all Xs to
1035 whatever is best for performance. --x-assign=0 converts all Xs to
1036 0s, and is also fast. --x-assign=1 converts all Xs to 1s, this is
1037 nearly as fast as 0, but more likely to find reset bugs as active
1038 high logic will fire. --x-assign=unique will call a function to
1039 determine the value, this allows randomization of all Xs to find
1040 reset bugs and is the slowest, but safest for finding reset bugs in
1041 code.
1042 If using --x-assign unique, you may want to seed your random number
1044 generator such that each regression run gets a different
1045 randomization sequence. Use the system's srand48() or for Windows
1046 srand() function to do this. You'll probably also want to print
1047 any seeds selected, and code to enable rerunning with that same
1048 seed so you can reproduce bugs.
1049 Note. This option applies only to variables which are explicitly
1051 assigned to X in the Verilog source code. Initial values of clocks
1052 are set to 0 unless --x-initial-edge is specified. Initial values
1053 of all other state holding variables are controlled with
1054 --x-initial.
1055 --x-initial 0
1057 --x-initial fast
1058 --x-initial unique (default)
1059 Controls the two-state value that is used to initialize variables
1060 that are not otherwise initialized.
1061 --x-initial=0, initializes all otherwise uninitialized variables to
1063 zero.
1064 --x-initial=unique, the default, initializes variables using a
1066 function, which determines the value to use each initialization.
1067 This gives greatest flexibility and allows finding reset bugs. See
1068 "Unknown states"
1069 --x-initial=fast, is best for performance, and initializes all
1071 variables to a state Verilator determines is optimal. This may
1072 allow further code optimizations, but will likely hide any code
1073 bugs relating to missing resets.
1074 Note. This option applies only to initial values of variables.
1076 Initial values of clocks are set to 0 unless --x-initial-edge is
1077 specified.
1078 --x-initial-edge
1080 Enables emulation of event driven simulators which generally
1081 trigger an edge on a transition from X to 1 ("posedge") or X to 0
1082 ("negedge"). Thus the following code, where "rst_n" is
1083 uninitialized would set "res_n" to "1'b1" when "rst_n" is first set
1084 to zero:
1085 reg res_n = 1'b0;
1087 always @(negedge rst_n) begin
1089 if (rst_n == 1'b0) begin
1090 res_n <= 1'b1;
1091 end
1092 end
1093 In Verilator, by default, uninitialized clocks are given a value of
1095 zero, so the above "always" block would not trigger.
1096 While it is not good practice, there are some designs that rely on
1098 X X 0 triggering a "negedge", particularly in reset sequences.
1099 Using --x-initial-edge with Verilator will replicate this behavior.
1100 It will also ensure that X X 1 triggers a "posedge".
1101 Note. Some users have reported that using this option can affect
1103 convergence, and that it may be necessary to use --converge-limit
1104 to increase the number of convergence iterations. This may be
1105 another indication of problems with the modelled design that should
1106 be addressed.
1107 -y dir
1109 Add the directory to the list of directories that should be
1110 searched for include files or libraries. The three flags -y,
1111 +incdir and -I have similar effect; +incdir and +y are fairly
1112 standard across Verilog tools while -I is an alias for GCC
1113 compatibility.
1114 Verilator defaults to the current directory ("-y .") and any
1116 specified --Mdir, though these default paths are used after any
1117 user specified directories. This allows '-y "$(pwd)"' to be used
1118 if absolute filenames are desired for error messages instead of
1119 relative filenames.
1120
1122 We'll compile this example into C++.
1123 mkdir test_our
1125 cd test_our
1126 cat <<EOF >our.v
1128 module our;
1129 initial begin $display("Hello World"); $finish; end
1130 endmodule
1131 EOF
1132 cat <<EOF >sim_main.cpp
1134 #include "Vour.h"
1135 #include "verilated.h"
1136 int main(int argc, char** argv, char** env) {
1137 Verilated::commandArgs(argc, argv);
1138 Vour* top = new Vour;
1139 while (!Verilated::gotFinish()) { top->eval(); }
1140 delete top;
1141 exit(0);
1142 }
1143 EOF
1144 See the README in the source kit for various ways to install or point
1146 to Verilator binaries. In brief, if you are running Verilator that
1147 came from your operating system (as an RPM), or did a "make install" to
1148 place Verilator into your default path, you do not need anything
1149 special in your environment, and should not have VERILATOR_ROOT set.
1150 However, if you installed Verilator from sources and want to run
1151 Verilator out of where you compiled Verilator, you need to point to the
1152 kit:
1153 # See above; don't do this if using an OS-distributed Verilator
1155 export VERILATOR_ROOT=/path/to/where/verilator/was/installed
1156 export PATH=$VERILATOR_ROOT/bin:$PATH
1157 Now we run Verilator on our little example.
1159 verilator -Wall --cc our.v --exe sim_main.cpp
1161 We can see the source code under the "obj_dir" directory. See the
1163 FILES section below for descriptions of some of the files that were
1164 created.
1165 ls -l obj_dir
1167 We then can compile it
1169 make -j -C obj_dir -f Vour.mk Vour
1171 (Verilator included a default compile rule and link rule, since we used
1173 --exe and passed a .cpp file on the Verilator command line. You can
1174 also write your own compile rules, as we'll show in the SYSTEMC
1175 section.)
1176 And now we run it
1178 obj_dir/Vour
1180 And we get as output
1182 Hello World
1184 - our.v:2: Verilog $finish
1185 Really, you're better off writing a Makefile to do all this for you.
1187 Then, when your source changes it will automatically run all of these
1188 steps; to aid this Verilator can create a makefile dependency file.
1189 See the examples directory in the distribution.
1190
1192 This is an example similar to the above, but using SystemC.
1193 mkdir test_our_sc
1195 cd test_our_sc
1196 cat <<EOF >our.v
1198 module our (clk);
1199 input clk; // Clock is required to get initial activation
1200 always @ (posedge clk)
1201 begin $display("Hello World"); $finish; end
1202 endmodule
1203 EOF
1204 cat <<EOF >sc_main.cpp
1206 #include "Vour.h"
1207 int sc_main(int argc, char **argv) {
1208 Verilated::commandArgs(argc, argv);
1209 sc_clock clk ("clk",10, 0.5, 3, true);
1210 Vour* top;
1211 top = new Vour("top");
1212 top->clk(clk);
1213 while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
1214 delete top;
1215 exit(0);
1216 }
1217 EOF
1218 See the README in the source kit for various ways to install or point
1220 to Verilator binaries. In brief, if you are running Verilator that
1221 came from your operating system (as an RPM), or did a "make install" to
1222 place Verilator into your default path, you do not need anything
1223 special in your environment, and should not have VERILATOR_ROOT set.
1224 However, if you installed Verilator from sources and want to run
1225 Verilator out of where you compiled Verilator, you need to point to the
1226 kit:
1227 # See above; don't do this if using an OS-distributed Verilator
1229 export VERILATOR_ROOT=/path/to/where/verilator/was/installed
1230 export PATH=$VERILATOR_ROOT/bin:$PATH
1231 Now we run Verilator on our little example.
1233 verilator -Wall --sc our.v
1235 We then can compile it
1237 cd obj_dir
1239 make -j -f Vour.mk Vour__ALL.a
1240 make -j -f Vour.mk ../sc_main.o verilated.o
1241 And link with SystemC. Note your path to the libraries may vary,
1243 depending on the operating system.
1244 export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
1246 export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
1247 # Might be needed if SystemC 2.3.0
1248 export SYSTEMC_CXX_FLAGS=-pthread
1249 g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL*.o verilated.o \
1251 -o Vour -lsystemc
1252 And now we run it
1254 cd ..
1256 obj_dir/Vour
1257 And we get the same output as the C++ example:
1259 Hello World
1261 - our.v:2: Verilog $finish
1262 Really, you're better off using a Makefile to do all this for you.
1264 Then, when your source changes it will automatically run all of these
1265 steps. See the examples directory in the distribution.
1266
1268 For best performance, run Verilator with the "-O3 --x-assign=fast
1269 --x-initial=fast --noassert" flags. The -O3 flag will require longer
1270 compile times, and --x-assign=fast --x-initial=fast may increase the
1271 risk of reset bugs in trade for performance; see the above
1272 documentation for these flags.
1273 Minor Verilog code changes can also give big wins. You should not have
1275 any UNOPTFLAT warnings from Verilator. Fixing these warnings can
1276 result in huge improvements; one user fixed their one UNOPTFLAT warning
1277 by making a simple change to a clock latch used to gate clocks and
1278 gained a 60% performance improvement.
1279 Beyond that, the performance of a Verilated model depends mostly on
1281 your C++ compiler and size of your CPU's caches.
1282 By default, the lib/verilated.mk file has optimization turned off.
1284 This is for the benefit of new users, as it improves compile times at
1285 the cost of runtimes. To add optimization as the default, set one of
1286 three variables, OPT, OPT_FAST, or OPT_SLOW lib/verilated.mk. Or, use
1287 the -CFLAGS and/or -LDFLAGS option on the verilator command line to
1288 pass the flags directly to the compiler or linker. Or, just for one
1289 run, pass them on the command line to make:
1290 make OPT_FAST="-O2 -fno-stack-protector" -f Vour.mk Vour__ALL.a
1292 OPT_FAST specifies optimizations for those programs that are part of
1294 the fast path, mostly code that is executed every cycle. OPT_SLOW
1295 specifies optimizations for slow-path files (plus tracing), which
1296 execute only rarely, yet take a long time to compile with optimization
1297 on. OPT specifies overall optimization and affects all compiles,
1298 including those OPT_FAST and OPT_SLOW control. For best results, use
1299 OPT="-O2", and link with "-static". Nearly the same results can be had
1300 with much better compile times with OPT_FAST="-O1 -fstrict-aliasing".
1301 Higher optimization such as "-O3" may help, but gcc compile times may
1302 be excessive under O3 on even medium sized designs. Alternatively,
1303 some larger designs report better performance using "-Os".
1304 Unfortunately, using the optimizer with SystemC files can result in
1306 compiles taking several minutes. (The SystemC libraries have many
1307 little inlined functions that drive the compiler nuts.)
1308 For best results, use GCC 3.3 or newer. GCC 3.2 and earlier have
1310 optimization bugs around pointer aliasing detection, which can result
1311 in 2x performance losses.
1312 If you will be running many simulations on a single compile,
1314 investigate feedback driven compilation. With GCC, using
1315 -fprofile-arcs, then -fbranch-probabilities will yield another 15% or
1316 so.
1317 Modern compilers also support link-time optimization (LTO), which can
1319 help especially if you link in DPI code. To enable LTO on GCC, pass
1320 "-flto" in both compilation and link. Note LTO may cause excessive
1321 compile times on large designs.
1322 If you are using your own makefiles, you may want to compile the
1324 Verilated code with -DVL_INLINE_OPT=inline. This will inline functions,
1325 however this requires that all cpp files be compiled in a single
1326 compiler run.
1327 You may uncover further tuning possibilities by profiling the Verilog
1329 code. Use Verilator's --profile-cfuncs, then GCC's -g -pg. You can
1330 then run either oprofile or gprof to see where in the C++ code the time
1331 is spent. Run the gprof output through verilator_profcfunc and it will
1332 tell you what Verilog line numbers on which most of the time is being
1333 spent.
1334 When done, please let the author know the results. I like to keep tabs
1336 on how Verilator compares, and may be able to suggest additional
1337 improvements.
1338
1340 All output files are placed in the output directory name specified with
1341 the -Mdir option, or "obj_dir" if not specified.
1342 Verilator creates the following files in the output directory:
1344 {prefix}.mk // Make include file for compiling
1346 {prefix}_classes.mk // Make include file with class names
1347 For -cc and -sc mode, it also creates:
1349 {prefix}.cpp // Top level C++ file
1351 {prefix}.h // Top level header
1352 {prefix}{each_verilog_module}.cpp // Lower level internal C++ files
1353 {prefix}{each_verilog_module}.h // Lower level internal header files
1354 In certain optimization modes, it also creates:
1356 {prefix}__Dpi.h // DPI import and export declarations
1358 {prefix}__Inlines.h // Inline support functions
1359 {prefix}__Slow.cpp // Constructors and infrequent routines
1360 {prefix}__Syms.cpp // Global symbol table C++
1361 {prefix}__Syms.h // Global symbol table header
1362 {prefix}__Trace.cpp // Wave file generation code (--trace)
1363 {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc)
1364 {prefix}__stats.txt // Statistics (--stats)
1365 It also creates internal files that can be mostly ignored:
1367 {each_verilog_module}.vpp // Post-processed verilog (--debug)
1369 {prefix}.flags_vbin // Verilator dependencies
1370 {prefix}.flags_vpp // Pre-processor dependencies
1371 {prefix}__verFiles.dat // Timestamps for skip-identical
1372 {prefix}{misc}.d // Make dependencies (-MMD)
1373 {prefix}{misc}.dot // Debugging graph files (--debug)
1374 {prefix}{misc}.tree // Debugging files (--debug)
1375 After running Make, the C++ compiler should produce the following:
1377 {prefix} // Final executable (w/--exe argument)
1379 {prefix}__ALL.a // Library of all Verilated objects
1380 {prefix}{misc}.o // Intermediate objects
1381
1383 LD_LIBRARY_PATH
1384 A generic Linux/OS variable specifying what directories have shared
1385 object (.so) files. This path should include SystemC and any other
1386 shared objects needed at runtime.
1387 OBJCACHE
1389 Optionally specifies a caching or distribution program to place in
1390 front of all runs of the C++ Compiler. For example, "objcache
1391 --read --write", or "ccache". If using distcc, it would generally
1392 be run under either objcache or ccache; see the documentation for
1393 those programs.
1394 SYSTEMC
1396 Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not
1397 set. If set, specifies the directory containing the SystemC
1398 distribution. If not specified, it will come from a default
1399 optionally specified at configure time (before Verilator was
1400 compiled).
1401 SYSTEMC_ARCH
1403 Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the
1404 architecture name used by the SystemC kit. This is the part after
1405 the dash in the lib-{...} directory name created by a 'make' in the
1406 SystemC distribution. If not set, Verilator will try to intuit the
1407 proper setting, or use the default optionally specified at
1408 configure time (before Verilator was compiled).
1409 SYSTEMC_CXX_FLAGS
1411 Specifies additional flags that are required to be passed to GCC
1412 when building the SystemC model. System 2.3.0 may need this set to
1413 "-pthread".
1414 SYSTEMC_INCLUDE
1416 If set, specifies the directory containing the systemc.h header
1417 file. If not specified, it will come from a default optionally
1418 specified at configure time (before Verilator was compiled), or
1419 computed from SYSTEMC/include.
1420 SYSTEMC_LIBDIR
1422 If set, specifies the directory containing the libsystemc.a
1423 library. If not specified, it will come from a default optionally
1424 specified at configure time (before Verilator was compiled), or
1425 computed from SYSTEMC/lib-SYSTEMC_ARCH.
1426 VCS_HOME
1428 If set, specifies the directory containing the Synopsys VCS
1429 distribution. When set, a 'make test' in the Verilator
1430 distribution will also run VCS baseline regression tests.
1431 VERILATOR_BIN
1433 If set, specifies an alternative name of the Verilator binary. May
1434 be used for debugging and selecting between multiple operating
1435 system builds.
1436 VERILATOR_GDB
1438 If set, the command to run when using the --gdb option, such as
1439 "ddd". If not specified, it will use "gdb".
1440 VERILATOR_ROOT
1442 Specifies the directory containing the distribution kit. This is
1443 used to find the executable, Perl library, and include files. If
1444 not specified, it will come from a default optionally specified at
1445 configure time (before Verilator was compiled). It should not be
1446 specified if using a pre-compiled Verilator RPM as the hardcoded
1447 value should be correct.
1448
1450 Verilator creates a .h and .cpp file for the top level module and all
1451 modules under it. See the examples directory in the kit for examples.
1452 After the modules are completed, there will be a module.mk file that
1454 may be used with Make to produce a module__ALL.a file with all required
1455 objects in it. This is then linked with the user's top level to create
1456 the simulation executable.
1457 The user must write the top level of the simulation. Here's a simple
1459 example:
1460 #include <verilated.h> // Defines common routines
1462 #include <iostream> // Need std::cout
1463 #include "Vtop.h" // From Verilating "top.v"
1464 Vtop *top; // Instantiation of module
1466 vluint64_t main_time = 0; // Current simulation time
1468 // This is a 64-bit integer to reduce wrap over issues and
1469 // allow modulus. You can also use a double, if you wish.
1470 double sc_time_stamp () { // Called by $time in Verilog
1472 return main_time; // converts to double, to match
1473 // what SystemC does
1474 }
1475 int main(int argc, char** argv) {
1477 Verilated::commandArgs(argc, argv); // Remember args
1478 top = new Vtop; // Create instance
1480 top->reset_l = 0; // Set some inputs
1482 while (!Verilated::gotFinish()) {
1484 if (main_time > 10) {
1485 top->reset_l = 1; // Deassert reset
1486 }
1487 if ((main_time % 10) == 1) {
1488 top->clk = 1; // Toggle clock
1489 }
1490 if ((main_time % 10) == 6) {
1491 top->clk = 0;
1492 }
1493 top->eval(); // Evaluate model
1494 cout << top->out << endl; // Read a output
1495 main_time++; // Time passes...
1496 }
1497 top->final(); // Done simulating
1499 // // (Though this example doesn't get here)
1500 delete top;
1501 }
1502 Note signals are read and written as member variables of the lower
1504 module. You call the eval() method to evaluate the model. When the
1505 simulation is complete call the final() method to wrap up any
1506 SystemVerilog final blocks, and complete any assertions.
1507
1509 Verilator will convert the top level module to a SC_MODULE. This
1510 module will plug directly into a SystemC netlist.
1511 The SC_MODULE gets the same pinout as the Verilog module, with the
1513 following type conversions: Pins of a single bit become bool. Pins
1514 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's
1515 or vluint64_t's depending on the --no-pins64 switch. Wider pins become
1516 sc_bv's. (Uints simulate the fastest so are used where possible.)
1517 Lower modules are not pure SystemC code. This is a feature, as using
1519 the SystemC pin interconnect scheme everywhere would reduce performance
1520 by an order of magnitude.
1521
1523 Verilator supports SystemVerilog Direct Programming Interface import
1524 and export statements. Only the SystemVerilog form ("DPI-C") is
1525 supported, not the original Synopsys-only DPI.
1526 DPI Example
1528 In the SYSTEMC example above, if you wanted to import C++ functions
1529 into Verilog, put in our.v:
1530 import "DPI-C" function integer add (input integer a, input integer b);
1532 initial begin
1534 $display("%x + %x = %x", 1, 2, add(1,2));
1535 endtask
1536 Then after Verilating, Verilator will create a file Vour__Dpi.h with
1538 the prototype to call this function:
1539 extern int add (int a, int b);
1541 From the sc_main.cpp file (or another .cpp file passed to the Verilator
1543 command line, or the link), you'd then:
1544 #include "svdpi.h"
1546 #include "Vour__Dpi.h"
1547 int add (int a, int b) { return a+b; }
1548 DPI System Task/Functions
1550 Verilator extends the DPI format to allow using the same scheme to
1551 efficiently add system functions. Simply use a dollar-sign prefixed
1552 system function name for the import, but note it must be escaped.
1553 export "DPI-C" function integer \$myRand;
1555 initial $display("myRand=%d", $myRand());
1557 Going the other direction, you can export Verilog tasks so they can be
1559 called from C++:
1560 export "DPI-C" task publicSetBool;
1562 task publicSetBool;
1564 input bit in_bool;
1565 var_bool = in_bool;
1566 endtask
1567 Then after Verilating, Verilator will create a file Vour__Dpi.h with
1569 the prototype to call this function:
1570 extern bool publicSetBool(bool in_bool);
1572 From the sc_main.cpp file, you'd then:
1574 #include "Vour__Dpi.h"
1576 publicSetBool(value);
1577 Or, alternatively, call the function under the design class. This
1579 isn't DPI compatible but is easier to read and better supports multiple
1580 designs.
1581 #include "Vour__Dpi.h"
1583 Vour::publicSetBool(value);
1584 // or top->publicSetBool(value);
1585 Note that if the DPI task or function accesses any register or net
1587 within the RTL, it will require a scope to be set. This can be done
1588 using the standard functions within svdpi.h, after the module is
1589 instantiated, but before the task(s) and/or function(s) are called.
1590 For example, if the top level module is instantiated with the name
1592 "dut" and the name references within tasks are all hierarchical
1593 (dotted) names with respect to that top level module, then the scope
1594 could be set with
1595 #include "svdpi.h"
1597 ...
1598 svSetScope (svGetScopeFromName ("dut"));
1599 (Remember that Verilator adds a "V" to the top of the module
1601 hierarchy.)
1602 Scope can also be set from within a DPI imported C function that has
1604 been called from Verilog by querying the scope of that function. See
1605 the sections on DPI Context Functions and DPI Header Isolation below
1606 and the comments within the svdpi.h header for more information.
1607 DPI Display Functions
1609 Verilator allows writing $display like functions using this syntax:
1610 import "DPI-C" function void
1612 \$my_display (input string formatted /*verilator sformat*/ );
1613 The /*verilator sformat*/ indicates that this function accepts a
1615 $display like format specifier followed by any number of arguments to
1616 satisfy the format.
1617 DPI Context Functions
1619 Verilator supports IEEE DPI Context Functions. Context imports pass
1620 the simulator context, including calling scope name, and filename and
1621 line number to the C code. For example, in Verilog:
1622 import "DPI-C" context function int dpic_line();
1624 initial $display("This is line %d, again, line %d\n", `line, dpic_line());
1625 This will call C++ code which may then use the svGet* functions to read
1627 information, in this case the line number of the Verilog statement that
1628 invoked the dpic_line function:
1629 int dpic_line() {
1631 // Get a scope: svScope scope = svGetScope();
1632 const char* scopenamep = svGetNameFromScope(scope);
1634 assert(scopenamep);
1635 const char* filenamep = "";
1637 int lineno = 0;
1638 if (svGetCallerInfo(&filenamep, &lineno)) {
1639 printf("dpic_line called from scope %s on line %d\n",
1640 scopenamep, lineno);
1641 return lineno;
1642 } else {
1643 return 0;
1644 }
1645 }
1646 See the IEEE Standard for more information.
1648 DPI Header Isolation
1650 Verilator places the IEEE standard header files such as svdpi.h into a
1651 separate include directory, vltstd (VeriLaTor STandarD). When
1652 compiling most applications $VERILATOR_ROOT/include/vltstd would be in
1653 the include path along with the normal $VERILATOR_ROOT/include.
1654 However, when compiling Verilated models into other simulators which
1655 have their own svdpi.h and similar standard files with different
1656 contents, the vltstd directory should not be included to prevent
1657 picking up incompatible definitions.
1658 Public Functions
1660 Instead of DPI exporting, there's also Verilator public functions,
1661 which are slightly faster, but less compatible.
1662
1664 Verilator supports a very limited subset of the VPI. This subset
1665 allows inspection, examination, value change callbacks, and depositing
1666 of values to public signals only.
1667 VPI is enabled with the verilator --vpi switch.
1669 To access signals via the VPI, Verilator must be told exactly which
1671 signals are to be accessed. This is done using the Verilator public
1672 pragmas documented below.
1673 Verilator has an important difference from an event based simulator;
1675 signal values that are changed by the VPI will not immediately
1676 propagate their values, instead the top level header file's eval()
1677 method must be called. Normally this would be part of the normal
1678 evaluation (i.e. the next clock edge), not as part of the value change.
1679 This makes the performance of VPI routines extremely fast compared to
1680 event based simulators, but can confuse some test-benches that expect
1681 immediate propagation.
1682 Note the VPI by its specified implementation will always be much slower
1684 than accessing the Verilator values by direct reference
1685 (structure->module->signame), as the VPI accessors perform lookup in
1686 functions at runtime requiring at best hundreds of instructions, while
1687 the direct references are evaluated by the compiler and result in only
1688 a couple of instructions.
1689 For signal callbacks to work the main loop of the program must call
1691 VerilatedVpi::callValueCbs().
1692 VPI Example
1694 In the below example, we have readme marked read-only, and writeme
1695 which if written from outside the model will have the same semantics as
1696 if it changed on the specified clock edge.
1697 cat <<EOF >our.v
1699 module our (input clk);
1700 reg readme /*verilator public_flat_rd*/;
1701 reg writeme /*verilator public_flat_rw @(posedge clk) */;
1702 initial $finish;
1703 endmodule
1704 EOF
1705 There are many online tutorials and books on the VPI, but an example
1707 that accesses the above signal "readme" would be:
1708 cat <<EOF >sim_main.cpp
1710 #include "Vour.h"
1711 #include "verilated.h"
1712 #include "verilated_vpi.h" // Required to get definitions
1713 vluint64_t main_time = 0; // See comments in first example
1715 double sc_time_stamp () { return main_time; }
1716 void read_and_check() {
1718 vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
1719 if (!vh1) { vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found"); }
1720 const char* name = vpi_get_str(vpiName, vh1);
1721 printf("Module name: %s\n", name); // Prints "readme"
1722 s_vpi_value v;
1724 v.format = vpiIntVal;
1725 vpi_get_value(vh1, &v);
1726 printf("Value of v: %d\n", v.value.integer); // Prints "readme"
1727 }
1728 int main(int argc, char** argv, char** env) {
1730 Verilated::commandArgs(argc, argv);
1731 Vour* top = new Vour;
1732 Verilated::internalsDump(); // See scopes to help debug
1733 while (!Verilated::gotFinish()) {
1734 top->eval();
1735 VerilatedVpi::callValueCbs(); // For signal callbacks
1736 read_and_check();
1737 }
1738 delete top;
1739 exit(0);
1740 }
1741 EOF
1742
1744 Verilator supports cross-compiling Verilated code. This is generally
1745 used to run Verilator on a Linux system and produce C++ code that is
1746 then compiled on Windows.
1747 Cross compilation involves up to three different OSes. The build
1749 system is where you configured and compiled Verilator, the host system
1750 where you run Verilator, and the target system where you compile the
1751 Verilated code and run the simulation.
1752 Currently, Verilator requires the build and host system type to be the
1754 same, though the target system type may be different. To support this,
1755 ./configure and make Verilator on the build system. Then, run
1756 Verilator on the host system. Finally, the output of Verilator may be
1757 compiled on the different target system.
1758 To support this, none of the files that Verilator produces will
1760 reference any configure generated build-system specific files, such as
1761 config.h (which is renamed in Verilator to config_build.h to reduce
1762 confusion.) The disadvantage of this approach is that
1763 include/verilatedos.h must self-detect the requirements of the target
1764 system, rather than using configure.
1765 The target system may also require edits to the Makefiles, the simple
1767 Makefiles produced by Verilator presume the target system is the same
1768 type as the build system.
1769 Cadence NC-SystemC Models
1771 Similar to compiling Verilated designs with gcc, Verilated designs may
1772 be compiled inside other simulators that support C++ or SystemC models.
1773 One such simulator is Cadence's NC-SystemC, part of their Incisive
1774 Verification Suite. (Highly recommended.)
1775 Using the example files above, the following command will build the
1777 model underneath NC:
1778 cd obj_dir
1780 ncsc_run \
1781 sc_main.cpp \
1782 Vour__ALLcls.cpp \
1783 Vour__ALLsup.cpp \
1784 verilated.cpp
1785 For larger designs you'll want to automate this using makefiles, which
1787 pull the names of the .cpp files to compile in from the make variables
1788 generated in obj_dir/Vour_classes.mk.
1789
1791 In addition to the command line, warnings and other features may be
1792 controlled by configuration files, typically named with the .vlt
1793 extension. An example:
1794 `verilator_config
1796 lint_off -msg WIDTH
1797 lint_off -msg CASEX -file "silly_vendor_code.v"
1798 This disables WIDTH warnings globally, and CASEX for a specific file.
1800 Configuration files are parsed after the normal Verilog preprocessing,
1802 so `ifdefs, `defines, and comments may be used as if it were normal
1803 Verilog code.
1804 The grammar of configuration commands is as follows:
1806 `verilator_config
1808 Take remaining text up the the next `verilog mode switch and treat
1809 it as Verilator configuration commands.
1810 coverage_on [-file "<filename>" [-lines <line> [ - <line> ]]]
1812 coverage_off [-file "<filename>" [-lines <line> [ - <line> ]]]
1813 Enable/disable coverage for the specified filename (or wildcard
1814 with '*' or '?', or all files if omitted) and range of line numbers
1815 (or all lines if omitted). Often used to ignore an entire module
1816 for coverage analysis purposes.
1817 lint_on [-msg <message>] [-file "<filename>" [-lines <line> [ -
1819 <line>]]]
1820 lint_off [-msg <message>] [-file "<filename>" [-lines <line> [ -
1821 <line>]]]
1822 Enable/disables the specified lint warning, in the specified
1823 filename (or wildcard with '*' or '?', or all files if omitted) and
1824 range of line numbers (or all lines if omitted).
1825 With lint_off using '*' will override any lint_on directives in the
1827 source, i.e. the warning will still not be printed.
1828 If the -msg is omitted, all lint warnings (see list in -Wno-lint)
1830 are enabled/disabled. This will override all later lint warning
1831 enables for the specified region.
1832 tracing_on [-file "<filename>" [-lines <line> [ - <line> ]]]
1834 tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]
1835 Enable/disable waveform tracing for all future signals declared in
1836 the specified filename (or wildcard with '*' or '?', or all files
1837 if omitted) and range of line numbers (or all lines if omitted).
1838 For tracing_off, cells below any module in the files/ranges
1840 specified will also not be traced.
1841
1843 Verilog 2001 (IEEE 1364-2001) Support
1844 Verilator supports most Verilog 2001 language features. This includes
1845 signed numbers, "always @*", generate statements, multidimensional
1846 arrays, localparam, and C-style declarations inside port lists.
1847 Verilog 2005 (IEEE 1364-2005) Support
1849 Verilator supports most Verilog 2005 language features. This includes
1850 the `begin_keywords and `end_keywords compiler directives, $clog2, and
1851 the uwire keyword.
1852 SystemVerilog 2005 (IEEE 1800-2005) Support
1854 Verilator supports ==? and !=? operators, ++ and -- in some contexts,
1855 $bits, $countones, $error, $fatal, $info, $isunknown, $onehot,
1856 $onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit,
1857 byte, chandle, const, do-while, enum, export, final, import, int,
1858 interface, logic, longint, modport, package, program, shortint, struct,
1859 time, typedef, union, var, void, priority case/if, and unique case/if.
1860 It also supports .name and .* interconnection.
1862 Verilator partially supports concurrent assert and cover statements;
1864 see the enclosed coverage tests for the syntax which is allowed.
1865 SystemVerilog 2012 (IEEE 1800-2012) Support
1867 Verilator implements a full SystemVerilog 2012 preprocessor, including
1868 function call-like preprocessor defines, default define arguments,
1869 `__FILE__, `__LINE__ and `undefineall.
1870 Verilator currently has some support for SystemVerilog synthesis
1872 constructs. As SystemVerilog features enter common usage they are
1873 added; please file a bug if a feature you need is missing.
1874 SystemVerilog 2017 (IEEE 1800-2017) Support
1876 Verilator supports the 2017 "for" loop constructs, and several minor
1877 cleanups made in 1800-2017.
1878 Verilog AMS Support
1880 Verilator implements a very small subset of Verilog AMS (Verilog Analog
1881 and Mixed-Signal Extensions) with the subset corresponding to those VMS
1882 keywords with near equivalents in the Verilog 2005 or SystemVerilog
1883 2009 languages.
1884 AMS parsing is enabled with "--language VAMS" or "--language
1886 1800+VAMS".
1887 At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
1889 string, and wreal.
1890 Synthesis Directive Assertion Support
1892 With the --assert switch, Verilator reads any "//synopsys full_case" or
1893 "//synopsys parallel_case" directives. The same applies to any
1894 "//ambit synthesis", "//cadence" or "//pragma" directives of the same
1895 form.
1896 When these synthesis directives are discovered, Verilator will either
1898 formally prove the directive to be true, or failing that, will insert
1899 the appropriate code to detect failing cases at runtime and print an
1900 "Assertion failed" error message.
1901 Verilator likewise also asserts any "unique" or "priority"
1903 SystemVerilog keywords on case statement, as well as "unique" on if
1904 statements. However, "priority if" is currently simply ignored.
1905
1907 The following additional constructs are the extensions Verilator
1908 supports on top of standard Verilog code. Using these features outside
1909 of comments or `ifdef's may break other tools.
1910 `__FILE__
1912 The __FILE__ define expands to the current filename as a string,
1913 like C++'s __FILE__. This was incorporated into to the 1800-2009
1914 standard (but supported by Verilator since 2006!)
1915 `__LINE__
1917 The __LINE__ define expands to the current filename as a string,
1918 like C++'s __LINE__. This was incorporated into to the 1800-2009
1919 standard (but supported by Verilator since 2006!)
1920 `error string
1922 This will report an error when encountered, like C++'s #error.
1923 $c(string, ...);
1925 The string will be embedded directly in the output C++ code at the
1926 point where the surrounding Verilog code is compiled. It may
1927 either be a standalone statement (with a trailing ; in the string),
1928 or a function that returns up to a 32-bit number (without a
1929 trailing ;). This can be used to call C++ functions from your
1930 Verilog code.
1931 String arguments will be put directly into the output C++ code.
1933 Expression arguments will have the code to evaluate the expression
1934 inserted. Thus to call a C++ function, $c("func(",a,")") will
1935 result in 'func(a)' in the output C++ code. For input arguments,
1936 rather than hard-coding variable names in the string $c("func(a)"),
1937 instead pass the variable as an expression $c("func(",a,")"). This
1938 will allow the call to work inside Verilog functions where the
1939 variable is flattened out, and also enable other optimizations.
1940 If you will be reading or writing any Verilog variables inside the
1942 C++ functions, the Verilog signals must be declared with
1943 /*verilator public*/.
1944 You may also append an arbitrary number to $c, generally the width
1946 of the output. [signal_32_bits = $c32("...");] This allows for
1947 compatibility with other simulators which require a differently
1948 named PLI function name for each different output width.
1949 $display, $write, $fdisplay, $fwrite, $sformat, $swrite
1951 Format arguments may use C fprintf sizes after the % escape. Per
1952 the Verilog standard, %x prints a number with the natural width,
1953 and %0x prints a number with minimum width. Verilator extends this
1954 so %5x prints 5 digits per the C standard (it's unspecified in
1955 Verilog).
1956 `coverage_block_off
1958 Specifies the entire begin/end block should be ignored for coverage
1959 analysis. Must be inside a basic block, e.g. within a begin/end
1960 pair. Same as /* verilator coverage_block_off */.
1961 `systemc_header
1963 Take remaining text up to the next `verilog or `systemc_... mode
1964 switch and place it verbatim into the output .h file's header.
1965 Must be placed as a module item, e.g. directly inside a
1966 module/endmodule pair. Despite the name of this macro, this also
1967 works in pure C++ code.
1968 `systemc_ctor
1970 Take remaining text up to the next `verilog or `systemc_... mode
1971 switch and place it verbatim into the C++ class constructor. Must
1972 be placed as a module item, e.g. directly inside a module/endmodule
1973 pair. Despite the name of this macro, this also works in pure C++
1974 code.
1975 `systemc_dtor
1977 Take remaining text up to the next `verilog or `systemc_... mode
1978 switch and place it verbatim into the C++ class destructor. Must
1979 be placed as a module item, e.g. directly inside a module/endmodule
1980 pair. Despite the name of this macro, this also works in pure C++
1981 code.
1982 `systemc_interface
1984 Take remaining text up to the next `verilog or `systemc_... mode
1985 switch and place it verbatim into the C++ class interface. Must be
1986 placed as a module item, e.g. directly inside a module/endmodule
1987 pair. Despite the name of this macro, this also works in pure C++
1988 code.
1989 `systemc_imp_header
1991 Take remaining text up to the next `verilog or `systemc_... mode
1992 switch and place it verbatim into the header of all files for this
1993 C++ class implementation. Must be placed as a module item, e.g.
1994 directly inside a module/endmodule pair. Despite the name of this
1995 macro, this also works in pure C++ code.
1996 `systemc_implementation
1998 Take remaining text up to the next `verilog or `systemc_... mode
1999 switch and place it verbatim into a single file of the C++ class
2000 implementation. Must be placed as a module item, e.g. directly
2001 inside a module/endmodule pair. Despite the name of this macro,
2002 this also works in pure C++ code.
2003 If you will be reading or writing any Verilog variables in the C++
2005 functions, the Verilog signals must be declared with /*verilator
2006 public*/. See also the public task feature; writing an accessor
2007 may result in cleaner code.
2008 `SYSTEMVERILOG
2010 The SYSTEMVERILOG, SV_COV_START and related standard defines are
2011 set by default when --language is 1800-*.
2012 `VERILATOR
2014 `verilator
2015 `verilator3
2016 The VERILATOR, verilator and verilator3 defines are set by default
2017 so you may `ifdef around compiler specific constructs.
2018 `verilator_config
2020 Take remaining text up the the next `verilog mode switch and treat
2021 it as Verilator configuration commands.
2022 `verilog
2024 Switch back to processing Verilog code after a `systemc_... mode
2025 switch. The Verilog code returns to the last language mode
2026 specified with `begin_keywords, or SystemVerilog if none was
2027 specified.
2028 /*verilator clock_enable*/
2030 Used after a signal declaration to indicate the signal is used to
2031 gate a clock, and the user takes responsibility for insuring there
2032 are no races related to it. (Typically by adding a latch, and
2033 running static timing analysis.) For example:
2034 reg enable_r /*verilator clock_enable*/;
2036 wire gated_clk = clk & enable_r;
2037 always_ff @ (posedge clk)
2038 enable_r <= enable_early;
2039 The clock_enable attribute will cause the clock gate to be ignored
2041 in the scheduling algorithm, sometimes required for correct clock
2042 behavior, and always improving performance. It's also a good idea
2043 to enable the IMPERFECTSCH warning, to insure all clock enables are
2044 properly recognized.
2045 /*verilator clocker*/
2047 /*verilator no_clocker*/
2048 Used after a signal declaration to indicate the signal is used as
2049 clock or not. This information is used by Verilator to mark the
2050 signal as clocker and propagate the clocker attribute automatically
2051 to derived signals. See "--clk" for more information.
2052 /*verilator coverage_block_off*/
2054 Specifies the entire begin/end block should be ignored for coverage
2055 analysis purposes.
2056 /*verilator coverage_off*/
2058 Specifies that following lines of code should have coverage
2059 disabled. Often used to ignore an entire module for coverage
2060 analysis purposes.
2061 /*verilator coverage_on*/
2063 Specifies that following lines of code should have coverage re-
2064 enabled (if appropriate --coverage flags are passed) after being
2065 disabled earlier with /*verilator coverage_off*/.
2066 /*verilator inline_module*/
2068 Specifies the module the comment appears in may be inlined into any
2069 modules that use this module. This is useful to speed up
2070 simulation time with some small loss of trace visibility and
2071 modularity. Note signals under inlined submodules will be named
2072 submodule__DOT__subsignal as C++ does not allow "." in signal
2073 names. When tracing such signals the tracing routines will replace
2074 the __DOT__ with the period.
2075 /*verilator isolate_assignments*/
2077 Used after a signal declaration to indicate the assignments to this
2078 signal in any blocks should be isolated into new blocks. When
2079 there is a large combinatorial block that is resulting in a
2080 UNOPTFLAT warning, attaching this to the signal causing a false
2081 loop may clear up the problem.
2082 IE, with the following
2084 reg splitme /* verilator isolate_assignments*/;
2086 // Note the placement of the semicolon above
2087 always @* begin
2088 if (....) begin
2089 splitme = ....;
2090 other assignments
2091 end
2092 end
2093 Verilator will internally split the block that assigns to "splitme"
2095 into two blocks:
2096 It would then internally break it into (sort of):
2098 // All assignments excluding those to splitme
2100 always @* begin
2101 if (....) begin
2102 other assignments
2103 end
2104 end
2105 // All assignments to splitme
2106 always @* begin
2107 if (....) begin
2108 splitme = ....;
2109 end
2110 end
2111 /*verilator lint_off msg*/
2113 Disable the specified warning message for any warnings following
2114 the comment.
2115 /*verilator lint_on msg*/
2117 Re-enable the specified warning message for any warnings following
2118 the comment.
2119 /*verilator lint_restore*/
2121 After a /*verilator lint_save*/, pop the stack containing lint
2122 message state. Often this is useful at the bottom of include
2123 files.
2124 /*verilator lint_save*/
2126 Push the current state of what lint messages are turned on or
2127 turned off to a stack. Later meta-comments may then lint_on or
2128 lint_off specific messages, then return to the earlier message
2129 state by using /*verilator lint_restore*/. For example:
2130 // verilator lint_save
2132 // verilator lint_off SOME_WARNING
2133 ... // code needing SOME_WARNING turned off
2134 // verilator lint_restore
2135 If SOME_WARNING was on before the lint_off, it will now be restored
2137 to on, and if it was off before the lint_off it will remain off.
2138 /*verilator no_inline_module*/
2140 Specifies the module the comment appears in should not be inlined
2141 into any modules that use this module. This is useful especially
2142 at the top level module to reduce the size of the interface class,
2143 to aid compile time at a small performance loss.
2144 /*verilator no_inline_task*/
2146 Used in a function or task variable definition section to specify
2147 the function or task should not be inlined into where it is used.
2148 This may reduce the size of the final executable when a task is
2149 used a very large number of times. For this flag to work, the task
2150 and tasks below it must be pure; they cannot reference any
2151 variables outside the task itself.
2152 /*verilator public*/ (parameter)
2154 Used after a parameter declaration to indicate the emitted C code
2155 should have the parameter values visible. Due to C++ language
2156 restrictions, this may only be used on 64-bit or narrower integral
2157 enumerations.
2158 parameter [2:0] PARAM /*verilator public*/ = 2'b0;
2160 /*verilator public*/ (typedef enum)
2162 Used after an enum typedef declaration to indicate the emitted C
2163 code should have the enum values visible. Due to C++ language
2164 restrictions, this may only be used on 64-bit or narrower integral
2165 enumerations.
2166 typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
2168 /*verilator public*/ (variable)
2170 Used after an input, output, register, or wire declaration to
2171 indicate the signal should be declared so that C code may read or
2172 write the value of the signal. This will also declare this module
2173 public, otherwise use /*verilator public_flat*/.
2174 Instead of using public variables, consider instead making a DPI or
2176 public function that accesses the variable. This is nicer as it
2177 provides an obvious entry point that is also compatible across
2178 simulators.
2179 /*verilator public*/ (task/function)
2181 Used inside the declaration section of a function or task
2182 declaration to indicate the function or task should be made into a
2183 C++ function, public to outside callers. Public tasks will be
2184 declared as a void C++ function, public functions will get the
2185 appropriate non-void (bool, uint32_t, etc) return type. Any input
2186 arguments will become C++ arguments to the function. Any output
2187 arguments will become C++ reference arguments. Any local
2188 registers/integers will become function automatic variables on the
2189 stack.
2190 Wide variables over 64 bits cannot be function returns, to avoid
2192 exposing complexities. However, wide variables can be
2193 input/outputs; they will be passed as references to an array of
2194 32-bit numbers.
2195 Generally, only the values of stored state (flops) should be
2197 written, as the model will NOT notice changes made to variables in
2198 these functions. (Same as when a signal is declared public.)
2199 You may want to use DPI exports instead, as it's compatible with
2201 other simulators.
2202 /*verilator public_flat*/ (variable)
2204 Used after an input, output, register, or wire declaration to
2205 indicate the signal should be declared so that C code may read or
2206 write the value of the signal. This will not declare this module
2207 public, which means the name of the signal or path to it may change
2208 based upon the module inlining which takes place.
2209 /*verilator public_flat_rd*/ (variable)
2211 Used after an input, output, register, or wire declaration to
2212 indicate the signal should be declared public_flat (see above), but
2213 read-only.
2214 /*verilator public_flat_rw @(<edge_list>) */ (variable)
2216 Used after an input, output, register, or wire declaration to
2217 indicate the signal should be declared public_flat_rd (see above),
2218 and also writable, where writes should be considered to have the
2219 timing specified by the given sensitivity edge list.
2220 /*verilator public_module*/
2222 Used after a module statement to indicate the module should not be
2223 inlined (unless specifically requested) so that C code may access
2224 the module. Verilator automatically sets this attribute when the
2225 module contains any public signals or `systemc_ directives. Also
2226 set for all modules when using the --public switch.
2227 /*verilator sc_clock*/
2229 Rarely needed. Used after an input declaration to indicate the
2230 signal should be declared in SystemC as a sc_clock instead of a
2231 bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0
2232 and later do not require clock pins to be sc_clocks and this is no
2233 longer needed.
2234 /*verilator sc_bv*/
2236 Used after a port declaration. It sets the port to be of
2237 sc_bv<width> type, instead of bool, vluint32_t or vluint64_t. This
2238 may be useful if the port width is parametrized and different of
2239 such modules interface a templated module (such as a transactor) or
2240 for other reasons. In general you should avoid using this
2241 attribute when not necessary as with increasing usage of sc_bv the
2242 performance increases significantly.
2243 /*verilator sformat*/
2245 Attached to the final input of a function or task "input string" to
2246 indicate the function or task should pass all remaining arguments
2247 through $sformatf. This allows creation of DPI functions with
2248 $display like behavior. See the test_regress/t/t_dpi_display.v
2249 file for an example.
2250 /*verilator tag <text...>*/
2252 Attached after a variable or structure member to indicate opaque
2253 (to Verilator) text that should be passed through to the XML output
2254 as a tag, for use by downstream applications.
2255 /*verilator tracing_off*/
2257 Disable waveform tracing for all future signals that are declared
2258 in this module, or cells below this module. Often this is placed
2259 just after a primitive's module statement, so that the entire
2260 module and cells below it are not traced.
2261 /*verilator tracing_on*/
2263 Re-enable waveform tracing for all future signals or cells that are
2264 declared.
2265
2267 There are some limitations and lack of features relative to a
2268 commercial simulator, by intent. User beware.
2269 It is strongly recommended you use a lint tool before running this
2271 program. Verilator isn't designed to easily uncover common mistakes
2272 that a lint program will find for you.
2273 Synthesis Subset
2275 Verilator supports only the Synthesis subset with a few minor additions
2276 such as $stop, $finish and $display. That is, you cannot use
2277 hierarchical references, events or similar features of the Verilog
2278 language. It also simulates as Synopsys's Design Compiler would;
2279 namely a block of the form:
2280 always @ (x) y = x & z;
2282 This will recompute y when there is even a potential for change in x or
2284 a change in z, that is when the flops computing x or z evaluate (which
2285 is what Design Compiler will synthesize.) A compliant simulator would
2286 only calculate y if x changes. Use Verilog-Mode's /*AS*/ or Verilog
2287 2001's always @* to reduce missing activity items. Avoid putting
2288 $displays in combo blocks, as they may print multiple times when not
2289 desired, even on compliant simulators as event ordering is not
2290 specified.
2291 Signal Naming
2293 To avoid conflicts with C symbol naming, any character in a signal name
2294 that is not alphanumeric nor a single underscore will be replaced by
2295 __0hh where hh is the hex code of the character. To avoid conflicts
2296 with Verilator's internal symbols, any double underscore are replaced
2297 with ___05F (5F is the hex code of an underscore.)
2298 Bind
2300 Verilator only supports "bind" to a target module name, not an instance
2301 path.
2302 Dotted cross-hierarchy references
2304 Verilator supports dotted references to variables, functions and tasks
2305 in different modules. However, references into named blocks and
2306 function-local variables are not supported. The portion before the dot
2307 must have a constant value; for example a[2].b is acceptable, while
2308 a[x].b is not.
2309 References into generated and arrayed instances use the instance names
2311 specified in the Verilog standard; arrayed instances are named
2312 {cellName}[{instanceNumber}] in Verilog, which becomes
2313 {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code.
2314 Verilator creates numbered "genblk" when a begin: name is not specified
2316 around a block inside a generate statement. These numbers may differ
2317 between other simulators, but the Verilog specification does not allow
2318 users to use these names, so it should not matter.
2319 If you are having trouble determining where a dotted path goes wrong,
2321 note that Verilator will print a list of known scopes to help your
2322 debugging.
2323 Floating Point
2325 Floating Point (real) numbers are supported.
2326 Latches
2328 Verilator is optimized for edge sensitive (flop based) designs. It
2329 will attempt to do the correct thing for latches, but most performance
2330 optimizations will be disabled around the latch.
2331 Structures and Unions
2333 Verilator only presently supports packed structs and packed unions.
2334 Rand and randc tags on members are simply ignored. All structures and
2335 unions are represented as a single vector, which means that generating
2336 one member of a structure from blocking, and another from non-blocking
2337 assignments is unsupported.
2338 Time
2340 All delays (#) are ignored, as they are in synthesis.
2341 Unknown states
2343 Verilator is mostly a two state simulator, not a four state simulator.
2344 However, it has two features which uncover most initialization bugs
2345 (including many that a four state simulator will miss.)
2346 Identity comparisons (=== or !==) are converted to standard ==/!== when
2348 neither side is a constant. This may make the expression result differ
2349 from a four state simulator. An === comparison to X will always be
2350 false, so that Verilog code which checks for uninitialized logic will
2351 not fire.
2352 Assigning a variable to a X will actually assign the variable to a
2354 random value (see the --x-assign switch.) Thus if the value is
2355 actually used, the random value should cause downstream errors.
2356 Integers also randomize, even though the Verilog 2001 specification
2357 says they initialize to zero.
2358 All variables, depending on --x-initial setting, are typically randomly
2360 initialized using a function. By running several random simulation
2361 runs you can determine that reset is working correctly. On the first
2362 run, the function initializes variables to zero. On the second, have
2363 it initialize variables to one. On the third and following runs have
2364 it initialize them randomly. If the results match, reset works. (Note
2365 this is what the hardware will really do.) In practice, just setting
2366 all variables to one at startup finds most problems (since typically
2367 control signals are active-high).
2368 --x-assign applies to variables explicitly initialized or assigned to
2370 X. Uninitialized clocks are initialized to zero, while all other state
2371 holding variables are initialized to a random value. Event driven
2372 simulators will generally trigger an edge on a transition from X to 1
2373 ("posedge") or X to 0 ("negedge"). However, by default, since clocks
2374 are initialized to zero, Verilator will not trigger an initial negedge.
2375 Some code (particularly for reset) may rely on X->0 triggering an edge.
2376 The --x-initial-edge switch enables this behavior. Comparing runs with
2377 and without this switch will find such problems.
2378 Tri/Inout
2380 Verilator converts some simple tristate structures into two state.
2381 Pullup, pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and
2382 tri1 are also supported. Simple comparisons with === 1'bz are also
2383 supported.
2384 An assignment of the form:
2386 inout driver;
2388 wire driver = (enable) ? output_value : 1'bz;
2389 Will be converted to
2391 input driver; // Value being driven in from "external" drivers
2393 output driver__en; // True if driven from this module
2394 output driver__out; // Value being driven from this module
2395 External logic will be needed to combine these signals with any
2397 external drivers.
2398 Tristate drivers are not supported inside functions and tasks; an inout
2400 there will be considered a two state variable that is read and written
2401 instead of a four state variable.
2402 Functions & Tasks
2404 All functions and tasks will be inlined (will not become functions in
2405 C.) The only support provided is for simple statements in tasks (which
2406 may affect global variables).
2407 Recursive functions and tasks are not supported. All inputs and
2409 outputs are automatic, as if they had the Verilog 2001 "automatic"
2410 keyword prepended. (If you don't know what this means, Verilator will
2411 do what you probably expect -- what C does. The default behavior of
2412 Verilog is different.)
2413 Generated Clocks
2415 Verilator attempts to deal with generated and enabled clocks correctly,
2416 however some cases cause problems in the scheduling algorithm which is
2417 optimized for performance. The safest option is to have all clocks as
2418 primary inputs to the model, or wires directly attached to primary
2419 inputs. For proper behavior clock enables may also need the
2420 /*verilator clock_enable*/ attribute.
2421 Ranges must be big-bit-endian
2423 Bit ranges must be numbered with the MSB being numbered greater or the
2424 same as the LSB. Little-bit-endian buses [0:15] are not supported as
2425 they aren't easily made compatible with C++.
2426 Gate Primitives
2428 The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor)
2429 are directly converted to behavioral equivalents. The 3-state and MOS
2430 gate primitives are not supported. Tables are not supported.
2431 Specify blocks
2433 All specify blocks and timing checks are ignored.
2434 Array Initialization
2436 When initializing a large array, you need to use non-delayed
2437 assignments. Verilator will tell you when this needs to be fixed; see
2438 the BLKLOOPINIT error for more information.
2439 Array Out of Bounds
2441 Writing a memory element that is outside the bounds specified for the
2442 array may cause a different memory element inside the array to be
2443 written instead. For power-of-2 sized arrays, Verilator will give a
2444 width warning and the address. For non-power-of-2-sizes arrays, index
2445 0 will be written.
2446 Reading a memory element that is outside the bounds specified for the
2448 array will give a width warning and wrap around the power-of-2 size.
2449 For non-power-of-2 sizes, it will return a unspecified constant of the
2450 appropriate width.
2451 Assertions
2453 Verilator is beginning to add support for assertions. Verilator
2454 currently only converts assertions to simple "if (...) error"
2455 statements, and coverage statements to increment the line counters
2456 described in the coverage section.
2457 Verilator does not support SEREs yet. All assertion and coverage
2459 statements must be simple expressions that complete in one cycle.
2460 (Arguably SEREs are much of the point, but one must start somewhere.)
2461 Language Keyword Limitations
2463 This section describes specific limitations for each language keyword.
2464 `__FILE__, `__LINE__, `begin_keywords, `begin_keywords,
2466 `begin_keywords, `begin_keywords, `begin_keywords, `define, `else,
2467 `elsif, `end_keywords, `endif, `error, `ifdef, `ifndef, `include,
2468 `line, `systemc_ctor, `systemc_dtor, `systemc_header,
2469 `systemc_imp_header, `systemc_implementation, `systemc_interface,
2470 `timescale, `undef, `verilog
2471 Fully supported.
2472 always, always_comb, always_ff, always_latch, and, assign, begin, buf,
2474 byte, case, casex, casez, default, defparam, do-while, else, end,
2475 endcase, endfunction, endgenerate, endmodule, endspecify, endtask,
2476 final, for, function, generate, genvar, if, initial, inout, input, int,
2477 integer, localparam, logic, longint, macromodule, module, nand,
2478 negedge, nor, not, or, output, parameter, posedge, reg, scalared,
2479 shortint, signed, supply0, supply1, task, time, tri, typedef, var,
2480 vectored, while, wire, xnor, xor
2481 Generally supported.
2482 ++, -- operators
2484 Increment/decrement can only be used as standalone statements or in
2485 for loops. They cannot be used as side effect operators inside
2486 more complicate expressions ("a = b++;").
2487 '{} operator
2489 Assignment patterns with order based, default, constant integer
2490 (array) or member identifier (struct/union) keys are supported.
2491 Data type keys and keys which are computed from a constant
2492 expression are not supported.
2493 cast operator
2495 Casting is supported only between simple scalar types, signed and
2496 unsigned, not arrays nor structs.
2497 chandle
2499 Treated as a "longint"; does not yet warn about operations that are
2500 specified as illegal on chandles.
2501 disable
2503 Disable statements may be used only if the block being disabled is
2504 a block the disable statement itself is inside. This was commonly
2505 used to provide loop break and continue functionality before
2506 SystemVerilog added the break and continue keywords.
2507 inside
2509 Inside expressions may not include unpacked array traversal or $ as
2510 an upper bound. Case inside and case matches are also unsupported.
2511 interface
2513 Interfaces and modports, including with generated data types are
2514 supported. Generate blocks around modports are not supported, nor
2515 are virtual interfaces nor unnamed interfaces.
2516 priority if, unique if
2518 Priority and unique if's are treated as normal ifs and not asserted
2519 to be full nor unique.
2520 specify specparam
2522 All specify blocks and timing checks are ignored.
2523 string
2525 String is supported only to the point that they can be assigned,
2526 concatenated, compared, and passed to DPI imports. Standard method
2527 calls on strings are not supported.
2528 timeunit, timeprecision
2530 All timing control statements are ignored.
2531 uwire
2533 Verilator does not perform warning checking on uwires, it treats
2534 the uwire keyword as if it were the normal wire keyword.
2535 $bits, $countones, $error, $fatal, $finish, $info, $isunknown, $onehot,
2537 $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time,
2538 $unsigned, $warning.
2539 Generally supported.
2540 $display, $write, $fdisplay, $fwrite, $swrite
2542 $display and friends must have a constant format string as the
2543 first argument (as with C's printf). The rare usage which lists
2544 variables standalone without a format is not supported.
2545 $displayb, $displayh, $displayo, $writeb, $writeh, $writeo, etc
2547 The sized display functions are rarely used and so not supported.
2548 Replace them with a $write with the appropriate format specifier.
2549 $finish, $stop
2551 The rarely used optional parameter to $finish and $stop is ignored.
2552 $fopen, $fclose, $fdisplay, $feof, $fflush, $fgetc, $fgets, $fscanf,
2554 $fwrite
2555 File descriptors passed to the file PLI calls must be file
2556 descriptors, not MCDs, which includes the mode parameter to $fopen
2557 being mandatory.
2558 $fscanf, $sscanf
2560 Only integer formats are supported; %e, %f, %m, %r, %v, and %z are
2561 not supported.
2562 $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
2564 $setup, $setuphold, $skew, $timeskew, $width
2565 All specify blocks and timing checks are ignored.
2566 $random
2568 $random does not support the optional argument to set the seed.
2569 Use the srand function in C to accomplish this, and note there is
2570 only one random number generator (not one per module).
2571 $readmemb, $readmemh
2573 Read memory commands should work properly. Note Verilator and the
2574 Verilog specification does not include support for readmem to
2575 multi-dimensional arrays.
2576 $test$plusargs, $value$plusargs
2578 Supported, but the instantiating C++/SystemC testbench must call
2579 Verilated::commandArgs(argc, argv);
2581 to register the command line before calling $test$plusargs or
2583 $value$plusargs.
2584 $timeformat
2586 Not supported as Verilator needs to determine all formatting at
2587 compile time. Generally you can just ifdef them out for no ill
2588 effect. Note also VL_TIME_MULTIPLER can be defined at compile time
2589 to move the decimal point when displaying all times, model wide.
2590
2592 Warnings may be disabled in three ways. First, when the warning is
2593 printed it will include a warning code. Simply surround the offending
2594 line with a warn_off/warn_on pair:
2595 // verilator lint_off UNSIGNED
2597 if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
2598 // verilator lint_on UNSIGNED
2599 Second, warnings may be disabled using a configuration file with a
2601 lint_off command. This is useful when a script is suppressing warnings
2602 and the Verilog source should not be changed.
2603 Warnings may also be globally disabled by invoking Verilator with the
2605 "-Wno-warning" switch. This should be avoided, as it removes all
2606 checking across the designs, and prevents other users from compiling
2607 your code without knowing the magic set of disables needed to
2608 successfully compile your design.
2609 List of all warnings:
2611 ALWCOMBORDER
2613 Warns that an always_comb block has a variable which is set after
2614 it is used. This may cause simulation-synthesis mismatches, as not
2615 all commercial simulators allow this ordering.
2616 always_comb begin
2618 a = b;
2619 b = 1;
2620 end
2621 Ignoring this warning will only suppress the lint check, it will
2623 simulate correctly.
2624 ASSIGNIN
2626 Error that an assignment is being made to an input signal. This is
2627 almost certainly a mistake, though technically legal.
2628 input a;
2630 assign a = 1'b1;
2631 Ignoring this warning will only suppress the lint check, it will
2633 simulate correctly.
2634 ASSIGNDLY
2636 Warns that you have an assignment statement with a delayed time in
2637 front of it, for example:
2638 a <= #100 b;
2640 assign #100 a = b;
2641 Ignoring this warning may make Verilator simulations differ from
2643 other simulators, however at one point this was a common style so
2644 disabled by default as a code style warning.
2645 BLKANDNBLK
2647 BLKANDNBLK is an error that a variable comes from a mix of blocked
2648 and non-blocking assignments. Generally, this is caused by a
2649 register driven by both combo logic and a flop:
2650 always @ (posedge clk) foo[0] <= ...
2652 always @* foo[1] = ...
2653 Simply use a different register for the flop:
2655 always @ (posedge clk) foo_flopped[0] <= ...
2657 always @* foo[0] = foo_flopped[0];
2658 always @* foo[1] = ...
2659 This is not illegal in SystemVerilog, but a violation of good
2661 coding practice. Verilator reports this as an error, because
2662 ignoring this warning may make Verilator simulations differ from
2663 other simulators.
2664 It is generally safe to disable this error (with a "// verilator
2666 lint_off BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option)
2667 when one of the assignments is inside a public task, or when the
2668 blocked and non-blocking assignments have non-overlapping bits and
2669 structure members.
2670 BLKSEQ
2672 This indicates that a blocking assignment (=) is used in a
2673 sequential block. Generally non-blocking/delayed assignments (<=)
2674 are used in sequential blocks, to avoid the possibility of
2675 simulator races. It can be reasonable to do this if the generated
2676 signal is used ONLY later in the same block, however this style is
2677 generally discouraged as it is error prone.
2678 always @ (posedge clk) foo = ...
2680 Disabled by default as this is a code style warning; it will
2682 simulate correctly.
2683 BLKLOOPINIT
2685 This indicates that the initialization of an array needs to use
2686 non-delayed assignments. This is done in the interest of speed; if
2687 delayed assignments were used, the simulator would have to copy
2688 large arrays every cycle. (In smaller loops, loop unrolling allows
2689 the delayed assignment to work, though it's a bit slower than a
2690 non-delayed assignment.) Here's an example
2691 always @ (posedge clk)
2693 if (~reset_l) begin
2694 for (i=0; i<`ARRAY_SIZE; i++) begin
2695 array[i] = 0; // Non-delayed for verilator
2696 end
2697 This message is only seen on large or complicated loops because
2699 Verilator generally unrolls small loops. You may want to try
2700 increasing --unroll-count (and occasionally --unroll-stmts) which
2701 will raise the small loop bar to avoid this error.
2702 BSSPACE
2704 Warns that a backslash is followed by a space then a newline.
2705 Likely the intent was to have a backslash directly followed by a
2706 newline (e.g. when making a `define) and there's accidentally
2707 whitespace at the end of the line. If the space is not accidental,
2708 suggest removing the backslash in the code as it serves no
2709 function.
2710 Ignoring this warning will only suppress the lint check, it will
2712 simulate correctly.
2713 CASEINCOMPLETE
2715 Warns that inside a case statement there is a stimulus pattern for
2716 which there is no case item specified. This is bad style, if a
2717 case is impossible, it's better to have a "default: $stop;" or just
2718 "default: ;" so that any design assumption violations will be
2719 discovered in simulation.
2720 Ignoring this warning will only suppress the lint check, it will
2722 simulate correctly.
2723 CASEOVERLAP
2725 Warns that inside a case statement you have case values which are
2726 detected to be overlapping. This is bad style, as moving the order
2727 of case values will cause different behavior. Generally the values
2728 can be respecified to not overlap.
2729 Ignoring this warning will only suppress the lint check, it will
2731 simulate correctly.
2732 CASEX
2734 Warns that it is simply better style to use casez, and "?" in place
2735 of "x"'s. See
2736 <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>
2737 Ignoring this warning will only suppress the lint check, it will
2739 simulate correctly.
2740 CASEWITHX
2742 Warns that a case statement contains a constant with a "x".
2743 Verilator is two-state so interpret such items as always false.
2744 Note a common error is to use a "X" in a case or casez statement
2745 item; often what the user instead intended is to use a casez with
2746 "?".
2747 Ignoring this warning will only suppress the lint check, it will
2749 simulate correctly.
2750 COLONPLUS
2752 Warns that a :+ is seen. Likely the intent was to use +: to select
2753 a range of bits. If the intent was a range that is explicitly
2754 positive, suggest adding a space, e.g. use ": +".
2755 Ignoring this warning will only suppress the lint check, it will
2757 simulate correctly.
2758 CDCRSTLOGIC
2760 With --cdc only, warns that asynchronous flop reset terms come from
2761 other than primary inputs or flopped outputs, creating the
2762 potential for reset glitches.
2763 CLKDATA
2765 Warns that clock signal is mixed used with/as data signal. The
2766 checking for this warning is enabled only if user has explicitly
2767 marked some signal as clocker using command line option or in-
2768 source meta comment (see "--clk").
2769 The warning can be disabled without affecting the simulation
2771 result. But it is recommended to check the warning as this may
2772 degrade the performance of the Verilated model.
2773 CMPCONST
2775 Warns that you are comparing a value in a way that will always be
2776 constant. For example "X > 1" will always be true when X is a
2777 single bit wide.
2778 Ignoring this warning will only suppress the lint check, it will
2780 simulate correctly.
2781 COMBDLY
2783 Warns that you have a delayed assignment inside of a combinatorial
2784 block. Using delayed assignments in this way is considered bad
2785 form, and may lead to the simulator not matching synthesis. If
2786 this message is suppressed, Verilator, like synthesis, will convert
2787 this to a non-delayed assignment, which may result in logic races
2788 or other nasties. See
2789 <http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>
2790 Ignoring this warning may make Verilator simulations differ from
2792 other simulators.
2793 DECLFILENAME
2795 Warns that a module or other declaration's name doesn't match the
2796 filename with path and extension stripped that it is declared in.
2797 The filename a modules/interfaces/programs is declared in should
2798 match the name of the module etc. so that -y directory searching
2799 will work. This warning is printed for only the first mismatching
2800 module in any given file, and -v library files are ignored.
2801 Disabled by default as this is a code style warning; it will
2803 simulate correctly.
2804 DEFPARAM
2806 Warns that the "defparam" statement was deprecated in Verilog 2001
2807 and all designs should now be using the #(...) format to specify
2808 parameters.
2809 Disabled by default as this is a code style warning; it will
2811 simulate correctly.
2812 DETECTARRAY
2814 Error when Verilator tries to deal with a combinatorial loop that
2815 could not be flattened, and which involves a datatype which
2816 Verilator cannot handle, such as an unpacked struct or a large
2817 unpacked array. This typically ocurrs when -Wno-UNOPTFLAT has been
2818 used to override an UNOPTFLAT warning (see below).
2819 The solution is to break the loop, as described for UNOPTFLAT.
2821 ENDLABEL
2823 Warns that a label attached to a "end"-something statement does not
2824 match the label attached to the block start.
2825 Ignoring this warning will only suppress the lint check, it will
2827 simulate correctly.
2828 GENCLK
2830 Warns that the specified signal is generated, but is also being
2831 used as a clock. Verilator needs to evaluate sequential logic
2832 multiple times in this situation. In somewhat contrived cases
2833 having any generated clock can reduce performance by almost a
2834 factor of two. For fastest results, generate ALL clocks outside in
2835 C++/SystemC and make them primary inputs to your Verilog model.
2836 (However once need to you have even one, don't sweat additional
2837 ones.)
2838 Ignoring this warning may make Verilator simulations differ from
2840 other simulators.
2841 IFDEPTH
2843 Warns that if/if else statements have exceeded the depth specified
2844 with --if-depth, as they are likely to result in slow priority
2845 encoders. Unique and priority if statements are ignored.
2846 Solutions include changing the code to a case statement, or a
2847 SystemVerilog 'unique if' or 'priority if'.
2848 Disabled by default as this is a code style warning; it will
2850 simulate correctly.
2851 IMPERFECTSCH
2853 Warns that the scheduling of the model is not absolutely perfect,
2854 and some manual code edits may result in faster performance. This
2855 warning defaults to off, is not part of -Wall, and must be turned
2856 on explicitly before the top module statement is processed.
2857 IMPLICIT
2859 Warns that a wire is being implicitly declared (it is a single bit
2860 wide output from a sub-module.) While legal in Verilog, implicit
2861 declarations only work for single bit wide signals (not buses), do
2862 not allow using a signal before it is implicitly declared by a
2863 cell, and can lead to dangling nets. A better option is the
2864 /*AUTOWIRE*/ feature of Verilog-Mode for Emacs, available from
2865 <http://www.veripool.org/>
2866 Ignoring this warning will only suppress the lint check, it will
2868 simulate correctly.
2869 IMPURE
2871 Warns that a task or function that has been marked with /*verilator
2872 no_inline_task*/ references variables that are not local to the
2873 task. Verilator cannot schedule these variables correctly.
2874 Ignoring this warning may make Verilator simulations differ from
2876 other simulators.
2877 INCABSPATH
2879 Warns that an `include filename specifies an absolute path. This
2880 means the code will not work on any other system with a different
2881 file system layout. Instead of using absolute paths, relative
2882 paths (preferably without any directory specified whatever) should
2883 be used, and +incdir used on the command line to specify the top
2884 include source directories.
2885 Disabled by default as this is a code style warning; it will
2887 simulate correctly.
2888 INFINITELOOP
2890 Warns that a while or for statement has a condition that is always
2891 true. and thus result in an infinite loop if the statement ever
2892 executes.
2893 This might be unintended behavior if the loop body contains
2895 statements that in other statements that would make time pass,
2896 which Verilator is ignoring due to e.g. STMTDLY warnings being
2897 disabled.
2898 Ignoring this warning will only suppress the lint check, it will
2900 simulate correctly (i.e. hang due to the infinite loop).
2901 INITIALDLY
2903 Warns that you have a delayed assignment inside of an initial or
2904 final block. If this message is suppressed, Verilator will convert
2905 this to a non-delayed assignment. See also the COMBDLY warning.
2906 Ignoring this warning may make Verilator simulations differ from
2908 other simulators.
2909 LITENDIAN
2911 Warns that a packed vector is declared with little endian bit
2912 numbering (i.e. [0:7]). Big endian bit numbering is now the
2913 overwhelming standard, and little numbering is now thus often due
2914 to simple oversight instead of intent.
2915 Also warns that a cell is declared with little endian range (i.e.
2917 [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE
2918 the bits will likely be backwards from what you expect (i.e. cell
2919 [0] will connect to signal bit [N-1] not bit [0]).
2920 Ignoring this warning will only suppress the lint check, it will
2922 simulate correctly.
2923 MODDUP
2925 Error that a module has multiple definitions. Generally this
2926 indicates a coding error, or a mistake in a library file and it's
2927 good practice to have one module per file to avoid these issues.
2928 For some gate level netlists duplicates are unavoidable, and this
2929 error may be disabled.
2930 MULTIDRIVEN
2932 Warns that the specified signal comes from multiple always blocks.
2933 This is often unsupported by synthesis tools, and is considered bad
2934 style. It will also cause longer runtimes due to reduced
2935 optimizations.
2936 Ignoring this warning will only slow simulations, it will simulate
2938 correctly.
2939 MULTITOP
2941 Error that there are multiple top level modules, that is modules
2942 not instantiated by any other module. Verilator only supports a
2943 single top level, if you need more, create a module that wraps all
2944 of the top modules.
2945 Often this error is because some low level cell is being read in,
2947 but is not really needed. The best solution is to insure that each
2948 module is in a unique file by the same name. Otherwise, make sure
2949 all library files are read in as libraries with -v, instead of
2950 automatically with -y.
2951 PINCONNECTEMPTY
2953 Warns that a cell instantiation has a pin which is connected to
2954 .pin_name(), e.g. not another signal, but with an explicit mention
2955 of the pin. It may be desirable to disable PINCONNECTEMPTY, as
2956 this indicates intention to have a no-connect.
2957 Disabled by default as this is a code style warning; it will
2959 simulate correctly.
2960 PINMISSING
2962 Warns that a module has a pin which is not mentioned in a cell
2963 instantiation. If a pin is not missing it should still be
2964 specified on the cell declaration with a empty connection, using
2965 "(.pin_name())".
2966 Ignoring this warning will only suppress the lint check, it will
2968 simulate correctly.
2969 PINNOCONNECT
2971 Warns that a cell instantiation has a pin which is not connected to
2972 another signal.
2973 Disabled by default as this is a code style warning; it will
2975 simulate correctly.
2976 REALCVT
2978 Warns that a real number is being implicitly rounded to an integer,
2979 with possible loss of precision.
2980 REDEFMACRO
2982 Warns that you have redefined the same macro with a different
2983 value, for example:
2984 `define MACRO def1
2986 //...
2987 `define MACRO otherdef
2988 The best solution is to use a different name for the second macro.
2990 If this is not possible, add a undef to indicate the code is
2991 overriding the value:
2992 `define MACRO def1
2994 //...
2995 `undef MACRO
2996 `define MACRO otherdef
2997 SELRANGE
2999 Warns that a selection index will go out of bounds:
3000 wire vec[6:0];
3002 initial out = vec[7]; // There is no 7
3003 Verilator will assume zero for this value, instead of X. Note that
3005 in some cases this warning may be false, when a condition upstream
3006 or downstream of the access means the access out of bounds will
3007 never execute or be used.
3008 wire vec[6:0];
3010 initial begin
3011 seven = 7;
3012 ...
3013 if (seven != 7) out = vec[seven]; // Never will use vec[7]
3014 STMTDLY
3016 Warns that you have a statement with a delayed time in front of it,
3017 for example:
3018 #100 $finish;
3020 Ignoring this warning may make Verilator simulations differ from
3022 other simulators.
3023 SYMRSVDWORD
3025 Warning that a symbol matches a C++ reserved word and using this as
3026 a symbol name would result in odd C compiler errors. You may
3027 disable this warning, but the symbol will be renamed by Verilator
3028 to avoid the conflict.
3029 SYNCASYNCNET
3031 Warns that the specified net is used in at least two different
3032 always statements with posedge/negedges (i.e. a flop). One usage
3033 has the signal in the sensitivity list and body, probably as an
3034 async reset, and the other usage has the signal only in the body,
3035 probably as a sync reset. Mixing sync and async resets is usually
3036 a mistake. The warning may be disabled with a lint_off pragma
3037 around the net, or either flopped block.
3038 Disabled by default as this is a code style warning; it will
3040 simulate correctly.
3041 TASKNSVAR
3043 Error when a call to a task or function has a output from that task
3044 tied to a non-simple signal. Instead connect the task output to a
3045 temporary signal of the appropriate width, and use that signal to
3046 set the appropriate expression as the next statement. For example:
3047 task foo; output sig; ... endtask
3049 always @* begin
3050 foo(bus_we_select_from[2]); // Will get TASKNSVAR error
3051 end
3052 Change this to:
3054 reg foo_temp_out;
3056 always @* begin
3057 foo(foo_temp_out);
3058 bus_we_select_from[2] = foo_temp_out;
3059 end
3060 Verilator doesn't do this conversion for you, as some more
3062 complicated cases would result in simulator mismatches.
3063 UNDRIVEN
3065 Warns that the specified signal is never sourced. Verilator is
3066 fairly liberal in the usage calculations; making a signal public,
3067 or loading only a single array element marks the entire signal as
3068 driven.
3069 Disabled by default as this is a code style warning; it will
3071 simulate correctly.
3072 UNOPT
3074 Warns that due to some construct, optimization of the specified
3075 signal or block is disabled. The construct should be cleaned up to
3076 improve runtime.
3077 A less obvious case of this is when a module instantiates two
3079 submodules. Inside submodule A, signal I is input and signal O is
3080 output. Likewise in submodule B, signal O is an input and I is an
3081 output. A loop exists and a UNOPT warning will result if AI & AO
3082 both come from and go to combinatorial blocks in both submodules,
3083 even if they are unrelated always blocks. This affects performance
3084 because Verilator would have to evaluate each submodule multiple
3085 times to stabilize the signals crossing between the modules.
3086 Ignoring this warning will only slow simulations, it will simulate
3088 correctly.
3089 UNOPTFLAT
3091 Warns that due to some construct, optimization of the specified
3092 signal is disabled. The signal specified includes a complete scope
3093 to the signal; it may be only one particular usage of a multiply
3094 instantiated block. The construct should be cleaned up to improve
3095 runtime; two times better performance may be possible by fixing
3096 these warnings.
3097 Unlike the UNOPT warning, this occurs after netlist flattening, and
3099 indicates a more basic problem, as the less obvious case described
3100 under UNOPT does not apply.
3101 Often UNOPTFLAT is caused by logic that isn't truly circular as
3103 viewed by synthesis which analyzes interconnection per-bit, but is
3104 circular to simulation which analyzes per-bus:
3105 wire [2:0] x = {x[1:0],shift_in};
3107 This statement needs to be evaluated multiple times, as a change in
3109 "shift_in" requires "x" to be computed 3 times before it becomes
3110 stable. This is because a change in "x" requires "x" itself to
3111 change value, which causes the warning.
3112 For significantly better performance, split this into 2 separate
3114 signals:
3115 wire [2:0] xout = {x[1:0],shift_in};
3117 and change all receiving logic to instead receive "xout".
3119 Alternatively, change it to
3120 wire [2:0] x = {xin[1:0],shift_in};
3122 and change all driving logic to instead drive "xin".
3124 With this change this assignment needs to be evaluated only once.
3126 These sort of changes may also speed up your traditional event
3127 driven simulator, as it will result in fewer events per cycle.
3128 The most complicated UNOPTFLAT path we've seen was due to low bits
3130 of a bus being generated from an always statement that consumed
3131 high bits of the same bus processed by another series of always
3132 blocks. The fix is the same; split it into two separate signals
3133 generated from each block.
3134 The UNOPTFLAT warning may also be due to clock enables, identified
3136 from the reported path going through a clock gating cell. To fix
3137 these, use the clock_enable meta comment described above.
3138 The UNOPTFLAT warning may also occur where outputs from a block of
3140 logic are independent, but occur in the same always block. To fix
3141 this, use the isolate_assignments meta comment described above.
3142 To assist in resolving UNOPTFLAT, the option "--report-unoptflat"
3144 can be used, which will provide suggestions for variables that can
3145 be split up, and a graph of all the nodes connected in the loop.
3146 See the Arguments section for more details.
3147 Ignoring this warning will only slow simulations, it will simulate
3149 correctly.
3150 UNPACKED
3152 Warns that unpacked structs and unions are not supported.
3153 Ignoring this warning will make Verilator treat the structure as
3155 packed, which may make Verilator simulations differ from other
3156 simulators.
3157 UNSIGNED
3159 Warns that you are comparing a unsigned value in a way that implies
3160 it is signed, for example "X < 0" will always be true when X is
3161 unsigned.
3162 Ignoring this warning will only suppress the lint check, it will
3164 simulate correctly.
3165 UNUSED
3167 Warns that the specified signal is never sinked. Verilator is
3168 fairly liberal in the usage calculations; making a signal public, a
3169 signal matching --unused-regexp ("*unused*") or accessing only a
3170 single array element marks the entire signal as used.
3171 Disabled by default as this is a code style warning; it will
3173 simulate correctly.
3174 A recommended style for unused nets is to put at the bottom of a
3176 file code similar to the following:
3177 wire _unused_ok = &{1'b0,
3179 sig_not_used_a,
3180 sig_not_used_yet_b, // To be fixed
3181 1'b0};
3182 The reduction AND and constant zeros mean the net will always be
3184 zero, so won't use simulation time. The redundant leading and
3185 trailing zeros avoid syntax errors if there are no signals between
3186 them. The magic name "unused" (-unused-regexp) is recognized by
3187 Verilator and suppresses warnings; if using other lint tools,
3188 either teach to tool to ignore signals with "unused" in the name,
3189 or put the appropriate lint_off around the wire. Having unused
3190 signals in one place makes it easy to find what is unused, and
3191 reduces the number of lint_off pragmas, reducing bugs.
3192 USERINFO, USERWARN, USERERROR, USERFATAL
3194 A SystemVerilog elaboration-time assertion print was executed.
3195 VARHIDDEN
3197 Warns that a task, function, or begin/end block is declaring a
3198 variable by the same name as a variable in the upper level module
3199 or begin/end block (thus hiding the upper variable from being able
3200 to be used.) Rename the variable to avoid confusion when reading
3201 the code.
3202 Disabled by default as this is a code style warning; it will
3204 simulate correctly.
3205 WIDTH
3207 Warns that based on width rules of Verilog, two operands have
3208 different widths. Verilator generally can intuit the common usages
3209 of widths, and you shouldn't need to disable this message like you
3210 do with most lint programs. Generally other than simple mistakes,
3211 you have two solutions:
3212 If it's a constant 0 that's 32 bits or less, simply leave it
3214 unwidthed. Verilator considers zero to be any width needed.
3215 Concatenate leading zeros when doing arithmetic. In the statement
3217 wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0];
3219 The best fix, which clarifies intent and will also make all tools
3221 happy is:
3222 wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
3224 Ignoring this warning will only suppress the lint check, it will
3226 simulate correctly.
3227 WIDTHCONCAT
3229 Warns that based on width rules of Verilog, a concatenate or
3230 replication has an indeterminate width. In most cases this
3231 violates the Verilog rule that widths inside concatenates and
3232 replicates must be sized, and should be fixed in the code.
3233 wire [63:0] concat = {1,2};
3235 An example where this is technically legal (though still bad form)
3237 is:
3238 parameter PAR = 1;
3240 wire [63:0] concat = {PAR,PAR};
3241 The correct fix is to either size the 1 ("32'h1"), or add the width
3243 to the parameter definition ("parameter [31:0]"), or add the width
3244 to the parameter usage ("{PAR[31:0],PAR[31:0]}".
3245 The following describes the less obvious errors:
3247 Internal Error
3249 This error should never occur first, though may occur if earlier
3250 warnings or error messages have corrupted the program. If there
3251 are no other warnings or errors, submit a bug report.
3252 Unsupported: ....
3254 This error indicates that you are using a Verilog language
3255 construct that is not yet supported in Verilator. See the
3256 Limitations chapter.
3257 Verilated model didn't converge
3259 Verilator sometimes has to evaluate combinatorial logic multiple
3260 times, usually around code where a UNOPTFLAT warning was issued,
3261 but disabled. For example:
3262 always @ (a) b=~a;
3264 always @ (b) a=b
3265 will toggle forever and thus the executable will give the didn't
3267 converge error to prevent an infinite loop.
3268 To debug this, run Verilator with --profile-cfuncs. Run make on
3270 the generated files with "OPT=-DVL_DEBUG". Then call
3271 Verilated::debug(1) in your main.cpp.
3272 This will cause each change in a variable to print a message. Near
3274 the bottom you'll see the code and variable that causes the
3275 problem. For the program above:
3276 CHANGE: filename.v:1: b
3278 CHANGE: filename.v:2: a
3279
3281 Does it run under Windows?
3282 Yes, using Cygwin. Verilated output also compiles under Microsoft
3283 Visual C++ Version 7 or newer, but this is not tested every
3284 release.
3285 Can you provide binaries?
3287 Verilator is available as a RPM for Debian/Ubuntu, SuSE, Fedora,
3288 and perhaps other systems; this is done by porters and may slightly
3289 lag the primary distribution. If there isn't a binary build for
3290 your distribution, how about you set one up? Please contact the
3291 authors for assistance.
3292 Note people sometimes request binaries when they are having
3294 problems with their C++ compiler. Alas, binaries won't help this,
3295 as in the end a fully working C++ compiler is required to compile
3296 the output of Verilator.
3297 How can it be faster than (name-the-commercial-simulator)?
3299 Generally, the implied part is of the question is "... with all of
3300 the manpower they can put into developing it."
3301 Most commercial simulators have to be Verilog compliant, meaning
3303 event driven. This prevents them from being able to reorder blocks
3304 and make netlist-style optimizations, which are where most of the
3305 gains come from.
3306 Non-compliance shouldn't be scary. Your synthesis program isn't
3308 compliant, so your simulator shouldn't have to be -- and Verilator
3309 is closer to the synthesis interpretation, so this is a good thing
3310 for getting working silicon.
3311 Will Verilator output remain under my own license?
3313 Yes, it's just like using GCC on your programs; this is why
3314 Verilator uses the "GNU *Lesser* Public License Version 3" instead
3315 of the more typical "GNU Public License". See the licenses for
3316 details, but in brief, if you change Verilator itself or the header
3317 files Verilator includes, you must make the source code available
3318 under the GNU Lesser Public License. However, Verilator output
3319 (the Verilated code) only "include"s the licensed files, and so you
3320 are NOT required to release any output from Verilator.
3321 You also have the option of using the Perl Artistic License, which
3323 again does not require you release your Verilog or generated code,
3324 and also allows you to modify Verilator for internal use without
3325 distributing the modified version. But please contribute back to
3326 the community!
3327 One limit is that you cannot under either license release a
3329 commercial Verilog simulation product incorporating Verilator
3330 without making the source code available.
3331 As is standard with Open Source, contributions back to Verilator
3333 will be placed under the Verilator copyright and LGPL/Artistic
3334 license. Small test cases will be released into the public domain
3335 so they can be used anywhere, and large tests under the
3336 LGPL/Artistic, unless requested otherwise.
3337 Why is Verilation so slow?
3339 Verilator needs more memory than the resulting simulator will
3340 require, as Verilator creates internally all of the state of the
3341 resulting generated simulator in order to optimize it. If it takes
3342 more than a minute or so (and you're not using --debug since debug
3343 is disk bound), see if your machine is paging; most likely you need
3344 to run it on a machine with more memory. Verilator is a full
3345 64-bit application and may use more than 4GB, but about 1GB is the
3346 maximum typically needed, and very large commercial designs have
3347 topped 16GB.
3348 How do I generate waveforms (traces) in C++?
3350 See the next question for tracing in SystemC mode.
3351 Add the --trace switch to Verilator, and in your top level C code,
3353 call Verilated::traceEverOn(true). Then create a VerilatedVcdC
3354 object, and in your main loop call "trace_object->dump(time)" every
3355 time step, and finally call "trace_object->close()". For an
3356 example, see below and the examples/tracing_c/sim_main.cpp file of
3357 the distribution.
3358 You also need to compile verilated_vcd_c.cpp and add it to your
3360 link, preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to
3361 your Makefile's link rule. This is done for you if using the
3362 Verilator --exe flag.
3363 Note you can also call ->trace on multiple Verilated objects with
3365 the same trace file if you want all data to land in the same output
3366 file.
3367 #include "verilated_vcd_c.h"
3369 ...
3370 int main(int argc, char** argv, char** env) {
3371 ...
3372 Verilated::traceEverOn(true);
3373 VerilatedVcdC* tfp = new VerilatedVcdC;
3374 topp->trace (tfp, 99);
3375 tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
3376 ...
3377 while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
3378 main_time += #;
3379 tfp->dump (main_time);
3380 }
3381 tfp->close();
3382 }
3383 How do I generate waveforms (traces) in SystemC?
3385 Add the --trace switch to Verilator, and in your top level C
3386 sc_main code, include verilated_vcd_sc.h. Then call
3387 Verilated::traceEverOn(true). Then create a VerilatedVcdSc object
3388 as you would create a normal SystemC trace file. For an example,
3389 see the call to VerilatedVcdSc in the
3390 examples/tracing_sc/sc_main.cpp file of the distribution, and
3391 below.
3392 Alternatively you may use the C++ trace mechanism described in the
3394 previous question, however the timescale and timeprecision will not
3395 inherited from your SystemC settings.
3396 You also need to compile verilated_vcd_sc.cpp and
3398 verilated_vcd_c.cpp and add them to your link, preferably by adding
3399 the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule.
3400 This is done for you if using the Verilator --exe flag.
3401 Note you can also call ->trace on multiple Verilated objects with
3403 the same trace file if you want all data to land in the same output
3404 file.
3405 #include "verilated_vcd_sc.h"
3407 ...
3408 int main(int argc, char** argv, char** env) {
3409 ...
3410 Verilated::traceEverOn(true);
3411 VerilatedVcdSc* tfp = new VerilatedVcdSc;
3412 topp->trace (tfp, 99);
3413 tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
3414 ...
3415 sc_start(1);
3416 ...
3417 tfp->close();
3418 }
3419 How do I view waveforms (traces)?
3421 Verilator makes standard VCD (Value Change Dump) files. They are
3422 viewable with the public domain GtkWave (recommended) or Dinotrace
3423 (legacy) programs, or any of the many commercial offerings.
3424 How do I reduce the size of large waveform (trace) files?
3426 First, instead of calling VerilatedVcdC->open at the beginning of
3427 time, delay calling it until the time stamp where you want to
3428 tracing to begin. Likewise you can also call VerilatedVcdC->open
3429 before the end of time (perhaps a short period after you detect a
3430 verification error.)
3431 Next, add /*verilator tracing_off*/ to any very low level modules
3433 you never want to trace (such as perhaps library cells). Finally,
3434 use the --trace-depth option to limit the depth of tracing, for
3435 example --trace-depth 1 to see only the top level signals.
3436 Also be sure you write your trace files to a local solid-state
3438 disk, instead of to a network disk. Network disks are generally
3439 far slower.
3440 How do I do coverage analysis?
3442 Verilator supports both block (line) coverage and user inserted
3443 functional coverage.
3444 First, run verilator with the --coverage option. If you're using
3446 your own makefile, compile the model with the GCC flag
3447 -DVM_COVERAGE (if using Verilator's, it will do this for you.)
3448 At the end of your test, call VerilatedCov::write passing the name
3450 of the coverage data file (typically "logs/coverage.dat").
3451 Run each of your tests in different directories. Each test will
3453 create a logs/coverage.dat file.
3454 After running all of your tests, verilator_coverage is executed.
3456 Verilator_coverage reads the logs/coverage.dat file(s), and creates
3457 an annotated source code listing showing code coverage details.
3458 For an example, after running 'make test' in the Verilator
3460 distribution, see the examples/tracing_c/logs directory. Grep for
3461 lines starting with '%' to see what lines Verilator believes need
3462 more coverage.
3463 Where is the translate_off command? (How do I ignore a construct?)
3465 Translate on/off pragmas are generally a bad idea, as it's easy to
3466 have mismatched pairs, and you can't see what another tool sees by
3467 just preprocessing the code. Instead, use the preprocessor;
3468 Verilator defines the "VERILATOR" define for you, so just wrap the
3469 code in an ifndef region:
3470 `ifndef VERILATOR
3472 Something_Verilator_Dislikes;
3473 `endif
3474 Most synthesis tools similarly define SYNTHESIS for you.
3476 Why do I get "unexpected `do'" or "unexpected `bit'" errors?
3478 Do, bit, ref, return, and other words are now SystemVerilog
3479 keywords. You should change your code to not use them to insure it
3480 works with newer tools. Alternatively, surround them by the
3481 Verilog 2005/SystemVerilog begin_keywords pragma to indicate
3482 Verilog 2001 code.
3483 `begin_keywords "1364-2001"
3485 integer bit; initial bit = 1;
3486 `end_keywords
3487 If you want the whole file to be parsed as Verilog 2001, just
3489 create a file with
3490 `begin_keywords "1364-2001"
3492 and add it before other Verilog files on the command line. (Note
3494 this will also change the default for --prefix, so if you're not
3495 using --prefix, you will now need to.)
3496 How do I prevent my assertions from firing during reset?
3498 Call Verilated::assertOn(false) before you first call the model,
3499 then turn it back on after reset. It defaults to true. When
3500 false, all assertions controlled by --assert are disabled.
3501 Why do I get "undefined reference to `sc_time_stamp()'"?
3503 In C++ (non SystemC) code you need to define this function so that
3504 the simulator knows the current time. See the "CONNECTING TO C++"
3505 examples.
3506 Why do I get "undefined reference to `VL_RAND_RESET_I' or
3508 `Verilated::...'"?
3509 You need to link your compiled Verilated code against the
3510 verilated.cpp file found in the include directory of the Verilator
3511 kit. This is one target in the $(VK_GLOBAL_OBJS) make variable,
3512 which should be part of your Makefile's link rule. If you use
3513 --exe, this is done for you.
3514 Is the PLI supported?
3516 Only somewhat. More specifically, the common PLI-ish calls
3517 $display, $finish, $stop, $time, $write are converted to C++
3518 equivalents. You can also use the "import DPI" SystemVerilog
3519 feature to call C code (see the chapter above). There is also
3520 limited VPI access to public signals.
3521 If you want something more complex, since Verilator emits standard
3523 C++ code, you can simply write your own C++ routines that can
3524 access and modify signal values without needing any PLI interface
3525 code, and call it with $c("{any_c++_statement}").
3526 How do I make a Verilog module that contain a C++ object?
3528 You need to add the object to the structure that Verilator creates,
3529 then use $c to call a method inside your object. The
3530 test_regress/t/t_extend_class files show an example of how to do
3531 this.
3532 How do I get faster build times?
3534 Use a recent compiler. Newer compilers tend do be faster, with the
3535 now relatively old GCC 3.0 to 3.3 being horrible.
3536 Compile in parallel on many machines and use caching; see the web
3538 for the ccache, distcc and icecream packages. ccache will skip GCC
3539 runs between identical source builds, even across different users.
3540 You can use the OBJCACHE environment variable to use these CC
3541 wrappers. Also see the --output-split option.
3542 To reduce the compile time of classes that use a Verilated module
3544 (e.g. a top CPP file) you may wish to add /*verilator
3545 no_inline_module*/ to your top level module. This will decrease the
3546 amount of code in the model's Verilated class, improving compile
3547 times of any instantiating top level C++ code, at a relatively
3548 small cost of execution performance.
3549 Why do so many files need to recompile when I add a signal?
3551 Adding a new signal requires the symbol table to be recompiled.
3552 Verilator uses one large symbol table, as that results in 2-3 less
3553 assembly instructions for each signal access. This makes the
3554 execution time 10-15% faster, but can result in more compilations
3555 when something changes.
3556 How do I access functions/tasks in C?
3558 Use the SystemVerilog Direct Programming Interface. You write a
3559 Verilog function or task with input/outputs that match what you
3560 want to call in with C. Then mark that function as an external
3561 function. See the DPI chapter in the manual.
3562 How do I access signals in C?
3564 The best thing is to make a SystemVerilog "export DPI task" or
3565 function that accesses that signal, as described in the DPI chapter
3566 in the manual and DPI tutorials on the web. This will allow
3567 Verilator to better optimize the model and should be portable
3568 across simulators.
3569 If you really want raw access to the signals, declare the signals
3571 you will be accessing with a /*verilator public*/ comment before
3572 the closing semicolon. Then scope into the C++ class to read the
3573 value of the signal, as you would any other member variable.
3574 Signals are the smallest of 8-bit chars, 16-bit shorts, 32-bit
3576 longs, or 64-bit long longs that fits the width of the signal.
3577 Generally, you can use just uint32_t's for 1 to 32 bits, or
3578 vluint64_t for 1 to 64 bits, and the compiler will properly up-
3579 convert smaller entities.
3580 Signals wider than 64 bits are stored as an array of 32-bit
3582 uint32_t's. Thus to read bits 31:0, access signal[0], and for bits
3583 63:32, access signal[1]. Unused bits (for example bit numbers
3584 65-96 of a 65-bit vector) will always be zero. if you change the
3585 value you must make sure to pack zeros in the unused bits or core-
3586 dumps may result. (Because Verilator strips array bound checks
3587 where it believes them to be unnecessary.)
3588 In the SYSTEMC example above, if you had in our.v:
3590 input clk /*verilator public*/;
3592 // Note the placement of the semicolon above
3593 From the sc_main.cpp file, you'd then:
3595 #include "Vour.h"
3597 #include "Vour_our.h"
3598 cout << "clock is " << top->our->clk << endl;
3599 In this example, clk is a bool you can read or set as any other
3601 variable. The value of normal signals may be set, though clocks
3602 shouldn't be changed by your code or you'll get strange results.
3603 Should a module be in Verilog or SystemC?
3605 Sometimes there is a block that just interconnects cells, and have
3606 a choice as to if you write it in Verilog or SystemC. Everything
3607 else being equal, best performance is when Verilator sees all of
3608 the design. So, look at the hierarchy of your design, labeling
3609 cells as to if they are SystemC or Verilog. Then:
3610 A module with only SystemC cells below must be SystemC.
3612 A module with a mix of Verilog and SystemC cells below must be
3614 SystemC. (As Verilator cannot connect to lower-level SystemC
3615 cells.)
3616 A module with only Verilog cells below can be either, but for best
3618 performance should be Verilog. (The exception is if you have a
3619 design that is instantiated many times; in this case Verilating one
3620 of the lower modules and instantiating that Verilated cells
3621 multiple times into a SystemC module *may* be faster.)
3622
3624 First, check the the coding limitations section.
3625 Next, try the --debug switch. This will enable additional internal
3627 assertions, and may help identify the problem.
3628 Finally, reduce your code to the smallest possible routine that
3630 exhibits the bug. Even better, create a test in the test_regress/t
3631 directory, as follows:
3632 cd test_regress
3634 cp -p t/t_EXAMPLE.pl t/t_BUG.pl
3635 cp -p t/t_EXAMPLE.v t/t_BUG.v
3636 There are many hits on how to write a good test in the driver.pl
3638 documentation which can be seen by running:
3639 cd $VERILATOR_ROOT # Need the original distribution kit
3641 test_regress/driver.pl --help
3642 Edit t/t_BUG.pl to suit your example; you can do anything you want in
3644 the Verilog code there; just make sure it retains the single clk input
3645 and no outputs. Now, the following should fail:
3646 cd $VERILATOR_ROOT # Need the original distribution kit
3648 cd test_regress
3649 t/t_BUG.pl # Run on Verilator
3650 t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator
3651 t/t_BUG.pl --vcs # Run on a commercial simulator
3652 t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators
3653 The test driver accepts a number of options, many of which mirror the
3655 main Verilator option. For example the previous test could have been
3656 run with debugging enabled. The full set of test options can be seen
3657 by running driver.pl --help as shown above.
3658 Finally, report the bug using the bug tracker at
3660 <http://www.veripool.org/verilator>. The bug will become publicly
3661 visible; if this is unacceptable, mail the bug report to
3662 "wsnyder@wsnyder.org".
3663
3665 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group
3666 at Digital Equipment Corporation. The Verilog code that was converted
3667 to C was then merged with a C based CPU model of the Alpha processor
3668 and simulated in a C based environment called CCLI.
3669 In 1995 Verilator started being used also for Multimedia and Network
3671 Processor development inside Digital. Duane Galbi took over active
3672 development of Verilator, and added several performance enhancements.
3673 CCLI was still being used as the shell.
3674 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
3676 Digital graciously agreed to release the source code. (Subject to the
3677 code not being resold, which is compatible with the GNU Public
3678 License.)
3679 In 2001, Wilson Snyder took the kit, and added a SystemC mode, and
3681 called it Verilator2. This was the first packaged public release.
3682 In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator
3684 from scratch in C++. This added many optimizations, yielding about a
3685 2-5x performance gain.
3686 In 2009, major SystemVerilog and DPI language support was added.
3688 Currently, various language features and performance enhancements are
3690 added as the need arises. Verilator is now about 3x faster than in
3691 2002, and is faster than many popular commercial simulators.
3692
3694 When possible, please instead report bugs to
3695 <http://www.veripool.org/>.
3696 Wilson Snyder <wsnyder@wsnyder.org>
3698 Major concepts by Paul Wasson, Duane Galbi and Jie Xu.
3700
3702 Many people have provided ideas and other assistance with Verilator.
3703 The major corporate sponsors of Verilator, by providing significant
3705 contributions of time or funds include include Atmel Corporation,
3706 Cavium Inc., Compaq Corporation, Digital Equipment Corporation,
3707 Embecosm Ltd., Hicamp Systems, Intel Corporation, Mindspeed
3708 Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun
3709 Microsystems Inc., Nauticus Networks Inc., and SiCortex Inc.
3710 The people who have contributed major functionality are Byron Bradley,
3712 Jeremy Bennett, Jie Xu, Lane Brooks, John Coiner, Duane Galbi, Paul
3713 Wasson, and Wilson Snyder. Major testers included Jeff Dutton,
3714 Jonathon Donaldson, Ralf Karge, David Hewson, Iztok Jeras, Wim
3715 Michiels, Alex Solomatnikov, Sebastien Van Cauwenberghe, Gene Weber,
3716 and Clifford Wolf.
3717 Some of the people who have provided ideas and feedback for Verilator
3719 include: Ahmed El-Mahmoudy, David Addison, Tariq B. Ahmad, Nikana
3720 Anastasiadis, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad
3721 Bagri, Andrew Bardsley, Matthew Barr, Geoff Barrett, Julius Baxter,
3722 Jeremy Bennett, Michael Berman, David Binderman, Johan Bjork, David
3723 Black, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler,
3724 Byron Bradley, Bryan Brady, Charlie Brej, J Briquet, Lane Brooks, John
3725 Brownlee, Jeff Bush, Lawrence Butcher, Ted Campbell, Chris Candler,
3726 Lauren Carlson, Donal Casey, Terry Chen, Enzo Chi, Robert A. Clark,
3727 Allan Cochrane, John Coiner, Gunter Dannoritzer, Ashutosh Das, Bernard
3728 Deadman, John Demme, Mike Denio, John Deroo, Philip Derrick, John
3729 Dickol, Ruben Diez, Danny Ding, Ivan Djordjevic, Jonathon Donaldson,
3730 Sebastian Dressler, Alex Duller, Jeff Dutton, Usuario Eda, Chandan
3731 Egbert, Joe Eiler, Ahmed El-Mahmoudy, Robert Farrell, Eugen Fekete,
3732 Fabrizio Ferrandi, Brian Flachs, Andrea Foletto, Bob Fredieu, Christian
3733 Gelinek, Glen Gibb, Shankar Giri, Dan Gisselquist, Sam Gladstone, Amir
3734 Gonnen, Chitlesh Goorah, Xuan Guo, Neil Hamilton, Jannis Harder, Junji
3735 Hashimoto, Thomas Hawkins, Robert Henry, David Hewson, Jamey Hicks,
3736 Hiroki Honda, Alex Hornung, David Horton, Jae Hossell, Alan Hunter,
3737 Jamie Iles, Ben Jackson, Shareef Jalloq, Krzysztof Jankowski, HyungKi
3738 Jeong, Iztok Jeras, James Johnson, Christophe Joly, Franck Jullien,
3739 Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu
3740 Kandadi, Patricio Kaplan, Ralf Karge, Dan Katz, Sol Katzman, Jonathan
3741 Kimmitt, Olof Kindgren, Sobhan Klnv, Gernot Koch, Soon Koh, Steve
3742 Kolecki, Brett Koonce, Wojciech Koszek, Varun Koyyalagunta, David
3743 Kravitz, Roland Kruse, Sergey Kvachonok, Ed Lander, Steve Lang,
3744 Stephane Laurent, Walter Lavino, Christian Leber, Igor Lesik, John Li,
3745 Eivind Liland, Charlie Lind, Andrew Ling, Paul Liu, Derek Lockhart,
3746 Arthur Low, Stefan Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Mark
3747 Marshall, Alfonso Martinez, Yves Mathieu, Patrick Maupin, Jason
3748 McMullan, Elliot Mednick, Wim Michiels, Miodrag Milanovic, Wai Sum
3749 Mong, Sean Moore, Dennis Muhlestein, John Murphy, Richard Myers,
3750 Dimitris Nalbantis, Bob Newgard, Cong Van Nguyen, Paul Nitza, Pete
3751 Nixon, Lisa Noack, Mark Nodine, Andreas Olofsson, James Pallister, Brad
3752 Parker, Maciej Piechotka, David Pierce, Dominic Plunkett, David Poole,
3753 Mike Popoloski, Rich Porter, Niranjan Prabhu, Usha Priyadharshini, Mark
3754 Jackson Pulver, Prateek Puri, Chris Randall, Anton Rapp, Odd Magne
3755 Reitan, Frederic Requin, Alberto Del Rio, Oleg Rodionov, Paul Rolfe,
3756 Jan Egil Ruud, John Sanguinetti, Galen Seitz, Salman Sheikh, Mike
3757 Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Rodney Sinclair, Steven
3758 Slatter, Brian Small, Alex Solomatnikov, Wei Song, Art Stamness, John
3759 Stevenson, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki,
3760 Emerson Suguimoto, Gene Sullivan, Renga Sundararajan, Yutetsu
3761 Takatsukasa, Peter Tengstrand, Wesley Terpstra, Stefan Thiede, Gary
3762 Thomas, Kevin Thompson, Ian Thompson, Mike Thyer, Hans Tichelaar, Steve
3763 Tong, Michael Tresidder, Holger Waechtler, Stefan Wallentowitz, Shawn
3764 Wang, Greg Waters, Thomas Watts, Eugene Weber, David Welch, Thomas J
3765 Whatson, Leon Wildman, Gerald Williams, Trevor Williams, Jeff Winston,
3766 Joshua Wise, Clifford Wolf, Johan Wouters, Ding Xiaoliang, Jie Xu,
3767 Mandy Xu, Luke Yang, and Amir Yazdanbakhsh.
3768 Thanks to them, and all those we've missed including above.
3770
3772 The latest version is available from <http://www.veripool.org/>.
3773 Copyright 2003-2018 by Wilson Snyder. Verilator is free software; you
3775 can redistribute it and/or modify the Verilator internals under the
3776 terms of either the GNU Lesser General Public License Version 3 or the
3777 Perl Artistic License Version 2.0.
3778
3780 verilator_coverage, verilator_profcfunc, make,
3781 "verilator --help" which is the source for this document,
3783 and internals.txt in the distribution.
3785perl v5.28.1 2018-03-16 VERILATOR(1)