1VHIER(1) User Contributed Perl Documentation VHIER(1)
2
6 vhier - Return all files in a verilog hierarchy using Verilog::Netlist
7
9 vhier --help
10 vhier [verilog_options] [-o filename] [verilog_files.v...]
11
13 Vhier reads the Verilog files passed on the command line and outputs a
14 tree of all of the filenames, modules, and cells referenced by that
15 file.
16
18 The following arguments are compatible with GCC, VCS and most Verilog
19 programs.
20 +define+var+value =item -Dvar=value
22 Defines the given preprocessor symbol.
23 -f file
25 Read the specified file, and act as if all text inside it was
26 specified as command line parameters.
27 +incdir+dir =item -Idir
29 Add the directory to the list of directories that should be
30 searched for include directories or libraries.
31 +libext+ext+ext...
33 Specify the extensions that should be used for finding modules. If
34 for example module x is referenced, look in x.ext.
35 -y dir
37 Add the directory to the list of directories that should be
38 searched for include directories or libraries.
39
41 --help
42 Displays this message and program version and exits.
43 --o file
45 Use the given filename for output instead of stdout.
46 --cells
48 Show the module name of all cells in top-down order.
49 --input-files
51 Show all input filenames. Copying all of these files should result
52 in only those files needed to represent the entire design.
53 --language <1364-1995|1364-2001|1364-2005|1800-2005>
55 Set the language standard for the files. This determines which
56 tokens are signals versus keywords, such as the ever-common "do"
57 (data-out signal, versus a do-while loop keyword).
58 --resolve-files
60 Show resolved filenames passed on the command line. This will
61 convert raw module and filenames without paths to include the
62 library search path directory. Output filenames will be in the
63 same order as passed on the command line. Unlike --input-files or
64 --module-files, hierarchy is not traversed.
65 --module-files
67 Show all module filenames in top-down order. Child modules will
68 always appear as low as possible, so that reversing the list will
69 allow bottom-up processing of modules. Unlike input-files, header
70 files are not included.
71 --modules
73 Show all module names.
74 --nomissing
76 Do not complain about references to missing modules.
77 --missing-modules
79 With --nomissing, show all modules that are not found.
80 --top-module module
82 Start the report at the specified module name, ignoring all modules
83 that are not the one specified with --top-module or below, and
84 report an error if the --top-module specified does not exist.
85 Without this option vhier will report all modules, starting at the
86 module(s) that have no children below them.
87 Note this option will not change the result of the --input-files
89 list, as the files needed to parse any design are independent of
90 which modules are used.
91 --version
93 Displays program version and exits.
94
96 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
97 software tool suite. The latest version is available from CPAN and
98 from http://www.veripool.org/verilog-perl
99 <http://www.veripool.org/verilog-perl>.
100 Copyright 2005-2009 by Wilson Snyder. This package is free software;
102 you can redistribute it and/or modify it under the terms of either the
103 GNU Lesser General Public License Version 3 or the Perl Artistic
104 License Version 2.0.
105
107 Wilson Snyder <wsnyder@wsnyder.org>
108
110 Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist
111perl v5.12.0 2009-07-20 VHIER(1)