DS28E04(3)

1DS28E04-100(3)               One-Wire File System               DS28E04-100(3)
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NAME

6       DS28E04 - 1-Wire EEPROM chip (4096-bit) with seven address inputs
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SYNOPSIS

9       4096-bit EEPROM, 2 port switch
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11       1C  [.]XXXXXXXXXXXX[XX][/[  latch.[0-1|ALL|BYTE] | PIO.[0-1|ALL|BYTE] |
12       power | sensed.[0-1|ALL|BYTE] | polarity | por | set_alarm | address  |
13       crc8 | id | locator | r_address | r_id | r_locator | type ]]
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FAMILY CODE

16       1C
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SPECIAL PROPERTIES

19   latch.0 latch.1 latch.ALL latch.BYTE
20       read-write, binary
21       The  2  pins  (PIO) latch a bit when their state changes, either exter‐
22       nally, or through a write to the pin.
23       Reading the latch property indicates that the latch has been set.
24       Writing any data to ANY latch will reset them all. (This is  the  hard‐
25       ware design).
26       ALL is all latch states, accessed simultaneously, comma separated.
27       BYTE references all channels simultaneously as a single byte. Channel 0
28       is bit 0.
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30   PIO.0 PIO.1 PIO.ALL PIO.BYTE
31       read-write, yes-no
32       State of the open-drain output ( PIO ) pin. 0 = non-conducting = off, 1
33       = conducting = on.
34       Writing  zero  will  turn  off  the  switch,  non-zero will turn on the
35       switch. Reading the PIO state will return the switch setting. To deter‐
36       mine  the  actual  logic  level  at  the  switch, refer to the sensed.0
37       sensed.1 sensed.ALL sensed.BYTE property.
38       ALL references all channels simultaneously, comma separated.
39       BYTE references all channels simultaneously as a single byte. Channel 0
40       is bit 0.
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42   power
43       read-only, yes-no
44       Is  the DS28E04 powered parasitically (=0) or separately on the Vcc pin
45       (=1)?
46
47   sensed.0 sensed.1 sensed.ALL sensed.BYTE
48       read-only, yes-no
49       Logic level at the PIO pin. 0 = ground. 1 = high (~2.4V - 5V ).  Really
50       makes  sense only if the PIO state is set to zero (off), else will read
51       zero.
52       ALL references all channels simultaneously, comma separated.
53       BYTE references all channels simultaneously as a single byte. Channel 0
54       is bit 0.
55
56   polarity
57       read-only, yes-no
58       Reports  the  state  of the POL pin. The state of the POL pin specifies
59       whether the PIO pins P0 and P1 power up high or low. The polarity of  a
60       pulse  generated  at  a  PIO  pin is the opposite of the pin's power-up
61       state.
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63       0      PIO powers up 0
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65       1      PIO powers up 1
66
67   por
68       read-write, yes-no
69       Specifies whether the device has performed power-on reset. This bit can
70       only  be  cleared to 0 under software control. As long as this bit is 1
71       the device will allways respond to a conditional search.
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73   set_alarm
74       read-write, integer unsigned (0-333)
75       A number consisting of 3 digits XYY, where:
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77       X      select source and logical term
78              0 PIO   OR
79              1 latch OR
80              2 PIO   AND
81              3 latch AND
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83       Y      select channel and polarity
84              0 Unselected (LOW)
85              1 Unselected (HIGH)
86              2 Selected    LOW
87              3 Selected    HIGH
88
89       All digits will be truncated to  the  0-3  range.  Leading  zeroes  are
90       optional. Low-order digit is channel 0.
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92       Example:
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94       133    Responds  on  Conditional Search when latch.1 or latch.0 are set
95              to 1.
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97       222    Responds on Conditional Search when sensed.1  and  sensed.0  are
98              set to 0.
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100       000 (0)
101              Never responds to Conditional Search.
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STANDARD PROPERTIES

104   address
105   r_address
106       read-only, ascii
107       The  entire  64-bit  unique  ID. Given as upper case hexidecimal digits
108       (0-9A-F).
109       address starts with the family code
110       r address is the address in reverse order, which is often used in other
111       applications and labeling.
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113   crc8
114       read-only, ascii
115       The  8-bit error correction portion. Uses cyclic redundancy check. Com‐
116       puted from the preceding 56 bits of the  unique  ID  number.  Given  as
117       upper case hexidecimal digits (0-9A-F).
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119   family
120       read-only, ascii
121       The  8-bit  family  code. Unique to each type of device. Given as upper
122       case hexidecimal digits (0-9A-F).
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124   id
125   r_id
126       read-only, ascii
127       The 48-bit middle portion of the unique ID number. Does not include the
128       family code or CRC. Given as upper case hexidecimal digits (0-9A-F).
129       r  id is the id in reverse order, which is often used in other applica‐
130       tions and labeling.
131
132   locator
133   r_locator
134       read-only, ascii
135       Uses an extension of the 1-wire design from  iButtonLink  company  that
136       associated  1-wire  physical  connections with a unique 1-wire code. If
137       the connection is behind a Link Locator the locator will show a  unique
138       8-byte number (16 character hexidecimal) starting with family code FE.
139       If  no  Link  Locator is between the device and the master, the locator
140       field will be all FF.
141       r locator is the locator in reverse order.
142
143   present (DEPRECATED)
144       read-only, yes-no
145       Is the device currently present on the 1-wire bus?
146
147   type
148       read-only, ascii
149       Part name assigned by Dallas Semi. E.g.  DS2401  Alternative  packaging
150       (iButton vs chip) will not be distiguished.
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ALARMS

153       Use the set_alarm property to set the alarm triggering criteria.
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DESCRIPTION

156   1-Wire
157       1-wire is a wiring protocol and series of devices designed and manufac‐
158       tured by Dallas Semiconductor, Inc. The bus is  a  low-power  low-speed
159       low-connector scheme where the data line can also provide power.
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161       Each  device  is  uniquely and unalterably numbered during manufacture.
162       There are a wide variety of devices, including memory, sensors  (humid‐
163       ity, temperature, voltage, contact, current), switches, timers and data
164       loggers. More complex devices (like thermocouple sensors) can be  built
165       with  these  basic  devices.  There  are  also 1-wire devices that have
166       encryption included.
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168       The 1-wire scheme uses a single bus master and multiple slaves  on  the
169       same  wire.  The bus master initiates all communication. The slaves can
170       be individually discovered and addressed using their unique ID.
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172       Bus masters come in a variety of configurations including serial,  par‐
173       allel, i2c, network or USB adapters.
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175   OWFS design
176       OWFS  is  a  suite of programs that designed to make the 1-wire bus and
177       its devices easily accessible. The underlying principle is to create  a
178       virtual  filesystem,  with  the  unique ID being the directory, and the
179       individual properties of the device are  represented  as  simple  files
180       that can be read and written.
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182       Details  of  the  individual slave or master design are hidden behind a
183       consistent interface. The goal is to provide an easy set of tools for a
184       software  designer  to create monitoring or control applications. There
185       are some performance enhancements in the implementation, including data
186       caching, parallel access to bus masters, and aggregation of device com‐
187       munication. Still the fundemental goal has been ease of use,  flexibil‐
188       ity and correctness rather than speed.
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190   DS28E04
191       The DS28E04 (3) is a memory chip that bends the unique addressing capa‐
192       bilities of the 1-wire design. Some of the ID bits can be  assigned  by
193       hardware.
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ADDRESSING

196       All  1-wire  devices are factory assigned a unique 64-bit address. This
197       address is of the form:
198
199       Family Code
200              8 bits
201
202       Address
203              48 bits
204
205       CRC    8 bits
206
207       Addressing under OWFS is in hexidecimal, of form:
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209              01.123456789ABC
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211       where 01 is an example 8-bit family code, and 12345678ABC is an example
212       48 bit address.
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214       The  dot  is  optional,  and the CRC code can included. If included, it
215       must be correct.
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DATASHEET

218       http://pdfserv.maxim-ic.com/en/ds/DS28E04.pdf
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AVAILABILITY

281       http://www.owfs.org
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AUTHOR

284       Paul Alfille (paul.alfille@gmail.com)
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288OWFS Manpage                         2003                       DS28E04-100(3)