vbe(5alc)

1VBE(5)              VHDL subset of ASIM/LIP6/CAO-VLSI lab.              VBE(5)
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NAME

6       vbe
7       VHDL behavioural subset.
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DESCRIPTION

11       This  document  describes the ALLIANCE VHDL subset for behavioural data
12       flow descriptions.
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14
15       CONCURRENT STATEMENTS
16       In a data flow architecture only concurrent statements (except process)
17       are  supported.  All  sequential  statements  including  loops,  signal
18       assignment, etc .. are to be banished.
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20
21       Allowed concurrent statements are:
22              simple signal assignment
23              conditional signal assignment
24              selected signal assignment
25              concurrent assert statement
26              block statement
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28
29       BUSES
30       When using concurrent statements, an ordinary signal  can  be  assigned
31       only  once.   The value of the signal must be explicitly defined by the
32       signal assignment (for example, in a  selected  signal  assignment  the
33       value  of  the  target signal is to be defined for every value that the
34       select expression can take).
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37       The above constraint may be felt as a hard restriction  when  designing
38       distributed  controlled  hardware  (precharged line, distributed multi‐
39       plexer, etc ...). To hurdle this, VHDL uses a special feature: guarded-
40       resolved signals.
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42
43       A  resolved  signal  is  a signal declared with a resolved subtype (see
44       vhdl(5)).  A resolved subtype is a  type  combined  with  a  resolution
45       function.  A resolved signal can be assigned by multiple signal assign‐
46       ments. Depending on the value of each driver, the  resolution  function
47       determines the effective value of the signal.
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50       A  guarded  signal  is  a resolved signal with drivers that can be dis‐
51       conected.  A guarded signal must be assigned inside a  block  statement
52       through a guarded signal assignment.
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54
55       A distributed multiplexer may be described as :
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57       signal Distributed_Mux : mux_bit bus;
58
59       begin
60
61       first_driver_of_mux : block (Sel1 = '1')
62       begin
63         Distributed_Mux <= guarded Data1;
64       end block;
65
66       second_driver_of_mux : block (Sel2 = '1')
67       begin
68         Distributed_Mux <= guarded Data2;
69       end block;
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73       LATCHES and REGISTERS
74       Sequential  elements must be explicitly declared using the type reg_bit
75       or reg_vector (and must be of kind register). A sequential element must
76       be assigned inside a block statement by a guarded signal assignment.
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78
79       Rising edge triggered D flip flop :
80
81       signal Reg : reg_bit register;
82
83       begin
84
85       flip_flop : block (ck = '1' and not ck'STABLE)
86       begin
87         Reg <= guarded Din;
88       end block;
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90
91       Level sensitive latch:
92
93       signal Reg : reg_bit register;
94
95       begin
96
97       latch : block (ck = '1')
98       begin
99         Lat <= guarded Din;
100       end block;
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102
103       In  both  cases, the guard expression must depend only on one signal if
104       the description is to be processed by the  logic  synthetizer  (boom  +
105       boog).
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107
108       The  following  operators  are  only supported: not, and, or, xor, nor,
109       nand, &, =, /=
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111
112       They can be applied on all types supported by the subset.  Other  stan‐
113       dard  VHDL operators (+, -, >, <, ...) have not been implemented in the
114       present release.
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118       TIMING
119       Timing information can be specified in behavioural  descriptions  using
120       after  clauses. However, those delays are currently only used for simu‐
121       lation. After clauses are supported but not used for synthesis and for‐
122       mal proof.
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124
125       After  clauses in block statements (for guarded signal assignments) are
126       not supported for sequential elements (signals of kind  register),  but
127       supported  for  bus elements (signals of kind bus). This is because the
128       VHDL default disconnection time is null and  this  can  generate  unex‐
129       pected behavior for sequential elements.
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131
132       In  selected  signal assignment, only uniform delays are supported (the
133       same After clause in all assignments).
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135
136       Transport option is not supported. All delays are inertial delays.
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138       ASSERT STATEMENT
139       Only two severity levels are supported in concurrent assert statements:
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141       warning        print a warning message if the assert condition  is  not
142                      satisfied.
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144       error          print  an  error  message if the assert condition is not
145                      satisfied. Then, stop the simulation.
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147
148       Assert statements are ignored by the logic synthesis tool.
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150
151       DON'T CARE
152       A special feature has been introduced in order to  allow  "don't  care"
153       specification  when  the  logic  synthtizer is targeted ( Beware : this
154       feature is incompatible with the IEEE VHDL standard !!).
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156
157       An output can be assigned to the value 'D' (don't care). This is  taken
158       into  account  by the logic synthesis tool in the optimization process.
159       When the value of an output is 'D' the logic synthesis tool may turn it
160       into a '1' or a '0'.
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162
163       A 'D' value is understood as a '0' by the logic simulator (asimut).
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165
166       ARRAIES
167       Arraies  other  than  bit_vector, reg_vector, mux_vector and wor_vector
168       are not supported.
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170

EXAMPLES

172       Here is the description of an adder with an accumulator register.
173
174       entity add_accu is
175       port (
176         clk      : in  bit;
177         command  : in  bit;
178         data_in  : in  bit_vector (31 downto 0);
179         data_out : out bit_vector (31 downto 0);
180         cry_out  : out bit;
181         vdd      : in  bit;
182         vss      : in  bit
183         );
184       end add_accu;
185
186       architecture data_flow of add_accu is
187
188       signal eff_data  : bit_vector (31 downto 0);      -- effective operande
189       signal adder_out : bit_vector (31 downto 0);      -- adder's result
190       signal adder_cry : bit_vector (32 downto 0);      -- adder's carry
191       signal accum_reg : reg_vector (31 downto 0) register;  -- accumulator
192
193       constant initialize : bit := '0';
194       constant accumulate : bit := '1';
195
196       begin
197
198         -- select the effective operand
199
200         with command select
201         eff_data <= X"0000_0000" when initialize,
202                     accum_reg    when accumulate;
203
204         -- compute the result out of the adder
205
206         adder_out               <= eff_data xor data_in xor adder_cry;
207         adder_cry (0)           <= '0';
208         adder_cry (32 downto 1) <= (eff_data and adder_cry (31 downto 0)) or
209                                    (data_in  and adder_cry (31 downto 0)) or
210                                    (aff_data and data_in                ) ;
211
212         -- write the result into the register on the rising edge of clk
213
214         write : block (clk = '1' and not clk'STABLE)
215         begin
216           accum_reg <= guarded adder_out;
217         end block;
218
219         -- assign outputs
220
221         cry_out  <= adder_cry (32);
222         data_out <= accum_reg     ;
223
224         -- check power supply
225
226         assert (vdd = '1' and vss = '0')
227         report "power sypply is missing"
228         severity ERROR;
229
230       end;
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NAME

DESCRIPTION

EXAMPLES

SEE ALSO