1iverilog(1) $Date: 2007/03/22 16:08:18 $ iverilog(1)
2
6 iverilog - Icarus Verilog compiler
7
10 iverilog [-ESVv] [-Bpath] [-ccmdfile] [-g1|-g2|-g2x|-gspecify-gxtypes]
11 [-Dmacro[=defn]] [-pflag=value] [-Iincludedir] [-mmodule] [-Mfile]
12 [-Nfile] [-ooutputfilename] [-stopmodule] [-ttype] [-Tmin/typ/max]
13 [-Wclass] [-ypath] sourcefile
14
17 iverilog is a compiler that translates Verilog source code into exe‐
18 cutable programs for simulation, or other netlist formats for further
19 processing. The currently supported targets are vvp for simulation, and
20 xnf and fpga for synthesis. Other target types are added as code gener‐
21 ators are implemented.
22
25 iverilog accepts the following options:
26 -Bbase The iverilog program uses external programs and configuration
28 files to preprocess and compile the Verilog source. Normally,
29 the path used to locate these tools is built into the iverilog
30 program. However, the -B switch allows the user to select a
31 different set of programs. The path given is used to locate
32 ivlpp, ivl, code generators and the VPI modules.
33 -cfile This flag specifies an input file that contains a list of Ver‐
35 ilog source files. This is similar to the command file of other
36 Verilog simulators, in that it is a file that contains the file
37 names instead of taking them on the command line. See Command
38 Files below.
39 -Dmacro Defines macro macro with the string `1' as its definition. This
41 form is normally only used to trigger ifdef conditionals in the
42 Verilog source.
43 -Dmacro=defn
45 Defines macro macro as defn.
46 -E Preprocess the Verilog source, but do not compile it. The out‐
48 put file is the Verilog input, but with file inclusions and
49 macro references expanded and removed. This is useful, for
50 example, to preprocess Verilog source for use by other compil‐
51 ers.
52 -g1|-g2|-g2x
54 Select the Verilog language generation to support in the com‐
55 piler. This selects between IEEE1364-1995(1), IEEE1364-2001(2),
56 or Verilog with extension(2x). Normally, Icarus Verilog
57 defaults to the latest known generation of the language. This
58 flag is most useful to restrict the language to a set supported
59 by tools of specific generations, for compatibility with other
60 tools.
61 -gspecify|-gno-specify
63 Enable (default) or disable specify block support. When
64 enabled, specify block code is elaborated. When disabled, spec‐
65 ify blocks are parsed but ignored. Specify blocks are commonly
66 not needed for RTL simulation, and in fact can hurt performance
67 of the simulation. However, disabling specify blocks reduces
68 accuracy of full-timing simulations.
69 -gxtypes|-gno-xtypes
71 Enable (default) or disable support for extended types.
72 Enabling extended types allows for new types that are supported
73 by Icarus Verilog as extensions beyond the baseline Verilog. It
74 may be necessary to disable extended types if compiling code
75 that clashes with the few new keywords used to implement the
76 type system.
77 -Iincludedir
79 Append directory includedir to list of directories searched for
80 Verilog include files. The -I switch may be used many times to
81 specify several directories to search, the directories are
82 searched in the order they appear on the command line.
83 -Mpath Write into the file specified by path a list of files that con‐
85 tribute to the compilation of the design. This includes files
86 that are included by include directives and files that are
87 automatically loaded by library support. The output is one file
88 name per line, with no leading or trailing space.
89 -mmodule
91 Add this module to the list of VPI modules to be loaded by the
92 simulation. Many modules can be specified, and all will be
93 loaded, in the order specified. The system module is implicit
94 and always included.
95 -Npath This is used for debugging the compiler proper. Dump the final
97 netlist form of the design to the specified file. It otherwise
98 does not affect operation of the compiler. The dump happens
99 after the design is elaborated and optimized.
100 -o filename
102 Place output in the file filename. If no output file name is
103 specified, iverilog uses the default name a.out.
104 -pflag=value
106 Assign a value to a target specific flag. The -p switch may be
107 used as often as necessary to specify all the desired flags.
108 The flags that are used depend on the target that is selected,
109 and are described in target specific documentation. Flags that
110 are not used are ignored.
111 -S Synthesize. Normally, if the target can accept behavioral
113 descriptions the compiler will leave processes in behavioral
114 form. The -S switch causes the compiler to perform synthesis
115 even if it is not necessary for the target. If the target type
116 is a netlist format, the -S switch is unnecessary and has no
117 effect.
118 -s topmodule
120 Specify the top level module to elaborate. Icarus Verilog will
121 by default choose modules that are not instantiated in any
122 other modules, but sometimes that is not sufficient, or instan‐
123 tiates too many modules. If the user specifies one or more root
124 modules with -s flags, then they will be used as root modules
125 instead.
126 -Tmin|typ|max
128 Use this switch to select min, typ or max times from
129 min:typ:max expressions. Normally, the compiler will simply use
130 the typ value from these expressions (with a warning) but this
131 switch will tell the compiler explicitly which value to use.
132 This will suppress the warning that the compiler is making a
133 choice.
134 -ttarget
136 Use this switch to specify the target output format. See the
137 TARGETS section below for a list of valid output formats.
138 -v Turn on verbose messages. This will print the command lines
140 that are executed to perform the actual compilation, along with
141 version information from the various components, as well as the
142 version of the product as a whole. You will notice that the
143 command lines include a reference to a key temporary file that
144 passes information to the compiler proper. To keep that file
145 from being deleted at the end of the process, provide a file
146 name of your own in the environment variable IVERILOG_ICONFIG.
147 -V Print the version of the compiler, and exit.
149 -Wclass Turn on different classes of warnings. See the WARNING TYPES
151 section below for descriptions of the different warning groups.
152 If multiple -W switches are used, the warning set is the union
153 of all the requested classes.
154 -ylibdir
156 Append the directory to the library module search path. When
157 the compiler finds an undefined module, it looks in these
158 directories for files with the right name.
159
162 The Icarus Verilog compiler supports module libraries as directories
163 that contain Verilog source files. During elaboration, the compiler
164 notices the instantiation of undefined module types. If the user speci‐
165 fies library search directories, the compiler will search the directory
166 for files with the name of the missing module type. If it finds such a
167 file, it loads it as a Verilog source file, they tries again to elabo‐
168 rate the module.
169 Library module files should contain only a single module, but this is
171 not a requirement. Library modules may reference other modules in the
172 library or in the main design.
173
176 The Icarus Verilog compiler supports a variety of targets, for differ‐
177 ent purposes, and the -t switch is used to select the desired target.
178 null The null target causes no code to be generated. It is useful
181 for checking the syntax of the Verilog source.
182 vvp This is the default. The vvp target generates code for the vvp
184 runtime. The output is a complete program that simulates the
185 design but must be run by the vvp command.
186 xnf This is the Xilinx Netlist Format used by many tools for plac‐
188 ing devices in FPGAs or other programmable devices. This target
189 is obsolete, use the fpga target instead.
190 fpga This is a synthesis target that supports a variety of fpga
192 devices, mostly by EDIF format output. The Icarus Verilog fpga
193 code generator can generate complete designs or EDIF macros
194 that can in turn be imported into larger designs by other
195 tools. The fpga target implies the synthesis -S flag.
196
199 These are the types of warnings that can be selected by the -W switch.
200 All the warning types (other than all) can also be prefixed with no- to
201 turn off that warning. This is most useful after a -Wall argument to
202 suppress isolated warning types.
203 all This enables all supported warning categories.
206 implicit
209 This enables warnings for creation of implicit declarations.
210 For example, if a scalar wire X is used but not declared in the
211 Verilog source, this will print a warning at its first use.
212 portbind
215 This enables warnings for ports of module instantiations that
216 are not connected but probably should be. Dangling input ports,
217 for example, will generate a warning.
218 timescale
221 This enables warnings for inconsistent use of the timescale
222 directive. It detects if some modules have no timescale, or if
223 modules inherit timescale from another file. Both probably mean
224 that timescales are inconsistent, and simulation timing can be
225 confusing and dependent on compilation order.
226
229 If the source file name as a .sft suffix, then it is taken to be a sys‐
230 tem function table file. A System function table file is used to
231 describe to the compiler the return types for system functions. This is
232 necessary because the compiler needs this information to elaborate
233 expressions that contain these system functions, but cannot run the
234 sizetf functions since it has no run-time.
235 The format of the table is ASCII, one function per line. Empty lines
237 are ignored, and lines that start with the '#' character are comment
238 lines. Each non-comment line starts with the function name, then the
239 vpi type (i.e. vpiSysFuncReal). The following types are supported:
240 vpiSysFuncReal
243 The function returns a real/realtime value.
244 vpiSysFuncInt
247 The function returns an integer.
248 vpiSysFuncSized <wid> <signed|unsigned>
251 The function returns a vector with the given width, and is
252 signed or unsigned according to the flag.
253
256 The command file allows the user to place source file names and certain
257 command line switches into a text file instead of on a long command
258 line. Command files can include C or C++ style comments, as well as #
259 comments, if the # starts the line.
260 file name
263 A simple file name or file path is taken to be the name of a
264 Verilog source file. The path starts with the first non-white-
265 space character. Variables are substituted in file names.
266 -y libdir
269 A -y token prefixes a library directory in the command file,
270 exactly like it does on the command line. The parameter to the
271 -y flag may be on the same line or the next non-comment line.
272 Variables in the libdir are substituted.
274 +incdir+includedir
277 The +incdir+ token in command files gives directories to search
278 for include files in much the same way that -I flags work on
279 the command line. The difference is that multiple +includedir
280 directories are valid parameters to a single +incdir+ token,
281 although you may also have multiple +incdir+ lines.
282 Variables in the includedir are substituted.
284 +libext+ext
287 The +libext token in command files fives file extensions to try
288 when looking for a library file. This is useful in conjunction
289 with -y flags to list suffixes to try in each directory before
290 moving on to the next library directory.
291 +libdir+dir
294 This is another way to specify library directories. See the -y
295 flag.
296 +libdir-nocase+dir
299 This is like the +libdir statement, but file names inside the
300 directories declared here are case insensitive. The missing
301 module name in a lookup need not match the file name case, as
302 long as the letters are correct. For example, "foo" matches
303 "Foo.v" but not "bar.v".
304 +define+NAME=value
307 The +define+ token is the same as the -D option on the command
308 line. The value part of the token is optional.
309 +toupper-filename
312 This token causes file names after this in the command file to
313 be translated to uppercase. This helps with situations where a
314 directory has passed through a DOS machine, and in the process
315 the file names become munged.
316 +tolower-filename
319 This is similar to the +toupper-filename hack described above.
320 +integer-width+value
323 This allows the programmer to select the width for integer
324 variables in the Verilog source. The default is 32, the value
325 can be any desired integer value.
326
329 In certain cases, iverilog supports variables in command files. These
330 are strings of the form "$(varname)", where varname is the name of the
331 environment variable to read. The entire string is replaced with the
332 contents of that variable. Variables are only substituted in contexts
333 that explicitly support them, including file and directory strings.
334 Variable values come from the operating system environment, and not
336 from preprocessor defines elsewhere in the file or the command line.
337
340 These examples assume that you have a Verilog source file called
341 hello.v in the current directory
342 To compile hello.v to an executable file called a.out:
344 iverilog hello.v
346 To compile hello.v to an executable file called hello:
348 iverilog -o hello hello.v
350 To compile and run explicitly using the vvp runtime:
352 iverilog -ohello.vvp -tvvp hello.v
354 To compile hello.v to a file in XNF-format called hello.xnf
356 iverilog -txnf -ohello.xnf hello.v
358
362 Steve Williams (steve@icarus.com)
363
366 vvp(1), <http://www.icarus.com/eda/verilog/>
367
370 Copyright © 2002 Stephen Williams
371 This document can be freely redistributed according to the terms of the
373 GNU General Public License version 2.0
374Version $Date: 2007/03/22 16:08:18 $ iverilog(1)