1RDTSET(8) System Manager's Manual RDTSET(8)
2
6 rtdset - Task CPU affinity and Intel(R) Resource Director Technology
7 control tool
8
10 rdtset <-t feature=value;...cpu=cpulist>... -c <cpulist> (-p <pid> |
11 [-k] cmd [<args>...])
12 rdtset -r <cpulist> <-t feature=value;...cpu=cpulist>... -c <cpulist>
13 (-p <pid> | [-k] cmd [<args>...])
14 rdtset -r <cpulist> -c <cpulist> (-p <pid> | [-k] cmd [<args>...])
15 rdtset -r <cpulist> <-t feature=value;...cpu=cpulist>... -p <pid>
16
18 For more details on Intel(R) Resource Director Technology see
19 http://www.intel.com/content/www/us/en/architecture-and-technol‐
20 ogy/resource-director-technology.html
21 or https://github.com/01org/intel-cmt-cat/wiki
22 The rdtset tool provides support to set up the CAT (Cache Allocation
24 Technology) capabilities for a task and set its CPU affinity. Current
25 RDT/CAT operations of the utility are based on controlling MSR regis‐
26 ters (via libpqos library). Class of service 0 (CLOS0) is assumed as
27 default one. In command mode, rdtset forks and one process executes
28 the command. Another process waits for the task to terminate and
29 restores default CAT state by assigning cpu's back to CLOS0. This
30 behavior is not in place in PID mode.
31
33 rdtset options are as follow:
34 -h, --help
36 Show help
37 -v, --verbose
39 Verbose mode
40 -t , --rdt feature=value;...cpu=cpulist
42 Specify RDT configuration, single class configuration per -t,
43 multiple -t options allowed.
44 Accepted values for features:
45 2, l2 for level 2 cache
46 3, l3 for level 3 cache
47 For example:
49 -t 'l3=0xf;cpu=1'
51 CPU 1 uses four L3 cache-ways (mask 0xf)
52 -t 'l3=0xf;cpu=2' -t 'l3=0xf0;cpu=3,4,5'
54 CPU 2 uses four L3 cache-ways (mask 0xf), CPUs 3-5 share four L3
55 cache-ways (mask 0xf0), L3 cache-ways used by CPU 2 and 3-4 are
56 non-overlapping
57 -t 'l3=0xf;cpu=0-2' -t 'l3=0xf0;cpu=3,4,5'
59 CPUs 0-2 share four L3 cache-ways (mask 0xf), CPUs 3-5 share
60 four L3 cache-ways (mask 0xf0), L3 cache-ways used by CPUs 0-2
61 and 3-5 are non-overlapping
62 -t 'l3=0xf,0xf0;cpu=1'
64 On CDP enabled system, CPU 1 uses four cache-ways for code (mask
65 0xf) and four cache-ways for data (mask 0xf0), data and code
66 cache-ways are non-overlapping
67 -c <cpulist>, --cpu <cpulist>
69 Specify CPU affinity configuration, a numerical list of proces‐
70 sors. The numbers are separated by commas and may include
71 ranges. For example: 1-3,4,5.
72 -p <pid>, --pid <pid>
74 Operate on existing, given pid
75 -r <cpulist>, --reset <cpulist>
77 Reset CAT for CPUs (assign COS#0 to listed CPUs)
78 For example:
79 -r 0-5
81 Reset CAT configuration of CPUs 0-5
82 -r 0-5 -t 'l3=0xf0;cpu=0-5' -c 0-5 -p $BASHPID
84 Reconfigure CAT for CPUs 0-5
85 In order to reconfigure CAT, it is needed to reset current CAT
86 configuration
87 -k, --sudokeep
90 Do not drop sudo elevated privileges
91
93 CAT is configured using Model Specific Registers (MSRs) to set up the
94 class of service masks and manage the association of the cores/logical
95 threads to a class of service. The rdtset software executes in user
96 space, and access to the MSRs is obtained through a standard
97 Linux*/FreeBSD* interface. Under Linux, the virtual file system struc‐
98 ture /dev/cpu/CPUNUM/msr provides an interface to read and write the
99 MSRs, under FreeBSD it is /dev/cpuctlCPUNUM. The msr/cpuctl file
100 interface is protected and requires root privileges. The msr/cpuctl
101 driver might not be auto-loaded and on some modular kernels the driver
102 may need to be loaded manually:
103 Under Linux:
105 sudo modprobe msr
106 Under FreeBSD:
108 sudo kldload cpuctl
109
111 msr(4)
112
114 rdtset was written by Wojciech Andralojc <woj‐
115 ciechx.andralojc@intel.com>, Tomasz Kantecki <tomasz.kan‐
116 tecki@intel.com>
117 This is free software; see the source for copying conditions. There is
119 NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
120 PURPOSE.
121 September 20, 2016 RDTSET(8)