1VPASSERT(1) User Contributed Perl Documentation VPASSERT(1)
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6 vpassert - Preprocess Verilog code assertions
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9 vpassert [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [
10 files... ]
11
13 Vpassert will read the specified Verilog files and preprocess special
14 PLI assertions. The files are written to the directory named .vpassert
15 unless another name is given with -o. If a directory is passed, all
16 files in that directory will be preprocessed.
17
19 Standard VCS and GCC-like parameters are used to specify the files to
20 be preprocessed:
21 +libext+I<ext>+I<ext>... Specify extensions to be processed
23 -f I<file> Parse parameters in file
24 -v I<file> Parse the library file (I<file>)
25 -y I<dir> Parse all files in the directory (I<dir>)
26 -II<dir> Parse all files in the directory (I<dir>)
27 +incdir+I<dir> Parse all files in the directory (I<dir>)
28 To prevent recursion and allow reuse of the input.vc being passed to
30 the simulator, if the output directory is requested to be preprocessed,
31 that directory is simply ignored.
32 --allfiles
34 Preprocess and write out files that do not have any macros that
35 need expanding. By default, files that do not need processing are
36 not written out.
37 This option may speed up simulator compile times; the file will
39 always be found in the preprocessed directory, saving the compiler
40 from having to search a large number of -v directories to find it.
41 --chiponly
43 Special standalone chip compile
44 --date
46 Check file dates versus the last run of VPASSERT and don't process
47 if the given source file has not changed.
48 --exclude
50 Exclude processing any files which begin with the specified prefix.
51 --help
53 Displays this message and program version and exits.
54 --language <1364-1995|1364-2001|1364-2005|1800-2005>
56 Set the language standard for the files. This determines which
57 tokens are signals versus keywords, such as the ever-common "do"
58 (data-out signal, versus a do-while loop keyword).
59 --minimum
61 Include `__message_minimum in the $uinfo test, so that by defining
62 __message_minimum=1 some uinfos may be optimized away at compile
63 time.
64 --noline
66 Do not emit `line directives. If not specified they will be used
67 under --language 1364-2001 and later.
68 --nopli
70 Delete all 'simple' PLI calls. PLI function calls inside
71 parenthesis will not be changed, and thus may still need to be
72 manually ifdef'ed out. Useful for reducing the amount of `ifdef's
73 required to feed non-PLI competent synthesis programs.
74 --quiet
76 Suppress messages about what files are being preprocessed.
77 --nostop
79 By default, $error and $warn insert a $stop statement. With
80 --nostop, this is replaced by incrementing a variable, which may
81 then be used to conditionally halt simulation.
82 --o file
84 Use the given filename for output instead of the input name
85 .vpassert. If the name ends in a / it is used as a output
86 directory with the default name.
87 --realintent
89 Special RealIntent enable/disables added around unreachable code.
90 --timeformat-units units
92 If specified, include Verilog $timeformat calls before all
93 messages. Use the provided argument as the units. Units is in
94 powers of 10, so -9 indicates to use nanoseconds.
95 --timeformat-precision prec
97 When using --timeformat-units, use this as the precision value, the
98 number of digits after the decimal point. Defaults to zero.
99 --vericov
101 Special Vericov enable/disables added around unreachable code.
102 --verilator
104 Special Verilator translations enabled.
105 --version
107 Displays program version and exits.
108
110 These Verilog pseudo-pli calls are expanded:
111 $uassert (case, "message", [vars...] )
113 Report a $uerror if the given case is FALSE. (Like assert() in C.)
114 $uassert_amone (sig, [sig...], "message", [vars...] )
116 Report a $uerror if more than one signal is asserted, or any are X.
117 (None asserted is ok.) The error message will include a binary
118 display of the signal values.
119 $uassert_info (case, "message", [vars...] )
121 Report a $uinfo if the given case is FALSE. (Like assert() in C.)
122 $uassert_onehot (sig, [sig...], "message", [vars...] )
124 Report a $uerror if other than one signal is asserted, or any are
125 X. The error message will include a binary display of the signal
126 values.
127 $uassert_req_ack (req_sig, ack_sig, [data_sig,...] )
129 Check for a single cycle request pulse, followed by a single cycle
130 acknowledgment pulse. Do not allow any of the data signals to
131 change between the request and acknowledgement.
132 $ucheck_ilevel (level )
134 Return true if the __message level is greater or equal to the given
135 level, and that global messages are turned on.
136 $ucover_clk (clock, label)
138 Similar to $uerror_clk, add a SystemVerilog assertion at the next
139 specified clock's edge, with the label specified. This allows cover
140 properties to be specified "inline" with normal RTL code.
141 $ucover_foreach_clk (clock, label, "msb:lsb", (... $ui ...))
143 Similar to $ucover_clk, however cover a range where $ui in the
144 expression is replaced with the range index.
145 Range is "msb:lsb" to indicate from msb downto lsb inclusive,
147 and/or a comma separated list of values.
148 Similar to:
150 for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin
152 if (expression with $ui)
153 $ucover_clk(clock, label ## "_" ## bit)
154 end
155 However there's no way to form a label from a for loop (as
157 psudocoded with ## above), thus this macro.
158 $ui Loop index used inside $ucover_foreach_clk.
160 $uinfo (level, "message", [vars...] )
162 Report a informational message in standard form. End test if
163 warning limit exceeded.
164 $uerror ("message", [vars...] )
166 Report a error message in standard form. End test if error limit
167 exceeded.
168 $uerror_clk (clock, "message", [vars...] )
170 Report a error message in standard form at the next clock edge. If
171 you place a $uerror etc in a combo logic block (always @*), event
172 based simulators may misfire the assertion due to glitches.
173 $uerror_clk fixes this by instead creating a temporary signal and
174 then moving the assert itself to a new clocked block at the
175 specified edge. Note any variables printed will be the values at
176 the time of the next clock edge, which may differ from the value
177 where the $uerror_clk is assigned.
178 $uwarn ("message", [vars...] )
180 Report a warning message in standard form.
181 $uwarn_clk (clock "message", [vars...] )
183 Report a warning message in standard form at the next clock edge.
184 See $uerror_clk.
185
187 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
188 software tool suite. The latest version is available from CPAN and
189 from http://www.veripool.org/verilog-perl
190 <http://www.veripool.org/verilog-perl>.
191 Copyright 2000-2009 by Wilson Snyder. This package is free software;
193 you can redistribute it and/or modify it under the terms of either the
194 GNU Lesser General Public License Version 3 or the Perl Artistic
195 License Version 2.0.
196
198 Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi
199 <duane.galbi@conexant.com>
200
202 Verilog-Perl, Verilog::Parser, Verilog::Pli
203perl v5.12.0 2009-07-20 VPASSERT(1)