Verilog::Netlist(3pm)

1Netlist(3)            User Contributed Perl Documentation           Netlist(3)
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NAME

6       Verilog::Netlist - Verilog Netlist
7

SYNOPSIS

9           use Verilog::Netlist;
10
11           # Setup options so files can be found
12           use Verilog::Getopt;
13           my $opt = new Verilog::Getopt;
14           $opt->parameter( "+incdir+verilog",
15                            "-y","verilog",
16                            );
17
18           # Prepare netlist
19           my $nl = new Verilog::Netlist (options => $opt,);
20           foreach my $file ('testnetlist.v') {
21               $nl->read_file (filename=>$file);
22           }
23           # Read in any sub-modules
24           $nl->link();
25           $nl->lint();
26           $nl->exit_if_error();
27
28           foreach my $mod ($nl->top_modules_sorted) {
29               show_hier ($mod, "  ", "", "");
30           }
31
32           sub show_hier {
33               my $mod = shift;
34               my $indent = shift;
35               my $hier = shift;
36               my $cellname = shift;
37               if (!$cellname) {$hier = $mod->name;} #top modules get the design name
38               else {$hier .= ".$cellname";} #append the cellname
39               printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
40               foreach my $sig ($mod->ports_sorted) {
41                   printf ($indent."     %sput %s\n", $sig->direction, $sig->name);
42               }
43               foreach my $cell ($mod->cells_sorted) {
44                   printf ($indent. "    Cell %s\n", $cell->name);
45                   foreach my $pin ($cell->pins_sorted) {
46                       printf ($indent."     .%s(%s)\n", $pin->name, $pin->netname);
47                   }
48                   show_hier ($cell->submod, $indent."  ", $hier, $cell->name) if $cell->submod;
49               }
50           }
51

DESCRIPTION

53       Verilog::Netlist reads and holds interconnect information about a whole
54       design database.
55
56       See the "Which Package" section of Verilog::Language if you are unsure
57       which parsing package to use for a new application.
58
59       A Verilog::Netlist is composed of files, which contain the text read
60       from each file.
61
62       A file may contain modules, which are individual blocks that can be
63       instantiated (designs, in Synopsys terminology.)
64
65       Modules have ports, which are the interconnection between nets in that
66       module and the outside world.  Modules also have nets, (aka signals),
67       which interconnect the logic inside that module.
68
69       Modules can also instantiate other modules.  The instantiation of a
70       module is a Cell.  Cells have pins that interconnect the referenced
71       module's pin to a net in the module doing the instantiation.
72
73       Each of these types, files, modules, ports, nets, cells and pins have a
74       class.  For example Verilog::Netlist::Cell has the list of
75       Verilog::Netlist::Pin (s) that interconnect that cell.
76

FUNCTIONS

78       See also Verilog::Netlist::Subclass for additional accessors and
79       methods.
80
81       $netlist->lint
82           Error checks the entire netlist structure.
83
84       $netlist->link()
85           Resolves references between the different modules.
86
87           If link_read=>1 is passed when netlist->new is called (it is by
88           default), undefined modules will be searched for using the
89           Verilog::Getopt package, passed by a reference in the creation of
90           the netlist.  To suppress errors in any missing references, set
91           link_read_nonfatal=>1 also.
92
93           If keep_comments=>1 is passed, comment fields will be entered on
94           net declarations into the Vtest::Netlist::Net structures.
95           Otherwise all comments are stripped for speed.
96
97       $netlist->new
98           Creates a new netlist structure.  Pass optional parameters by name,
99           with the following parameters:
100
101           options => $opt_object
102                   An optional pointer to a Verilog::Getopt object, to be used
103                   for locating files.
104
105           implicit_wires_ok => $true_or_false
106                   Indicates whether to allow undeclared wires to be used.
107
108           logger => object
109                   Specify a message handler object to be used for error
110                   handling, this class should be a Verilog::Netlist::Logger
111                   object, or derived from one.  If unspecified, a
112                   Verilog::Netlist::Logger local to this netlist will be
113                   used.
114
115           preproc => $package_name
116                   The name of the preprocessor class. Defaults to
117                   "Verilog::Preproc".
118
119           link_read => $true_or_false
120                   Indicates whether or not the parser should automatically
121                   search for undefined modules through the "options" object.
122
123           include_open_nonfatal => $true_or_false
124                   Indicates that include files that do not exist should be
125                   ignored.
126
127           keep_comments => $true_or_false
128                   Indicates that comments should be preserved in the
129                   structure (slower).
130
131           link_read_nonfatal => $true_or_false
132                   Indicates that modules that referenced but not found should
133                   be ignored, rather than causing an error message.
134
135       $netlist->dump
136           Prints debugging information for the entire netlist structure.
137

INTERFACE FUNCTIONS

139       $netlist->find_interface($name)
140           Returns Verilog::Netlist::Interface matching given name.
141
142       $netlist->interfaces
143           Returns list of Verilog::Netlist::Interface.
144
145       $netlist->interfaces_sorted
146           Returns name sorted list of Verilog::Netlist::Interface.
147
148       $netlist->new_interface
149           Creates a new Verilog::Netlist::Interface.
150

MODULE FUNCTIONS

152       $netlist->find_module($name)
153           Returns Verilog::Netlist::Module matching given name.
154
155       $netlist->modules
156           Returns list of Verilog::Netlist::Module.
157
158       $netlist->modules_sorted
159           Returns name sorted list of Verilog::Netlist::Module.
160
161       $netlist->modules_sorted_level
162           Returns level sorted list of Verilog::Netlist::Module.  Leaf
163           modules will be first, the top most module will be last.
164
165       $netlist->new_module
166           Creates a new Verilog::Netlist::Module.
167
168       $netlist->top_modules_sorted
169           Returns name sorted list of Verilog::Netlist::Module, only for
170           those modules which have no children and are not unused library
171           cells.
172

FILE FUNCTIONS

174       $netlist->dependency_write(filename)
175           Writes a dependency file for make, listing all input and output
176           files.
177
178       $netlist->defvalue_nowarn (define)
179           Return the value of the specified define or undef.
180
181       $netlist->dependency_in(filename)
182           Adds an additional input dependency for dependency_write.
183
184       $netlist->dependency_out(filename)
185           Adds an additional output dependency for dependency_write.
186
187       $netlist->files
188           Returns list of Verilog::Netlist::File.
189
190       $netlist->files_sorted
191           Returns a name sorted list of Verilog::Netlist::File.
192
193       $netlist->find_file($name)
194           Returns Verilog::Netlist::File matching given name.
195
196       $netlist->read_file( filename=>$name)
197           Reads the given Verilog file, and returns a Verilog::Netlist::File
198           reference.
199
200           Generally called as $netlist->read_file.  Pass a hash of
201           parameters.  Reads the filename=> parameter, parsing all
202           instantiations, ports, and signals, and creating
203           Verilog::Netlist::Module structures.
204
205       $netlist->read_libraries ()
206           Read any libraries specified in the options=> argument passed with
207           the netlist constructor.  Automatically invoked when netlist
208           linking results in a module that wasn't found, and thus might be
209           inside the libraries.
210
211       $netlist->remove_defines (string)
212           Expand any `defines in the string and return the results.
213           Undefined defines will remain in the returned string.
214
215       $netlist->resolve_filename (string, [lookup_type])
216           Convert a module name to a filename.  Optional lookup_type is
217           'module', 'include', or 'all', to use only module_dirs, incdirs, or
218           both for the lookup.  Return undef if not found.
219
220       $self->verilog_text
221           Returns verilog code which represents the netlist.
222

BUGS

224       Cell instantiations without any arguments are not supported, a empty
225       set of parenthesis are required.  (Use "cell cell();", not "cell
226       cell;".)
227
228       Order based pin interconnect is not supported, use name based
229       connections.
230

DISTRIBUTION

232       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
233       software tool suite.  The latest version is available from CPAN and
234       from http://www.veripool.org/verilog-perl
235       <http://www.veripool.org/verilog-perl>.
236
237       Copyright 2000-2009 by Wilson Snyder.  This package is free software;
238       you can redistribute it and/or modify it under the terms of either the
239       GNU Lesser General Public License Version 3 or the Perl Artistic
240       License Version 2.0.
241

AUTHORS

243       Wilson Snyder <wsnyder@wsnyder.org>
244