1SigParser(3) User Contributed Perl Documentation SigParser(3)
2
6 Verilog::SigParser - Signal Parsing for Verilog language files
7
9 use Verilog::Preproc;
10 use Verilog::SigParser;
11 my $pp = Verilog::Preproc->new(keep_comments=>0,);
13 my $parser = new Verilog::SigParser;
15 $parser->parse_preproc_file ($pp);
16 # The below described callbacks are then invoked
17
19 Verilog::SigParser builds upon the Verilog::Parser module to provide
20 callbacks for when a signal is declared, a module instantiated, or a
21 module defined.
22 See the "Which Package" section of Verilog::Language if you are unsure
24 which parsing package to use for a new application. For a higher level
25 interface to this package, see Verilog::Netlist.
26
28 The method interface to Verilog::SigParser is described in the
29 Verilog::Parser module which this package inherits. You will probably
30 want to use the preprocessing option of Verilog::Parser with this
31 package.
32
34 In order to make the parser do anything interesting, you must make a
35 subclass where you override one or more of the following methods as
36 appropriate.
37 Note Verilog::Parser callbacks also are invoked when SigParser is
39 parsing.
40 $self->attribute ( $text )
42 Scanned an attribute or meta-comment. The parser inspects the
43 first word of each comment line ("//key rest" to end of line) or
44 comment block ("/*key rest */). It calls "$self-"attribute(
45 meta_text )" if the first word has a true value in hash
46 "$self-"metacomment>.
47 $self->endcell ( $token )
49 This method is called at the end of defining a cell. It is useful
50 for writing clean up routines.
51 $self->endinterface ( $token )
53 This method is called at a endinterface keyword. It is useful for
54 writing clean up routines.
55 $self->endtaskfunc ( $token )
57 This method is called at a endfunction or endtask keyword. It is
58 useful for writing clean up routines.
59 $self->endmodule ( $token )
61 This method is called at a endmodule keyword. It is useful for
62 writing clean up routines.
63 $self->endpackage ( $token )
65 This method is called at a endpackage keyword. It is useful for
66 writing clean up routines.
67 $self->endprogram ( $token )
69 This method is called at a endprogram keyword. It is useful for
70 writing clean up routines.
71 $self->function ( $keyword, $name, $data-type )
73 This method is called when a function is defined. Type is the
74 output size or typename, plus "signed", for example "", "[3:0]",
75 "integer", or "signed [2:0]".
76 $self->import ( $package, $id )
78 This method is called when an import is defined.
79 $self->instant ( $module, $cell, $range )
81 This method is called when a instantiation is defined. The first
82 parameter is the name of the module being instantiated. The second
83 parameter is the name of the cell, which may be "" for primitives.
84 The third is the range if the cell was arrayed.
85 Prior to version 3.000, the name of the parameters were also
87 included in this callback. This has been replaced with the parampin
88 callback.
89 $self->interface ( $keyword, $name )
91 This method is called when an interface is defined.
92 $self->module ( $keyword, $name, ignored, $in_celldefine )
94 This method is called when a module is defined.
95 $self->package ( $keyword, $name )
97 This method is called when a package is defined.
98 $self->parampin ( $name, $connection, $index )
100 This method is called when a parameter is connected to an
101 instantiation, IE the "#(...)" syntax. It is also used for UDP
102 delays (Three calls for "#(delay0,delay1,delay2)"), as the parser
103 does not know if the instantiation is for an UDP versus a module.
104 $self->pin ( $name, $connection, $index )
106 This method is called when a pin on a instant is defined. If a pin
107 name was not provided and the connection is by position, name will
108 be '' or undef.
109 $self->port ( $name, $objof, $direction, $data_type, $array, $pinnum )
111 This method is called when a module port is defined. It may be
112 called twice on a port if the 1995 style is used; the first call is
113 made at the port header, the second call at the input/output
114 declaration.
115 The first argument $name, is the name of the port. $objof is what
117 the port is an object of ('module', 'function', etc). $direction
118 is the port direction ('input', 'output', 'inout', 'ref', 'const
119 ref'). $data_type is the data type ('reg', 'user_type_t', 'signed
120 [31:0]', etc). $array is the arraying of the port ('[1:0][2:0]',
121 '', etc). $pinnum is set to the pin number for ANSI style
122 declarations, and 0 for Verilog 1995 declarations made outside the
123 port list.
124 $self->ppdefine ( $defvar, $definition )
126 This method is called when a preprocessor definition is
127 encountered.
128 $self->program ( $keyword, $name )
130 This method is called when a program is defined.
131 $self->signal_decl ( $keyword, $signame, $vector, $mem, $signed, $value
133 )
134 This method is no longer used, see $self->var.
135 $self->task ( $keyword, $name )
137 This method is called when a task is defined.
138 $self->var ( $kwd, $name, $objof, $nettype, $data_type, $array, $value
140 )
141 This method is called when a variable or net is defined.
142 The first argument $kwd is how it was declared ('port', 'var',
144 'genvar', 'parameter', 'localparam', 'typedef') or if applicable a
145 net type ('supply0', 'wire', etc). $name is the name of the
146 variable. $objof is what the variable is an object of ('module',
147 'function', etc). $nettype is the net type if any was defined ('',
148 'supply0', 'wire', 'tri', etc). $data_type is the data type
149 ('user_type_t', '[31:0] signed', etc). $array is the arraying of
150 the variable which is the text AFTER the variable name
151 ('[1:0][2:0]', '', etc). $value is what the variable was assigned
152 to ('', or expression).
153 Note typedefs are included here, because "parameter type" is both a
155 variable and a type declaration.
156 Below are some example declarations and the callbacks:
158 reg [4:0] vect = 5'b10100;
160 # VAR 'var' 'vect' 'module' '' 'reg [4:0]' '' '5'b10100'
161 wire (weak0, weak1) value = pullval;
162 # VAR 'net' 'value' 'module' 'wire' '' '' 'pullval'
163 reg [1:0] mem [12:2];
164 # VAR 'var' 'mem' 'module' '' 'reg [1:0]' '[12:2]' ''
165 int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
166 # verilog/parser_sv.v:121: VAR 'var' 'n' 'module' '' 'int' '[1:2][1:3]' ''{'{0,1,2},'{3}}'
167 module ( output logic [SZ-1:0] o_sized );
168 # VAR 'port' 'o_sized' 'module' '' 'logic [SZ-1:0]' '' ''
169 struct packed signed { bit [7:0] m_b; };
170 # VAR 'member' 'm_b' 'struct' '' 'bit [7:0]' '' ''
171
173 This is being distributed as a baseline for future contributions.
174 Don't expect a lot, the Parser is still naive, and there are many
175 awkward cases that aren't covered.
176 Note the SigParser is focused on extracting signal information. It
178 does NOT extract enough information to derive general interconnect; for
179 example the contents of 'assign' statements are not parsed.
180
182 Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA
183 software tool suite. The latest version is available from CPAN and
184 from http://www.veripool.org/verilog-perl
185 <http://www.veripool.org/verilog-perl>.
186 Copyright 2000-2009 by Wilson Snyder. This package is free software;
188 you can redistribute it and/or modify it under the terms of either the
189 GNU Lesser General Public License Version 3 or the Perl Artistic
190 License Version 2.0.
191
193 Wilson Snyder <wsnyder@wsnyder.org>
194
196 Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist,
197 Verilog::Getopt
198perl v5.12.0 2009-07-20 SigParser(3)